[DAGCombine] Change isBuildVectorAll* -> isConstantSplatVectorAll* for Vselect (llvm#147305)

Change isBuildVectorAll* -> isConstantSplatVectorAll* in VSelect in case
the fold happens after BuildVector has been canonically transformed to
Splat or if the Splat is initially in vselect already

- Fixes llvm#73454
- Update related test cases, add extra tests in wasm

---------

Co-authored-by: Simon Pilgrim <[email protected]>

Author: badumbatish

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

@@ -13091,10 +13091,10 @@ static SDValue combineVSelectWithAllOnesOrZeros(SDValue Cond, SDValue TVal,
   EVT CondVT = Cond.getValueType();
   assert(CondVT.isVector() && "Vector select expects a vector selector!");
 
-  bool IsTAllZero = ISD::isBuildVectorAllZeros(TVal.getNode());
-  bool IsTAllOne = ISD::isBuildVectorAllOnes(TVal.getNode());
-  bool IsFAllZero = ISD::isBuildVectorAllZeros(FVal.getNode());
-  bool IsFAllOne = ISD::isBuildVectorAllOnes(FVal.getNode());
+  bool IsTAllZero = ISD::isConstantSplatVectorAllZeros(TVal.getNode());
+  bool IsTAllOne = ISD::isConstantSplatVectorAllOnes(TVal.getNode());
+  bool IsFAllZero = ISD::isConstantSplatVectorAllZeros(FVal.getNode());
+  bool IsFAllOne = ISD::isConstantSplatVectorAllOnes(FVal.getNode());
 
   // no vselect(cond, 0/-1, X) or vselect(cond, X, 0/-1), return
   if (!IsTAllZero && !IsTAllOne && !IsFAllZero && !IsFAllOne)

llvm/test/CodeGen/WebAssembly/fpclamptosat_vec.ll

@@ -107,11 +107,9 @@ define <2 x i32> @ustest_f64i32(<2 x double> %x) {
 ; CHECK-NEXT:    v128.bitselect
 ; CHECK-NEXT:    local.tee 0
 ; CHECK-NEXT:    v128.const 0, 0
-; CHECK-NEXT:    local.tee 1
-; CHECK-NEXT:    local.get 0
-; CHECK-NEXT:    local.get 1
 ; CHECK-NEXT:    i64x2.gt_s
-; CHECK-NEXT:    v128.bitselect
+; CHECK-NEXT:    local.get 0
+; CHECK-NEXT:    v128.and
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    i8x16.shuffle 0, 1, 2, 3, 8, 9, 10, 11, 0, 1, 2, 3, 0, 1, 2, 3
 ; CHECK-NEXT:    # fallthrough-return
@@ -1558,11 +1556,9 @@ define <2 x i32> @ustest_f64i32_mm(<2 x double> %x) {
 ; CHECK-NEXT:    v128.bitselect
 ; CHECK-NEXT:    local.tee 0
 ; CHECK-NEXT:    v128.const 0, 0
-; CHECK-NEXT:    local.tee 1
-; CHECK-NEXT:    local.get 0
-; CHECK-NEXT:    local.get 1
 ; CHECK-NEXT:    i64x2.gt_s
-; CHECK-NEXT:    v128.bitselect
+; CHECK-NEXT:    local.get 0
+; CHECK-NEXT:    v128.and
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    i8x16.shuffle 0, 1, 2, 3, 8, 9, 10, 11, 0, 1, 2, 3, 0, 1, 2, 3
 ; CHECK-NEXT:    # fallthrough-return

llvm/test/CodeGen/WebAssembly/simd-select.ll

@@ -552,3 +552,73 @@ define <2 x double> @select_eq_v2f64(i32 %i, <2 x double> %x, <2 x double> %y) {
   %res = select i1 %c, <2 x double> %x, <2 x double> %y
   ret <2 x double> %res
 }
+
+define <4 x i32> @select_splat_first_zero_and_icmp(<4 x i32> %x) {
+; CHECK-LABEL: select_splat_first_zero_and_icmp:
+; CHECK:         .functype select_splat_first_zero_and_icmp (v128) -> (v128)
+; CHECK-NEXT:  # %bb.0:
+; CHECK-NEXT:    local.get 0
+; CHECK-NEXT:    v128.const 2139095040, 2139095040, 2139095040, 2139095040
+; CHECK-NEXT:    v128.and
+; CHECK-NEXT:    v128.const 0, 0, 0, 0
+; CHECK-NEXT:    i32x4.ne
+; CHECK-NEXT:    local.get 0
+; CHECK-NEXT:    v128.and
+; CHECK-NEXT:    # fallthrough-return
+  %a = and <4 x i32> %x, splat (i32 2139095040)
+  %c = icmp eq <4 x i32> %a, zeroinitializer
+  %res = select <4 x i1> %c, <4 x i32> zeroinitializer, <4 x i32> %x
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @select_splat_second_zero_and_icmp(<4 x i32> %x) {
+; CHECK-LABEL: select_splat_second_zero_and_icmp:
+; CHECK:         .functype select_splat_second_zero_and_icmp (v128) -> (v128)
+; CHECK-NEXT:  # %bb.0:
+; CHECK-NEXT:    local.get 0
+; CHECK-NEXT:    v128.const 2139095040, 2139095040, 2139095040, 2139095040
+; CHECK-NEXT:    v128.and
+; CHECK-NEXT:    v128.const 0, 0, 0, 0
+; CHECK-NEXT:    i32x4.eq
+; CHECK-NEXT:    local.get 0
+; CHECK-NEXT:    v128.and
+; CHECK-NEXT:    # fallthrough-return
+  %a = and <4 x i32> %x, splat (i32 2139095040)
+  %c = icmp eq <4 x i32> %a, zeroinitializer
+  %res = select <4 x i1> %c, <4 x i32> %x, <4 x i32> zeroinitializer
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @select_splat_first_zero_cond_input(<4 x i1> %c, <4 x i32> %x) {
+; CHECK-LABEL: select_splat_first_zero_cond_input:
+; CHECK:         .functype select_splat_first_zero_cond_input (v128, v128) -> (v128)
+; CHECK-NEXT:  # %bb.0:
+; CHECK-NEXT:    v128.const 0, 0, 0, 0
+; CHECK-NEXT:    local.get 1
+; CHECK-NEXT:    local.get 0
+; CHECK-NEXT:    i32.const 31
+; CHECK-NEXT:    i32x4.shl
+; CHECK-NEXT:    i32.const 31
+; CHECK-NEXT:    i32x4.shr_s
+; CHECK-NEXT:    v128.bitselect
+; CHECK-NEXT:    # fallthrough-return
+  %res = select <4 x i1> %c, <4 x i32> zeroinitializer, <4 x i32> %x
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @select_splat_second_zero_cond_input(<4 x i1> %c, <4 x i32> %x) {
+; CHECK-LABEL: select_splat_second_zero_cond_input:
+; CHECK:         .functype select_splat_second_zero_cond_input (v128, v128) -> (v128)
+; CHECK-NEXT:  # %bb.0:
+; CHECK-NEXT:    local.get 0
+; CHECK-NEXT:    i32.const 31
+; CHECK-NEXT:    i32x4.shl
+; CHECK-NEXT:    i32.const 31
+; CHECK-NEXT:    i32x4.shr_s
+; CHECK-NEXT:    local.get 1
+; CHECK-NEXT:    v128.and
+; CHECK-NEXT:    # fallthrough-return
+  %res = select <4 x i1> %c, <4 x i32> %x, <4 x i32> zeroinitializer
+  ret <4 x i32> %res
+}
+