@@ -589,7 +589,7 @@ void RISCVDisassembler::addSPOperands(MCInst &MI) const {
589589 DESC, ADDITIONAL_OPERATION) \
590590 do { \
591591 if (FEATURE_CHECKS) { \
592- LLVM_DEBUG (dbgs () << " Trying " DESC " :\n " ); \
592+ LLVM_DEBUG (dbgs () << " Trying " << DESC << " table :\n " ); \
593593 DecodeStatus Result = \
594594 decodeInstruction (DECODER_TABLE, MI, Insn, Address, this , STI); \
595595 if (Result != MCDisassembler::Fail) { \
@@ -622,106 +622,96 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
622622 TRY_TO_DECODE (STI.hasFeature (RISCV::FeatureStdExtZdinx) &&
623623 !STI.hasFeature (RISCV::Feature64Bit),
624624 DecoderTableRV32Zdinx32,
625- " RV32Zdinx table (Double in Integer and rv32)" );
625+ " RV32Zdinx (Double in Integer and rv32)" );
626626 TRY_TO_DECODE (STI.hasFeature (RISCV::FeatureStdExtZacas) &&
627627 !STI.hasFeature (RISCV::Feature64Bit),
628628 DecoderTableRV32Zacas32,
629- " RV32Zacas table (Compare-And-Swap and rv32)" );
629+ " RV32Zacas (Compare-And-Swap and rv32)" );
630630 TRY_TO_DECODE_FEATURE (RISCV::FeatureStdExtZfinx, DecoderTableRVZfinx32,
631- " RVZfinx table (Float in Integer)" );
631+ " RVZfinx (Float in Integer)" );
632632 TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXVentanaCondOps,
633- DecoderTableXVentana32, " Ventana custom opcode table " );
633+ DecoderTableXVentana32, " XVentanaCondOps " );
634634 TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXTHeadBa, DecoderTableXTHeadBa32,
635- " XTHeadBa custom opcode table " );
635+ " XTHeadBa" );
636636 TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXTHeadBb, DecoderTableXTHeadBb32,
637- " XTHeadBb custom opcode table " );
637+ " XTHeadBb" );
638638 TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXTHeadBs, DecoderTableXTHeadBs32,
639- " XTHeadBs custom opcode table " );
639+ " XTHeadBs" );
640640 TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXTHeadCondMov,
641- DecoderTableXTHeadCondMov32,
642- " XTHeadCondMov custom opcode table" );
641+ DecoderTableXTHeadCondMov32, " XTHeadCondMov" );
643642 TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXTHeadCmo, DecoderTableXTHeadCmo32,
644- " XTHeadCmo custom opcode table " );
643+ " XTHeadCmo" );
645644 TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXTHeadFMemIdx,
646- DecoderTableXTHeadFMemIdx32,
647- " XTHeadFMemIdx custom opcode table" );
645+ DecoderTableXTHeadFMemIdx32, " XTHeadFMemIdx" );
648646 TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXTHeadMac, DecoderTableXTHeadMac32,
649- " XTHeadMac custom opcode table " );
647+ " XTHeadMac" );
650648 TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXTHeadMemIdx,
651- DecoderTableXTHeadMemIdx32,
652- " XTHeadMemIdx custom opcode table" );
649+ DecoderTableXTHeadMemIdx32, " XTHeadMemIdx" );
653650 TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXTHeadMemPair,
654- DecoderTableXTHeadMemPair32,
655- " XTHeadMemPair custom opcode table" );
651+ DecoderTableXTHeadMemPair32, " XTHeadMemPair" );
656652 TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXTHeadSync,
657- DecoderTableXTHeadSync32,
658- " XTHeadSync custom opcode table" );
653+ DecoderTableXTHeadSync32, " XTHeadSync" );
659654 TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXTHeadVdot,
660- DecoderTableXTHeadVdot32,
661- " XTHeadVdot custom opcode table" );
655+ DecoderTableXTHeadVdot32, " XTHeadVdot" );
662656 TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32,
663- " SiFive VCIX custom opcode table " );
657+ " SiFive VCIX" );
664658 TRY_TO_DECODE_FEATURE (
665659 RISCV::FeatureVendorXSfvqmaccdod, DecoderTableXSfvqmaccdod32,
666- " SiFive Matrix Multiplication (2x8 and 8x2) Instruction opcode table " );
660+ " SiFive Matrix Multiplication (2x8 and 8x2) Instruction" );
667661 TRY_TO_DECODE_FEATURE (
668662 RISCV::FeatureVendorXSfvqmaccqoq, DecoderTableXSfvqmaccqoq32,
669- " SiFive Matrix Multiplication (4x8 and 8x4) Instruction opcode table " );
670- TRY_TO_DECODE_FEATURE (
671- RISCV::FeatureVendorXSfvfwmaccqqq, DecoderTableXSfvfwmaccqqq32,
672- " SiFive Matrix Multiplication Instruction opcode table " );
673- TRY_TO_DECODE_FEATURE (
674- RISCV::FeatureVendorXSfvfnrclipxfqf, DecoderTableXSfvfnrclipxfqf32,
675- " SiFive FP32-to-int8 Ranged Clip Instructions opcode table " );
663+ " SiFive Matrix Multiplication (4x8 and 8x4) Instruction" );
664+ TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXSfvfwmaccqqq,
665+ DecoderTableXSfvfwmaccqqq32,
666+ " SiFive Matrix Multiplication Instruction" );
667+ TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXSfvfnrclipxfqf,
668+ DecoderTableXSfvfnrclipxfqf32,
669+ " SiFive FP32-to-int8 Ranged Clip Instructions" );
676670 TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXSiFivecdiscarddlone,
677671 DecoderTableXSiFivecdiscarddlone32,
678- " SiFive sf.cdiscard.d.l1 custom opcode table " );
672+ " SiFive sf.cdiscard.d.l1" );
679673 TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXSiFivecflushdlone,
680674 DecoderTableXSiFivecflushdlone32,
681- " SiFive sf.cflush.d.l1 custom opcode table " );
675+ " SiFive sf.cflush.d.l1" );
682676 TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXSfcease, DecoderTableXSfcease32,
683- " SiFive sf.cease custom opcode table " );
677+ " SiFive sf.cease" );
684678 TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXMIPSLSP, DecoderTableXmipslsp32,
685- " MIPS mips.lsp custom opcode table " );
679+ " MIPS mips.lsp" );
686680 TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXMIPSCMove,
687- DecoderTableXmipscmove32,
688- " MIPS mips.ccmov custom opcode table" );
681+ DecoderTableXmipscmove32, " MIPS mips.ccmov" );
689682 TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXCVbitmanip,
690- DecoderTableXCVbitmanip32,
691- " CORE-V Bit Manipulation custom opcode table" );
683+ DecoderTableXCVbitmanip32, " CORE-V Bit Manipulation" );
692684 TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXCVelw, DecoderTableXCVelw32,
693- " CORE-V Event load custom opcode table " );
685+ " CORE-V Event load" );
694686 TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXCVmac, DecoderTableXCVmac32,
695- " CORE-V MAC custom opcode table " );
687+ " CORE-V MAC" );
696688 TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXCVmem, DecoderTableXCVmem32,
697- " CORE-V MEM custom opcode table " );
689+ " CORE-V MEM" );
698690 TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXCValu, DecoderTableXCValu32,
699- " CORE-V ALU custom opcode table " );
691+ " CORE-V ALU" );
700692 TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXCVsimd, DecoderTableXCVsimd32,
701- " CORE-V SIMD extensions custom opcode table " );
693+ " CORE-V SIMD extensions" );
702694 TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXCVbi, DecoderTableXCVbi32,
703- " CORE-V Immediate Branching custom opcode table " );
695+ " CORE-V Immediate Branching" );
704696 TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXqcicsr, DecoderTableXqcicsr32,
705- " Qualcomm uC CSR custom opcode table " );
697+ " Qualcomm uC CSR" );
706698 TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXqcisls, DecoderTableXqcisls32,
707- " Qualcomm uC Scaled Load Store custom opcode table " );
699+ " Qualcomm uC Scaled Load Store" );
708700 TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXqcia, DecoderTableXqcia32,
709- " Qualcomm uC Arithmetic custom opcode table " );
701+ " Qualcomm uC Arithmetic" );
710702 TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXqcics, DecoderTableXqcics32,
711- " Qualcomm uC Conditional Select custom opcode table " );
703+ " Qualcomm uC Conditional Select" );
712704 TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXqcilsm, DecoderTableXqcilsm32,
713- " Qualcomm uC Load Store Multiple custom opcode table" );
714- TRY_TO_DECODE_FEATURE (
715- RISCV::FeatureVendorXqciac, DecoderTableXqciac32,
716- " Qualcomm uC Load-Store Address Calculation custom opcode table" );
717- TRY_TO_DECODE_FEATURE (
718- RISCV::FeatureVendorXqcicli, DecoderTableXqcicli32,
719- " Qualcomm uC Conditional Load Immediate custom opcode table" );
705+ " Qualcomm uC Load Store Multiple" );
706+ TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXqciac, DecoderTableXqciac32,
707+ " Qualcomm uC Load-Store Address Calculation" );
708+ TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXqcicli, DecoderTableXqcicli32,
709+ " Qualcomm uC Conditional Load Immediate" );
720710 TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXqcicm, DecoderTableXqcicm32,
721- " Qualcomm uC Conditional Move custom opcode table " );
711+ " Qualcomm uC Conditional Move" );
722712 TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXqciint, DecoderTableXqciint32,
723- " Qualcomm uC Interrupts custom opcode table " );
724- TRY_TO_DECODE (true , DecoderTable32, " RISCV32 table " );
713+ " Qualcomm uC Interrupts" );
714+ TRY_TO_DECODE (true , DecoderTable32, " RISCV32" );
725715
726716 return MCDisassembler::Fail;
727717}
@@ -739,27 +729,23 @@ DecodeStatus RISCVDisassembler::getInstruction16(MCInst &MI, uint64_t &Size,
739729 uint32_t Insn = support::endian::read16le (Bytes.data ());
740730 TRY_TO_DECODE_AND_ADD_SP (!STI.hasFeature (RISCV::Feature64Bit),
741731 DecoderTableRISCV32Only_16,
742- " RISCV32Only_16 table (16-bit Instruction)" );
732+ " RISCV32Only_16 (16-bit Instruction)" );
743733 TRY_TO_DECODE_FEATURE (RISCV::FeatureStdExtZicfiss, DecoderTableZicfiss16,
744- " RVZicfiss table (Shadow Stack)" );
734+ " RVZicfiss (Shadow Stack)" );
745735 TRY_TO_DECODE_FEATURE (RISCV::FeatureStdExtZcmt, DecoderTableRVZcmt16,
746- " Zcmt table (16-bit Table Jump Instructions)" );
747- TRY_TO_DECODE_FEATURE (
748- RISCV::FeatureStdExtZcmp, DecoderTableRVZcmp16,
749- " Zcmp table (16-bit Push/Pop & Double Move Instructions)" );
750- TRY_TO_DECODE_FEATURE (
751- RISCV::FeatureVendorXqciac, DecoderTableXqciac16,
752- " Qualcomm uC Load-Store Address Calculation custom 16bit opcode table" );
753- TRY_TO_DECODE_FEATURE (
754- RISCV::FeatureVendorXqcicm, DecoderTableXqcicm16,
755- " Qualcomm uC Conditional Move custom 16bit opcode table" );
736+ " Zcmt (16-bit Table Jump Instructions)" );
737+ TRY_TO_DECODE_FEATURE (RISCV::FeatureStdExtZcmp, DecoderTableRVZcmp16,
738+ " Zcmp (16-bit Push/Pop & Double Move Instructions)" );
739+ TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXqciac, DecoderTableXqciac16,
740+ " Qualcomm uC Load-Store Address Calculation 16bit" );
741+ TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXqcicm, DecoderTableXqcicm16,
742+ " Qualcomm uC Conditional Move 16bit" );
756743 TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXqciint, DecoderTableXqciint16,
757- " Qualcomm uC Interrupts custom 16bit opcode table " );
744+ " Qualcomm uC Interrupts 16bit" );
758745 TRY_TO_DECODE_AND_ADD_SP (STI.hasFeature (RISCV::FeatureVendorXwchc),
759- DecoderTableXwchc16,
760- " WCH QingKe XW custom opcode table" );
746+ DecoderTableXwchc16, " WCH QingKe XW" );
761747 TRY_TO_DECODE_AND_ADD_SP (true , DecoderTable16,
762- " RISCV_C table (16-bit Instruction)" );
748+ " RISCV_C (16-bit Instruction)" );
763749
764750 return MCDisassembler::Fail;
765751}
@@ -778,9 +764,8 @@ DecodeStatus RISCVDisassembler::getInstruction48(MCInst &MI, uint64_t &Size,
778764 for (size_t i = Size; i-- != 0 ;) {
779765 Insn += (static_cast <uint64_t >(Bytes[i]) << 8 * i);
780766 }
781- TRY_TO_DECODE_FEATURE (
782- RISCV::FeatureVendorXqcilo, DecoderTableXqcilo48,
783- " Qualcomm uC Large Offset Load Store custom 48bit opcode table" );
767+ TRY_TO_DECODE_FEATURE (RISCV::FeatureVendorXqcilo, DecoderTableXqcilo48,
768+ " Qualcomm uC Large Offset Load Store 48bit" );
784769
785770 return MCDisassembler::Fail;
786771}
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