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Salinas, David
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[AMDGPU] Remove scope check in SIInsertWaitcnts::generateWaitcntInstB… (llvm#4380)
2 parents 796d821 + 3fded30 commit 5065ac8

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+1
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llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp

Lines changed: 1 addition & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1918,13 +1918,7 @@ bool SIInsertWaitcnts::generateWaitcntInstBefore(MachineInstr &MI,
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// LOAD_CNT is only relevant to vgpr or LDS.
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unsigned RegNo = FIRST_LDS_VGPR;
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// Only objects with alias scope info were added to LDSDMAScopes array.
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// In the absense of the scope info we will not be able to disambiguate
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// aliasing here. There is no need to try searching for a corresponding
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// store slot. This is conservatively correct because in that case we
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// will produce a wait using the first (general) LDS DMA wait slot which
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// will wait on all of them anyway.
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if (Ptr && Memop->getAAInfo() && Memop->getAAInfo().Scope) {
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if (Ptr && Memop->getAAInfo()) {
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const auto &LDSDMAStores = ScoreBrackets.getLDSDMAStores();
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for (unsigned I = 0, E = LDSDMAStores.size(); I != E; ++I) {
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if (MI.mayAlias(AA, *LDSDMAStores[I], true))

llvm/test/CodeGen/AMDGPU/waitcnt-unscoped.ll

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,6 @@ define amdgpu_kernel void @test_waitcnt(ptr addrspace(1) %global_buffer, ptr add
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; CHECK-NEXT: ds_write_b32 v2, v1
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; CHECK-NEXT: ds_write_b32 v3, v1
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; CHECK-NEXT: ; sched_barrier mask(0x00000000)
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: ds_read_b32 v2, v2
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: global_store_dword v0, v2, s[0:1] offset:16

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