lit test fixes, update revert_patches.txt

ronlieb · ronlieb · commit 58a19f31dbc6 · 2025-03-18T17:11:15.000-05:00
diff --git a/flang/test/Lower/OpenMP/distribute.f90 b/flang/test/Lower/OpenMP/distribute.f90
@@ -7,7 +7,7 @@ subroutine distribute_simple()
   ! CHECK: omp.teams
   !$omp teams
 
-  ! CHECK: omp.distribute private({{.*}}) {
+  ! CHECK: omp.distribute {
   !$omp distribute
 
   ! CHECK-NEXT: omp.loop_nest
diff --git a/flang/test/Lower/OpenMP/order-clause.f90 b/flang/test/Lower/OpenMP/order-clause.f90
@@ -61,15 +61,15 @@ end subroutine do_simd_order_parallel
 
 
 subroutine distribute_order
-   !CHECK: omp.distribute order(reproducible:concurrent) private({{.*}}) {
+   !CHECK: omp.distribute order(reproducible:concurrent) {
    !$omp teams distribute order(concurrent)
    do i=1,10
    end do
-   !CHECK: omp.distribute order(reproducible:concurrent) private({{.*}}) {
+   !CHECK: omp.distribute order(reproducible:concurrent) {
    !$omp teams distribute order(reproducible:concurrent)
    do i=1,10
    end do
-   !CHECK: omp.distribute order(unconstrained:concurrent) private({{.*}}) {
+   !CHECK: omp.distribute order(unconstrained:concurrent) {
    !$omp teams distribute order(unconstrained:concurrent)
    do i = 1, 10
    end do
diff --git a/flang/test/Transforms/stack-arrays-hlfir.f90 b/flang/test/Transforms/stack-arrays-hlfir.f90
@@ -73,7 +73,7 @@ end subroutine omp_target_wsloop
 ! CHECK-NOT:       fir.freemem
 ! CHECK:         omp.teams {
 ! CHECK:           fir.alloca !fir.array<2xi64>
-! CHECK:         omp.distribute private({{.*}}) {
+! CHECK:         omp.distribute {
 ! CHECK:         omp.loop_nest {{.*}} {
 ! CHECK-NOT:       fir.allocmem
 ! CHECK-NOT:       fir.freemem
diff --git a/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-debug-info-multi-entry.ll b/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-debug-info-multi-entry.ll
@@ -45,151 +45,151 @@ define amdgpu_kernel void @preload_block_count_x(ptr addrspace(1) inreg noundef
 ; GFX942-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX942-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX942-NEXT:    v_fmamk_f32 v0, v1, 0xcf800000, v0
-; GFX942-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX942-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GFX942-NEXT:    v_readfirstlane_b32 s5, v1
-; GFX942-NEXT:    v_readfirstlane_b32 s8, v0
-; GFX942-NEXT:    s_mul_i32 s9, s1, s5
-; GFX942-NEXT:    s_mul_hi_u32 s15, s1, s8
-; GFX942-NEXT:    s_mul_i32 s14, s3, s8
-; GFX942-NEXT:    s_add_i32 s9, s15, s9
-; GFX942-NEXT:    s_add_i32 s9, s9, s14
-; GFX942-NEXT:    s_mul_i32 s16, s1, s8
-; GFX942-NEXT:    s_mul_hi_u32 s14, s8, s9
-; GFX942-NEXT:    s_mul_i32 s15, s8, s9
-; GFX942-NEXT:    s_mul_hi_u32 s8, s8, s16
-; GFX942-NEXT:    s_add_u32 s8, s8, s15
-; GFX942-NEXT:    s_addc_u32 s14, 0, s14
-; GFX942-NEXT:    s_mul_hi_u32 s17, s5, s16
-; GFX942-NEXT:    s_mul_i32 s16, s5, s16
-; GFX942-NEXT:    s_add_u32 s8, s8, s16
-; GFX942-NEXT:    s_mul_hi_u32 s15, s5, s9
-; GFX942-NEXT:    s_addc_u32 s8, s14, s17
-; GFX942-NEXT:    s_addc_u32 s14, s15, 0
-; GFX942-NEXT:    s_mul_i32 s9, s5, s9
-; GFX942-NEXT:    s_add_u32 s8, s8, s9
-; GFX942-NEXT:    s_addc_u32 s9, 0, s14
-; GFX942-NEXT:    v_add_co_u32_e32 v0, vcc, s8, v0
-; GFX942-NEXT:    s_cmp_lg_u64 vcc, 0
-; GFX942-NEXT:    s_addc_u32 s5, s5, s9
-; GFX942-NEXT:    v_readfirstlane_b32 s9, v0
-; GFX942-NEXT:    s_mul_i32 s8, s1, s5
-; GFX942-NEXT:    s_mul_hi_u32 s14, s1, s9
-; GFX942-NEXT:    s_add_i32 s8, s14, s8
-; GFX942-NEXT:    s_mul_i32 s3, s3, s9
-; GFX942-NEXT:    s_add_i32 s8, s8, s3
-; GFX942-NEXT:    s_mul_i32 s1, s1, s9
-; GFX942-NEXT:    s_mul_hi_u32 s14, s5, s1
-; GFX942-NEXT:    s_mul_i32 s15, s5, s1
-; GFX942-NEXT:    s_mul_i32 s17, s9, s8
-; GFX942-NEXT:    s_mul_hi_u32 s1, s9, s1
-; GFX942-NEXT:    s_mul_hi_u32 s16, s9, s8
-; GFX942-NEXT:    s_add_u32 s1, s1, s17
-; GFX942-NEXT:    s_addc_u32 s9, 0, s16
-; GFX942-NEXT:    s_add_u32 s1, s1, s15
-; GFX942-NEXT:    s_mul_hi_u32 s3, s5, s8
-; GFX942-NEXT:    s_addc_u32 s1, s9, s14
-; GFX942-NEXT:    s_addc_u32 s3, s3, 0
-; GFX942-NEXT:    s_mul_i32 s8, s5, s8
-; GFX942-NEXT:    s_add_u32 s1, s1, s8
-; GFX942-NEXT:    s_addc_u32 s3, 0, s3
-; GFX942-NEXT:    v_add_co_u32_e32 v0, vcc, s1, v0
-; GFX942-NEXT:    s_cmp_lg_u64 vcc, 0
-; GFX942-NEXT:    s_addc_u32 s1, s5, s3
-; GFX942-NEXT:    v_readfirstlane_b32 s8, v0
-; GFX942-NEXT:    s_mul_i32 s5, s6, s1
-; GFX942-NEXT:    s_mul_hi_u32 s9, s6, s8
-; GFX942-NEXT:    s_mul_hi_u32 s3, s6, s1
-; GFX942-NEXT:    s_add_u32 s5, s9, s5
-; GFX942-NEXT:    s_addc_u32 s3, 0, s3
-; GFX942-NEXT:    s_mul_hi_u32 s14, s7, s8
-; GFX942-NEXT:    s_mul_i32 s8, s7, s8
-; GFX942-NEXT:    s_add_u32 s5, s5, s8
-; GFX942-NEXT:    s_mul_hi_u32 s9, s7, s1
-; GFX942-NEXT:    s_addc_u32 s3, s3, s14
-; GFX942-NEXT:    s_addc_u32 s5, s9, 0
-; GFX942-NEXT:    s_mul_i32 s1, s7, s1
-; GFX942-NEXT:    s_add_u32 s1, s3, s1
-; GFX942-NEXT:    s_addc_u32 s3, 0, s5
-; GFX942-NEXT:    s_mul_i32 s5, s12, s3
-; GFX942-NEXT:    s_mul_hi_u32 s8, s12, s1
-; GFX942-NEXT:    s_add_i32 s5, s8, s5
-; GFX942-NEXT:    s_mul_i32 s8, s13, s1
-; GFX942-NEXT:    s_mul_i32 s9, s12, s1
-; GFX942-NEXT:    s_add_i32 s5, s5, s8
-; GFX942-NEXT:    v_mov_b32_e32 v0, s9
-; GFX942-NEXT:    s_sub_i32 s8, s7, s5
-; GFX942-NEXT:    v_sub_co_u32_e32 v0, vcc, s6, v0
-; GFX942-NEXT:    s_cmp_lg_u64 vcc, 0
-; GFX942-NEXT:    s_subb_u32 s14, s8, s13
-; GFX942-NEXT:    v_subrev_co_u32_e64 v1, s[8:9], s12, v0
-; GFX942-NEXT:    s_cmp_lg_u64 s[8:9], 0
-; GFX942-NEXT:    s_subb_u32 s8, s14, 0
-; GFX942-NEXT:    s_cmp_ge_u32 s8, s13
-; GFX942-NEXT:    v_readfirstlane_b32 s14, v1
-; GFX942-NEXT:    s_cselect_b32 s9, -1, 0
-; GFX942-NEXT:    s_cmp_ge_u32 s14, s12
-; GFX942-NEXT:    s_cselect_b32 s14, -1, 0
-; GFX942-NEXT:    s_cmp_eq_u32 s8, s13
-; GFX942-NEXT:    s_cselect_b32 s8, s14, s9
-; GFX942-NEXT:    s_add_u32 s9, s1, 1
-; GFX942-NEXT:    s_addc_u32 s14, s3, 0
-; GFX942-NEXT:    s_add_u32 s15, s1, 2
-; GFX942-NEXT:    s_addc_u32 s16, s3, 0
-; GFX942-NEXT:    s_cmp_lg_u32 s8, 0
-; GFX942-NEXT:    s_cselect_b32 s8, s15, s9
-; GFX942-NEXT:    s_cselect_b32 s9, s16, s14
-; GFX942-NEXT:    s_cmp_lg_u64 vcc, 0
-; GFX942-NEXT:    s_subb_u32 s5, s7, s5
-; GFX942-NEXT:    s_cmp_ge_u32 s5, s13
-; GFX942-NEXT:    v_readfirstlane_b32 s15, v0
-; GFX942-NEXT:    s_cselect_b32 s14, -1, 0
-; GFX942-NEXT:    s_cmp_ge_u32 s15, s12
-; GFX942-NEXT:    s_cselect_b32 s15, -1, 0
-; GFX942-NEXT:    s_cmp_eq_u32 s5, s13
-; GFX942-NEXT:    s_cselect_b32 s5, s15, s14
-; GFX942-NEXT:    s_cmp_lg_u32 s5, 0
-; GFX942-NEXT:    s_cselect_b32 s9, s9, s3
-; GFX942-NEXT:    s_cselect_b32 s8, s8, s1
+; GFX942-NEXT:    v_cvt_u32_f32_e32 v4, v1
+; GFX942-NEXT:    v_cvt_u32_f32_e32 v5, v0
+; GFX942-NEXT:    v_mul_lo_u32 v0, s1, v4
+; GFX942-NEXT:    v_mul_hi_u32 v2, s1, v5
+; GFX942-NEXT:    v_mul_lo_u32 v1, s3, v5
+; GFX942-NEXT:    v_add_u32_e32 v0, v2, v0
+; GFX942-NEXT:    v_mul_lo_u32 v6, s1, v5
+; GFX942-NEXT:    v_add_u32_e32 v7, v0, v1
+; GFX942-NEXT:    v_mul_hi_u32 v3, v5, v7
+; GFX942-NEXT:    v_mul_lo_u32 v2, v5, v7
+; GFX942-NEXT:    v_mul_hi_u32 v0, v5, v6
+; GFX942-NEXT:    v_mov_b32_e32 v1, 0
+; GFX942-NEXT:    v_lshl_add_u64 v[2:3], v[0:1], 0, v[2:3]
+; GFX942-NEXT:    v_mul_hi_u32 v0, v4, v6
+; GFX942-NEXT:    v_mul_lo_u32 v6, v4, v6
+; GFX942-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v6
+; GFX942-NEXT:    v_mul_hi_u32 v8, v4, v7
+; GFX942-NEXT:    s_nop 0
+; GFX942-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
+; GFX942-NEXT:    v_mul_lo_u32 v2, v4, v7
+; GFX942-NEXT:    s_nop 0
+; GFX942-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v8, vcc
+; GFX942-NEXT:    v_lshl_add_u64 v[2:3], v[0:1], 0, v[2:3]
+; GFX942-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v2
+; GFX942-NEXT:    v_mul_hi_u32 v2, s1, v5
+; GFX942-NEXT:    s_nop 0
+; GFX942-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v3, vcc
+; GFX942-NEXT:    v_mul_lo_u32 v0, s1, v4
+; GFX942-NEXT:    v_add_u32_e32 v0, v2, v0
+; GFX942-NEXT:    v_mul_lo_u32 v2, s3, v5
+; GFX942-NEXT:    v_add_u32_e32 v6, v0, v2
+; GFX942-NEXT:    v_mul_lo_u32 v0, s1, v5
+; GFX942-NEXT:    v_mul_hi_u32 v8, v4, v0
+; GFX942-NEXT:    v_mul_lo_u32 v9, v4, v0
+; GFX942-NEXT:    v_mul_hi_u32 v3, v5, v6
+; GFX942-NEXT:    v_mul_lo_u32 v2, v5, v6
+; GFX942-NEXT:    v_mul_hi_u32 v0, v5, v0
+; GFX942-NEXT:    v_lshl_add_u64 v[2:3], v[0:1], 0, v[2:3]
+; GFX942-NEXT:    v_add_co_u32_e32 v0, vcc, v2, v9
+; GFX942-NEXT:    v_mul_hi_u32 v7, v4, v6
+; GFX942-NEXT:    s_nop 0
+; GFX942-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v8, vcc
+; GFX942-NEXT:    v_mul_lo_u32 v2, v4, v6
+; GFX942-NEXT:    s_nop 0
+; GFX942-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v7, vcc
+; GFX942-NEXT:    v_lshl_add_u64 v[2:3], v[0:1], 0, v[2:3]
+; GFX942-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v2
+; GFX942-NEXT:    v_mul_hi_u32 v0, s6, v5
+; GFX942-NEXT:    s_nop 0
+; GFX942-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v3, vcc
+; GFX942-NEXT:    v_mul_hi_u32 v3, s6, v4
+; GFX942-NEXT:    v_mul_lo_u32 v2, s6, v4
+; GFX942-NEXT:    v_lshl_add_u64 v[2:3], v[0:1], 0, v[2:3]
+; GFX942-NEXT:    v_mul_hi_u32 v0, s7, v5
+; GFX942-NEXT:    v_mul_lo_u32 v5, s7, v5
+; GFX942-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v5
+; GFX942-NEXT:    v_mul_hi_u32 v6, s7, v4
+; GFX942-NEXT:    s_nop 0
+; GFX942-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
+; GFX942-NEXT:    v_mul_lo_u32 v2, s7, v4
+; GFX942-NEXT:    s_nop 0
+; GFX942-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v6, vcc
+; GFX942-NEXT:    v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3]
+; GFX942-NEXT:    v_mul_lo_u32 v2, s12, v1
+; GFX942-NEXT:    v_mul_hi_u32 v3, s12, v0
+; GFX942-NEXT:    v_add_u32_e32 v2, v3, v2
+; GFX942-NEXT:    v_mul_lo_u32 v3, s13, v0
+; GFX942-NEXT:    v_add_u32_e32 v6, v2, v3
+; GFX942-NEXT:    v_mul_lo_u32 v3, s12, v0
+; GFX942-NEXT:    v_sub_u32_e32 v2, s7, v6
+; GFX942-NEXT:    v_mov_b32_e32 v4, s13
+; GFX942-NEXT:    v_sub_co_u32_e32 v7, vcc, s6, v3
+; GFX942-NEXT:    s_nop 1
+; GFX942-NEXT:    v_subb_co_u32_e64 v2, s[8:9], v2, v4, vcc
+; GFX942-NEXT:    v_subrev_co_u32_e64 v3, s[8:9], s12, v7
+; GFX942-NEXT:    s_nop 1
+; GFX942-NEXT:    v_subbrev_co_u32_e64 v2, s[8:9], 0, v2, s[8:9]
+; GFX942-NEXT:    v_cmp_le_u32_e64 s[8:9], s13, v2
+; GFX942-NEXT:    s_nop 1
+; GFX942-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[8:9]
+; GFX942-NEXT:    v_cmp_le_u32_e64 s[8:9], s12, v3
+; GFX942-NEXT:    s_nop 1
+; GFX942-NEXT:    v_cndmask_b32_e64 v3, 0, -1, s[8:9]
+; GFX942-NEXT:    v_cmp_eq_u32_e64 s[8:9], s13, v2
+; GFX942-NEXT:    s_nop 1
+; GFX942-NEXT:    v_cndmask_b32_e64 v8, v4, v3, s[8:9]
+; GFX942-NEXT:    v_lshl_add_u64 v[2:3], v[0:1], 0, 1
+; GFX942-NEXT:    v_lshl_add_u64 v[4:5], v[0:1], 0, 2
+; GFX942-NEXT:    v_cmp_ne_u32_e64 s[8:9], 0, v8
+; GFX942-NEXT:    s_nop 1
+; GFX942-NEXT:    v_cndmask_b32_e64 v2, v2, v4, s[8:9]
+; GFX942-NEXT:    v_mov_b32_e32 v4, s7
+; GFX942-NEXT:    v_subb_co_u32_e32 v4, vcc, v4, v6, vcc
+; GFX942-NEXT:    v_cmp_le_u32_e32 vcc, s13, v4
+; GFX942-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s[8:9]
+; GFX942-NEXT:    s_nop 0
+; GFX942-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
+; GFX942-NEXT:    v_cmp_le_u32_e32 vcc, s12, v7
+; GFX942-NEXT:    s_nop 1
+; GFX942-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
+; GFX942-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v4
+; GFX942-NEXT:    s_nop 1
+; GFX942-NEXT:    v_cndmask_b32_e32 v4, v5, v6, vcc
+; GFX942-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
+; GFX942-NEXT:    s_nop 1
+; GFX942-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX942-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
 ; GFX942-NEXT:    s_cbranch_execnz .LBB0_3
 ; GFX942-NEXT:  .LBB0_2:
 ; GFX942-NEXT:    v_cvt_f32_u32_e32 v0, s12
 ; GFX942-NEXT:    s_sub_i32 s1, 0, s12
-; GFX942-NEXT:    s_mov_b32 s9, 0
 ; GFX942-NEXT:    v_rcp_iflag_f32_e32 v0, v0
 ; GFX942-NEXT:    s_nop 0
 ; GFX942-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
 ; GFX942-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GFX942-NEXT:    s_nop 0
-; GFX942-NEXT:    v_readfirstlane_b32 s3, v0
-; GFX942-NEXT:    s_mul_i32 s1, s1, s3
-; GFX942-NEXT:    s_mul_hi_u32 s1, s3, s1
-; GFX942-NEXT:    s_add_i32 s3, s3, s1
-; GFX942-NEXT:    s_mul_hi_u32 s1, s6, s3
-; GFX942-NEXT:    s_mul_i32 s5, s1, s12
-; GFX942-NEXT:    s_sub_i32 s5, s6, s5
-; GFX942-NEXT:    s_add_i32 s3, s1, 1
-; GFX942-NEXT:    s_sub_i32 s8, s5, s12
-; GFX942-NEXT:    s_cmp_ge_u32 s5, s12
-; GFX942-NEXT:    s_cselect_b32 s1, s3, s1
-; GFX942-NEXT:    s_cselect_b32 s5, s8, s5
-; GFX942-NEXT:    s_add_i32 s3, s1, 1
-; GFX942-NEXT:    s_cmp_ge_u32 s5, s12
-; GFX942-NEXT:    s_cselect_b32 s8, s3, s1
+; GFX942-NEXT:    v_mul_lo_u32 v1, s1, v0
+; GFX942-NEXT:    v_mul_hi_u32 v1, v0, v1
+; GFX942-NEXT:    v_add_u32_e32 v0, v0, v1
+; GFX942-NEXT:    v_mul_hi_u32 v0, s6, v0
+; GFX942-NEXT:    v_mul_lo_u32 v2, v0, s12
+; GFX942-NEXT:    v_sub_u32_e32 v2, s6, v2
+; GFX942-NEXT:    v_add_u32_e32 v1, 1, v0
+; GFX942-NEXT:    v_subrev_u32_e32 v3, s12, v2
+; GFX942-NEXT:    v_cmp_le_u32_e32 vcc, s12, v2
+; GFX942-NEXT:    s_nop 1
+; GFX942-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
+; GFX942-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
+; GFX942-NEXT:    v_add_u32_e32 v1, 1, v0
+; GFX942-NEXT:    v_cmp_le_u32_e32 vcc, s12, v2
+; GFX942-NEXT:    s_nop 1
+; GFX942-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
+; GFX942-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX942-NEXT:  .LBB0_3:
+; GFX942-NEXT:    v_lshl_add_u64 v[0:1], v[0:1], 0, 15
 ; GFX942-NEXT:    s_ashr_i32 s1, s0, 31
-; GFX942-NEXT:    s_add_u32 s3, s8, 15
-; GFX942-NEXT:    s_addc_u32 s5, s9, 0
-; GFX942-NEXT:    s_and_b32 s3, s3, -16
-; GFX942-NEXT:    s_mul_i32 s1, s3, s1
-; GFX942-NEXT:    s_mul_hi_u32 s8, s3, s0
-; GFX942-NEXT:    s_add_i32 s1, s8, s1
-; GFX942-NEXT:    s_mul_i32 s5, s5, s0
-; GFX942-NEXT:    s_add_i32 s1, s1, s5
-; GFX942-NEXT:    s_mul_i32 s3, s3, s0
-; GFX942-NEXT:    v_cvt_f64_i32_e32 v[0:1], s1
+; GFX942-NEXT:    v_and_b32_e32 v0, -16, v0
+; GFX942-NEXT:    v_mul_lo_u32 v2, v0, s1
+; GFX942-NEXT:    v_mul_hi_u32 v3, v0, s0
+; GFX942-NEXT:    v_add_u32_e32 v2, v3, v2
+; GFX942-NEXT:    v_mul_lo_u32 v1, v1, s0
+; GFX942-NEXT:    v_add_u32_e32 v1, v2, v1
+; GFX942-NEXT:    v_mul_lo_u32 v2, v0, s0
+; GFX942-NEXT:    v_cvt_f64_i32_e32 v[0:1], v1
 ; GFX942-NEXT:    v_ldexp_f64 v[0:1], v[0:1], 32
-; GFX942-NEXT:    v_cvt_f64_u32_e32 v[2:3], s3
+; GFX942-NEXT:    v_cvt_f64_u32_e32 v[2:3], v2
 ; GFX942-NEXT:    v_add_f64 v[0:1], v[0:1], v[2:3]
 ; GFX942-NEXT:    v_cvt_f64_u32_e32 v[2:3], s7
 ; GFX942-NEXT:    v_ldexp_f64 v[2:3], v[2:3], 32
@@ -215,7 +215,7 @@ define amdgpu_kernel void @preload_block_count_x(ptr addrspace(1) inreg noundef
 ; GFX942-NEXT:  .LBB0_4:
 ; GFX942-NEXT:  .Ltmp4:
 ; GFX942-NEXT:    ;DEBUG_VALUE: test:var <- [DW_OP_LLVM_poisoned] $sgpr2_sgpr3
-; GFX942-NEXT:    ; implicit-def: $sgpr8_sgpr9
+; GFX942-NEXT:    ; implicit-def: $vgpr0_vgpr1
 ; GFX942-NEXT:    s_branch .LBB0_2
 ; GFX942-NEXT:  .Ltmp5:
 entry:
diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-budget-exhausted.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-budget-exhausted.ll
@@ -8,9 +8,9 @@ define amdgpu_kernel void @simple_users_scores() {
 ; CHECK-LABEL: define amdgpu_kernel void @simple_users_scores(
 ; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
 ; CHECK-NEXT:  [[ENTRY:.*:]]
+; CHECK-NEXT:    [[SIMPLEUSER:%.*]] = alloca [4 x i64], align 4, addrspace(5)
 ; CHECK-NEXT:    [[MANYUSERS:%.*]] = alloca [64 x i64], align 4, addrspace(5)
-; CHECK-NEXT:    [[SIMPLEUSER:%.*]] = freeze <4 x i64> poison
-; CHECK-NEXT:    [[TMP0:%.*]] = insertelement <4 x i64> [[SIMPLEUSER]], i64 42, i32 0
+; CHECK-NEXT:    store i64 42, ptr addrspace(5) [[SIMPLEUSER]], align 8
 ; CHECK-NEXT:    [[MANYUSERS_1:%.*]] = getelementptr i8, ptr addrspace(5) [[MANYUSERS]], i64 2
 ; CHECK-NEXT:    [[V0:%.*]] = load i8, ptr addrspace(5) [[MANYUSERS_1]], align 1
 ; CHECK-NEXT:    [[V0_EXT:%.*]] = zext i8 [[V0]] to i64
diff --git a/llvm/test/CodeGen/AMDGPU/spill-sgpr-to-virtual-vgpr.mir b/llvm/test/CodeGen/AMDGPU/spill-sgpr-to-virtual-vgpr.mir
@@ -56,21 +56,37 @@ body:             |
     ; GCN: liveins: $sgpr10, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $vgpr63, $sgpr30_sgpr31, $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71, $sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79, $sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87, $sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95
     ; GCN-NEXT: {{  $}}
     ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr64, 0, $vgpr63
+    ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr64, $vgpr63, 0, 32
     ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr65, 1, $vgpr63
+    ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr65, $vgpr63, 1, 32
     ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr66, 2, $vgpr63
+    ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr66, $vgpr63, 2, 32
     ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr67, 3, $vgpr63
+    ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr67, $vgpr63, 3, 32
     ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr68, 4, $vgpr63
+    ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr68, $vgpr63, 4, 32
     ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr69, 5, $vgpr63
+    ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr69, $vgpr63, 5, 32
     ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr70, 6, $vgpr63
+    ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr70, $vgpr63, 6, 32
     ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr71, 7, $vgpr63
+    ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr71, $vgpr63, 7, 32
     ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr80, 8, $vgpr63
+    ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr80, $vgpr63, 8, 32
     ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr81, 9, $vgpr63
+    ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr81, $vgpr63, 9, 32
     ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr82, 10, $vgpr63
+    ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr82, $vgpr63, 10, 32
     ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr83, 11, $vgpr63
+    ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr83, $vgpr63, 11, 32
     ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr84, 12, $vgpr63
+    ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr84, $vgpr63, 12, 32
     ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr85, 13, $vgpr63
+    ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr85, $vgpr63, 13, 32
     ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr86, 14, $vgpr63
+    ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr86, $vgpr63, 14, 32
     ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr87, 15, $vgpr63
+    ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr87, $vgpr63, 15, 32
     ; GCN-NEXT: S_NOP 0
     ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
     ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR killed $sgpr10, 0, [[DEF]]
diff --git a/revert_patches.txt b/revert_patches.txt
@@ -20,11 +20,9 @@ revert: breaks build of rccl __cpuidex
 1c28b92373 [Clang] __has_builtin should return false for aux triple builtins (#121839) 
 Ron and Saiyed
 ---
-breaks flang build quadmath_wrapper.h
-[Flang-RT] Environment introspection for quadmath.h (#130411)  
-Kruse, palermo
---
-breaks build of offload
-libc] Make RPC server handling header only (#131205)  
-huber
+bdb63208b  [AMDGPU][CodeGen] Using MBB's liveIn check in tandem with MCRegAliasIterator in SILowerSGPRSpills (#129848)
+Vikash Gupta
+---
+needs local patch: Akash B
+cbc5c11f [MLIR][OpenMP] Add Lowering support for implicitly linking to default declare mappers (#131006)
 ---
