[AMDGPU][SIInsertHardClauses] Maintain instruction referencing debug info (llvm#1826)

Fixes SWDEV-508737

Author: epilk

llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp

@@ -167,18 +167,61 @@ class SIInsertHardClauses {
     SmallVector<const MachineOperand *, 4> BaseOps;
   };
 
+  void substituteDebugInstrNumbersToBundleHeader(MachineInstr &FirstInBundle) {
+    auto *MBB = FirstInBundle.getParent();
+    auto *MF = MBB->getParent();
+
+    // Make a map from registers defined within the bundle to their defining
+    // debug instruction number and operand.
+    DenseMap<Register, std::pair<unsigned, unsigned>> RegDefs;
+    for (const MachineOperand &Op : const_mi_bundle_ops(FirstInBundle)) {
+      const MachineInstr &MI = *Op.getParent();
+      if (!MI.isBundle() && Op.isReg() && Op.isDef())
+        RegDefs[Op.getReg()] = {MI.peekDebugInstrNum(), Op.getOperandNo()};
+    }
+
+    MachineInstr &BundleHeader = *std::prev(FirstInBundle.getIterator());
+    for (const MachineOperand &HeaderOp : BundleHeader.operands()) {
+      if (!HeaderOp.isReg() || !HeaderOp.isDef() || HeaderOp.isDead())
+        continue;
+      auto It = RegDefs.find(HeaderOp.getReg());
+      if (It == RegDefs.end())
+        continue;
+      auto [DINum, OpNum] = It->second;
+      if (DINum == 0)
+        continue;
+      MF->makeDebugValueSubstitution(
+          {DINum, OpNum},
+          {BundleHeader.getDebugInstrNum(), HeaderOp.getOperandNo()});
+    }
+  }
+
   bool emitClause(const ClauseInfo &CI, const SIInstrInfo *SII) {
     if (CI.First == CI.Last)
       return false;
     assert(CI.Length <= ST->maxHardClauseLength() &&
            "Hard clause is too long!");
 
     auto &MBB = *CI.First->getParent();
+    bool NeedDebugSubs = false;
+    // Move debug instructions before the bundle and check if debug
+    // substitutions need to be added to the bundle header.
+    for (auto It = CI.First->getIterator(),
+              E = std::next(CI.Last->getIterator());
+         It != E;) {
+      auto MI = It++;
+      if (MI->isDebugInstr())
+        MBB.splice(CI.First, &MBB, MI);
+      else if (MI->peekDebugInstrNum() != 0)
+        NeedDebugSubs = true;
+    }
     auto ClauseMI =
         BuildMI(MBB, *CI.First, DebugLoc(), SII->get(AMDGPU::S_CLAUSE))
             .addImm(CI.Length - 1);
     finalizeBundle(MBB, ClauseMI->getIterator(),
                    std::next(CI.Last->getIterator()));
+    if (NeedDebugSubs)
+      substituteDebugInstrNumbersToBundleHeader(*ClauseMI);
     return true;
   }
 

llvm/test/DebugInfo/AMDGPU/hard-clauses.mir

@@ -0,0 +1,57 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs -run-pass si-insert-hard-clauses %s -o - | FileCheck %s
+
+# CHECK-LABEL: name: debug_instrs
+# CHECK-LABEL: debugValueSubstitutions:
+# CHECK-NEXT: - { srcinst: 3, srcop: 0, dstinst: 4, dstop: 0, subreg: 0 }
+# CHECK-NEXT: - { srcinst: 2, srcop: 0, dstinst: 4, dstop: 3, subreg: 0 }
+
+---
+name: debug_instrs
+tracksRegLiveness: true
+debugInstrRef: true
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1
+    ; CHECK: liveins: $sgpr0_sgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: DBG_VALUE_LIST
+    ; CHECK-NEXT: DBG_PHI
+    ; CHECK-NEXT: DBG_INSTR_REF
+    ; CHECK-NEXT: BUNDLE implicit-def $sgpr3, implicit-def $sgpr3_lo16, implicit-def $sgpr3_hi16, implicit-def $sgpr2, implicit-def $sgpr2_lo16, implicit-def $sgpr2_hi16, implicit $sgpr0_sgpr1, debug-instr-number 4 {
+    ; CHECK-NEXT:   S_CLAUSE 2
+    ; CHECK-NEXT:   $sgpr3 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, debug-instr-number 1
+    ; CHECK-NEXT:   $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 4, 0, debug-instr-number 2
+    ; CHECK-NEXT:   $sgpr3 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 8, 0, debug-instr-number 3
+    ; CHECK-NEXT: }
+    ; CHECK-NEXT: DBG_VALUE
+    DBG_VALUE_LIST
+    $sgpr3 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, debug-instr-number 1
+    DBG_PHI
+    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 4, 0, debug-instr-number 2
+    DBG_INSTR_REF
+    $sgpr3 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 8, 0, debug-instr-number 3
+    DBG_VALUE
+...
+
+# CHECK-LABEL: name: only_last_instr
+# CHECK-LABEL: debugValueSubstitutions:
+# CHECK-NEXT: - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 3, subreg: 0 }
+
+---
+name: only_last_instr
+tracksRegLiveness: true
+debugInstrRef: true
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1
+    ; CHECK: liveins: $sgpr0_sgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: BUNDLE implicit-def $sgpr2, implicit-def $sgpr2_lo16, implicit-def $sgpr2_hi16, implicit-def $sgpr3, implicit-def $sgpr3_lo16, implicit-def $sgpr3_hi16, implicit $sgpr0_sgpr1, debug-instr-number 2 {
+    ; CHECK-NEXT:   S_CLAUSE 1
+    ; CHECK-NEXT:   $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 4, 0
+    ; CHECK-NEXT:   $sgpr3 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 8, 0, debug-instr-number 1
+    ; CHECK-NEXT: }
+    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 4, 0
+    $sgpr3 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 8, 0, debug-instr-number 1
+...