Skip to content

Commit 5b1c9d3

Browse files
ronliebronlieb
authored
Revert "[AMDGPU][MC] Allow op_sel in v_alignbit_b32 etc in GFX9 and G… (llvm#3104)
2 parents 11f6a4a + 50d81a6 commit 5b1c9d3

File tree

11 files changed

+12
-230
lines changed

11 files changed

+12
-230
lines changed

‎llvm/lib/Target/AMDGPU/SIInstructions.td‎

Lines changed: 5 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -2488,7 +2488,6 @@ def : AMDGPUPat <
24882488
>;
24892489

24902490
let True16Predicate = NotHasTrue16BitInsts in {
2491-
let SubtargetPredicate = isNotGFX9Plus in {
24922491
def : ROTRPattern <V_ALIGNBIT_B32_e64>;
24932492

24942493
def : GCNPat<(i32 (trunc (srl i64:$src0, (and i32:$src1, (i32 31))))),
@@ -2498,35 +2497,6 @@ def : GCNPat<(i32 (trunc (srl i64:$src0, (and i32:$src1, (i32 31))))),
24982497
def : GCNPat<(i32 (trunc (srl i64:$src0, (i32 ShiftAmt32Imm:$src1)))),
24992498
(V_ALIGNBIT_B32_e64 (i32 (EXTRACT_SUBREG (i64 $src0), sub1)),
25002499
(i32 (EXTRACT_SUBREG (i64 $src0), sub0)), $src1)>;
2501-
} // isNotGFX9Plus
2502-
2503-
let SubtargetPredicate = isGFX9GFX10 in {
2504-
def : GCNPat <
2505-
(rotr i32:$src0, i32:$src1),
2506-
(V_ALIGNBIT_B32_opsel_e64 /* src0_modifiers */ 0, $src0,
2507-
/* src1_modifiers */ 0, $src0,
2508-
/* src2_modifiers */ 0,
2509-
$src1, /* clamp */ 0, /* op_sel */ 0)
2510-
>;
2511-
2512-
foreach pat = [(i32 (trunc (srl i64:$src0, (and i32:$src1, (i32 31))))),
2513-
(i32 (trunc (srl i64:$src0, (i32 ShiftAmt32Imm:$src1))))] in
2514-
def : GCNPat<pat,
2515-
(V_ALIGNBIT_B32_opsel_e64 0, /* src0_modifiers */
2516-
(i32 (EXTRACT_SUBREG (i64 $src0), sub1)),
2517-
0, /* src1_modifiers */
2518-
(i32 (EXTRACT_SUBREG (i64 $src0), sub0)),
2519-
0, /* src2_modifiers */
2520-
$src1, /* clamp */ 0, /* op_sel */ 0)
2521-
>;
2522-
2523-
def : GCNPat<(fshr i32:$src0, i32:$src1, i32:$src2),
2524-
(V_ALIGNBIT_B32_opsel_e64 /* src0_modifiers */ 0, $src0,
2525-
/* src1_modifiers */ 0, $src1,
2526-
/* src2_modifiers */ 0,
2527-
$src2, /* clamp */ 0, /* op_sel */ 0)
2528-
>;
2529-
} // isGFX9GFX10
25302500
} // end True16Predicate = NotHasTrue16BitInsts
25312501

25322502
let True16Predicate = UseRealTrue16Insts in {
@@ -3127,8 +3097,6 @@ def : GCNPat <
31273097
(i32 (EXTRACT_SUBREG $a, sub0))), (i32 1))
31283098
>;
31293099

3130-
// This pattern for bswap is used for pre-GFX8. For GFX8+, bswap is mapped
3131-
// to V_PERM_B32.
31323100
let True16Predicate = NotHasTrue16BitInsts in
31333101
def : GCNPat <
31343102
(i32 (bswap i32:$a)),
@@ -3604,20 +3572,15 @@ def : GCNPat <
36043572

36053573
// Take the upper 16 bits from V[0] and the lower 16 bits from V[1]
36063574
// Special case, can use V_ALIGNBIT (always uses encoded literal)
3607-
let True16Predicate = NotHasTrue16BitInsts in {
3608-
defvar BuildVectorToAlignBitPat =
3575+
let True16Predicate = NotHasTrue16BitInsts in
3576+
def : GCNPat <
36093577
(vecTy (DivergentBinFrag<build_vector>
36103578
(Ty !if(!eq(Ty, i16),
36113579
(Ty (trunc (srl VGPR_32:$a, (i32 16)))),
36123580
(Ty (bitconvert (i16 (trunc (srl VGPR_32:$a, (i32 16)))))))),
3613-
(Ty VGPR_32:$b)));
3614-
3615-
let SubtargetPredicate = isNotGFX9Plus in
3616-
def : GCNPat<BuildVectorToAlignBitPat, (V_ALIGNBIT_B32_e64 VGPR_32:$b, VGPR_32:$a, (i32 16))>;
3617-
3618-
let SubtargetPredicate = isGFX9GFX10 in
3619-
def : GCNPat<BuildVectorToAlignBitPat, (V_ALIGNBIT_B32_opsel_e64 0, VGPR_32:$b, 0, VGPR_32:$a, 0, (i32 16), 0, 0)>;
3620-
} //True16Predicate = NotHasTrue16BitInsts
3581+
(Ty VGPR_32:$b))),
3582+
(V_ALIGNBIT_B32_e64 VGPR_32:$b, VGPR_32:$a, (i32 16))
3583+
>;
36213584

36223585
let True16Predicate = UseFakeTrue16Insts in
36233586
def : GCNPat <

‎llvm/lib/Target/AMDGPU/VOP3Instructions.td‎

Lines changed: 2 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -224,12 +224,6 @@ defm V_ALIGNBIT_B32 : VOP3Inst_t16_with_profiles <"v_alignbit_b32",
224224
fshr, null_frag>;
225225

226226
defm V_ALIGNBYTE_B32 : VOP3Inst <"v_alignbyte_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_alignbyte>;
227-
228-
// In gfx9 and 10, opsel is allowed for V_ALIGNBIT_B32 and V_ALIGNBYTE_B32.
229-
// Hardware uses opsel[1:0] to byte-select src2. Other opsel bits are ignored.
230-
defm V_ALIGNBIT_B32_opsel : VOP3Inst <"v_alignbit_b32_opsel", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_OPSEL>>;
231-
defm V_ALIGNBYTE_B32_opsel : VOP3Inst <"v_alignbyte_b32_opsel", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_OPSEL>>;
232-
233227
let True16Predicate = UseRealTrue16Insts in
234228
defm V_ALIGNBYTE_B32_t16 : VOP3Inst <"v_alignbyte_b32_t16", VOP3_Profile_True16<VOP_I32_I32_I32_I16, VOP3_OPSEL>>;
235229
let True16Predicate = UseFakeTrue16Insts in
@@ -1960,9 +1954,6 @@ let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in {
19601954
}
19611955
} // End AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10"
19621956

1963-
defm V_ALIGNBIT_B32_opsel : VOP3OpSel_Real_gfx10_with_name<0x14e, "V_ALIGNBIT_B32_opsel", "v_alignbit_b32">;
1964-
defm V_ALIGNBYTE_B32_opsel : VOP3OpSel_Real_gfx10_with_name<0x14f, "V_ALIGNBYTE_B32_opsel", "v_alignbyte_b32">;
1965-
19661957
defm V_READLANE_B32 : VOP3_Real_No_Suffix_gfx10<0x360>;
19671958

19681959
let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) in {
@@ -2113,8 +2104,8 @@ defm V_BFI_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14a>;
21132104
defm V_FMA_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x14b>;
21142105
defm V_FMA_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x14c>;
21152106
defm V_LERP_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x14d>;
2116-
defm V_ALIGNBIT_B32 : VOP3_Real_gfx6_gfx7<0x14e>;
2117-
defm V_ALIGNBYTE_B32 : VOP3_Real_gfx6_gfx7<0x14f>;
2107+
defm V_ALIGNBIT_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14e>;
2108+
defm V_ALIGNBYTE_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14f>;
21182109
defm V_MULLIT_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x150>;
21192110
defm V_MIN3_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x151>;
21202111
defm V_MIN3_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x152>;
@@ -2257,17 +2248,6 @@ multiclass VOP3_Real_BITOP3_gfx9<bits<10> op, string AsmName, bit isSingle = 0>
22572248
}
22582249
}
22592250

2260-
// Instructions such as v_alignbyte_b32 allows op_sel in gfx9, but not in vi.
2261-
// The following is created to support that.
2262-
multiclass VOP3OpSel_Real_gfx9_with_name<bits<10> op, string opName, string AsmName> {
2263-
defvar psName = opName#"_e64";
2264-
def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(psName), SIEncodingFamily.VI>, // note: encoding family is VI
2265-
VOP3OpSel_gfx9 <op, !cast<VOP3_Pseudo>(psName).Pfl> {
2266-
VOP3_Pseudo ps = !cast<VOP3_Pseudo>(psName);
2267-
let AsmString = AsmName # ps.AsmOperands;
2268-
}
2269-
}
2270-
22712251
} // End AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9"
22722252

22732253
defm V_MAD_U64_U32 : VOP3be_Real_vi <0x1E8>;
@@ -2287,10 +2267,8 @@ defm V_BFI_B32 : VOP3_Real_vi <0x1ca>;
22872267
defm V_FMA_F32 : VOP3_Real_vi <0x1cb>;
22882268
defm V_FMA_F64 : VOP3_Real_vi <0x1cc>;
22892269
defm V_LERP_U8 : VOP3_Real_vi <0x1cd>;
2290-
let SubtargetPredicate = isGFX8Only in {
22912270
defm V_ALIGNBIT_B32 : VOP3_Real_vi <0x1ce>;
22922271
defm V_ALIGNBYTE_B32 : VOP3_Real_vi <0x1cf>;
2293-
}
22942272
defm V_MIN3_F32 : VOP3_Real_vi <0x1d0>;
22952273
defm V_MIN3_I32 : VOP3_Real_vi <0x1d1>;
22962274
defm V_MIN3_U32 : VOP3_Real_vi <0x1d2>;
@@ -2335,9 +2313,6 @@ defm V_INTERP_P2_LEGACY_F16 : VOP3Interp_F16_Real_gfx9 <0x276, "V_INTERP_P2_F16"
23352313
defm V_MAD_LEGACY_U16 : VOP3_F16_Real_gfx9 <0x1eb, "V_MAD_U16", "v_mad_legacy_u16">;
23362314
defm V_MAD_LEGACY_I16 : VOP3_F16_Real_gfx9 <0x1ec, "V_MAD_I16", "v_mad_legacy_i16">;
23372315

2338-
defm V_ALIGNBIT_B32_opsel : VOP3OpSel_Real_gfx9_with_name <0x1ce, "V_ALIGNBIT_B32_opsel", "v_alignbit_b32">;
2339-
defm V_ALIGNBYTE_B32_opsel : VOP3OpSel_Real_gfx9_with_name <0x1cf, "V_ALIGNBYTE_B32_opsel", "v_alignbyte_b32">;
2340-
23412316
defm V_MAD_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x203, "v_mad_f16">;
23422317
defm V_MAD_U16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x204, "v_mad_u16">;
23432318
defm V_MAD_I16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x205, "v_mad_i16">;

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bswap.mir‎

Lines changed: 0 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -mtriple=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX7 %s
33
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
4-
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
5-
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s
64

75
---
86
name: bswap_i32_vv
@@ -21,30 +19,13 @@ body: |
2119
; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16711935
2220
; GFX7-NEXT: [[V_BFI_B32_e64_:%[0-9]+]]:vgpr_32 = V_BFI_B32_e64 [[S_MOV_B32_]], [[V_ALIGNBIT_B32_e64_1]], [[V_ALIGNBIT_B32_e64_]], implicit $exec
2321
; GFX7-NEXT: S_ENDPGM 0, implicit [[V_BFI_B32_e64_]]
24-
;
2522
; GFX8-LABEL: name: bswap_i32_vv
2623
; GFX8: liveins: $vgpr0
2724
; GFX8-NEXT: {{ $}}
2825
; GFX8-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
2926
; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 66051
3027
; GFX8-NEXT: [[V_PERM_B32_e64_:%[0-9]+]]:vgpr_32 = V_PERM_B32_e64 0, [[COPY]], [[S_MOV_B32_]], implicit $exec
3128
; GFX8-NEXT: S_ENDPGM 0, implicit [[V_PERM_B32_e64_]]
32-
;
33-
; GFX9-LABEL: name: bswap_i32_vv
34-
; GFX9: liveins: $vgpr0
35-
; GFX9-NEXT: {{ $}}
36-
; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
37-
; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 66051
38-
; GFX9-NEXT: [[V_PERM_B32_e64_:%[0-9]+]]:vgpr_32 = V_PERM_B32_e64 0, [[COPY]], [[S_MOV_B32_]], implicit $exec
39-
; GFX9-NEXT: S_ENDPGM 0, implicit [[V_PERM_B32_e64_]]
40-
;
41-
; GFX10-LABEL: name: bswap_i32_vv
42-
; GFX10: liveins: $vgpr0
43-
; GFX10-NEXT: {{ $}}
44-
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
45-
; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 66051
46-
; GFX10-NEXT: [[V_PERM_B32_e64_:%[0-9]+]]:vgpr_32 = V_PERM_B32_e64 0, [[COPY]], [[S_MOV_B32_]], implicit $exec
47-
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_PERM_B32_e64_]]
4829
%0:vgpr(s32) = COPY $vgpr0
4930
%1:vgpr(s32) = G_BSWAP %0
5031
S_ENDPGM 0, implicit %1

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fshr.mir‎

Lines changed: 2 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
33
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
4-
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
5-
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s
4+
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
5+
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
66
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefixes=GFX11 %s
77

88
---
@@ -24,24 +24,6 @@ body: |
2424
; GCN-NEXT: [[V_ALIGNBIT_B32_e64_:%[0-9]+]]:vgpr_32 = V_ALIGNBIT_B32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
2525
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ALIGNBIT_B32_e64_]]
2626
;
27-
; GFX9-LABEL: name: fshr_s32
28-
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
29-
; GFX9-NEXT: {{ $}}
30-
; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
31-
; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
32-
; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
33-
; GFX9-NEXT: [[V_ALIGNBIT_B32_opsel_e64_:%[0-9]+]]:vgpr_32 = V_ALIGNBIT_B32_opsel_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
34-
; GFX9-NEXT: S_ENDPGM 0, implicit [[V_ALIGNBIT_B32_opsel_e64_]]
35-
;
36-
; GFX10-LABEL: name: fshr_s32
37-
; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2
38-
; GFX10-NEXT: {{ $}}
39-
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
40-
; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
41-
; GFX10-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
42-
; GFX10-NEXT: [[V_ALIGNBIT_B32_opsel_e64_:%[0-9]+]]:vgpr_32 = V_ALIGNBIT_B32_opsel_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
43-
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_ALIGNBIT_B32_opsel_e64_]]
44-
;
4527
; GFX11-LABEL: name: fshr_s32
4628
; GFX11: liveins: $vgpr0, $vgpr1, $vgpr2
4729
; GFX11-NEXT: {{ $}}

‎llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -768,10 +768,10 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
768768
; GFX90A-NEXT: renamable $vgpr10 = COPY renamable $sgpr22, implicit $exec
769769
; GFX90A-NEXT: renamable $vgpr12_vgpr13 = DS_READ_B64_gfx9 killed renamable $vgpr10, 0, 0, implicit $exec :: (load (s64) from %ir.8, addrspace 3)
770770
; GFX90A-NEXT: renamable $vgpr10 = COPY renamable $sgpr46, implicit $exec
771-
; GFX90A-NEXT: renamable $vgpr11 = V_ALIGNBIT_B32_opsel_e64 0, killed $sgpr47, 0, killed $vgpr10, 0, 1, 0, 0, implicit $exec
772-
; GFX90A-NEXT: renamable $vgpr52 = V_ALIGNBIT_B32_opsel_e64 0, $vgpr17, 0, $vgpr16, 0, 1, 0, 0, implicit $exec
771+
; GFX90A-NEXT: renamable $vgpr11 = V_ALIGNBIT_B32_e64 killed $sgpr47, killed $vgpr10, 1, implicit $exec
772+
; GFX90A-NEXT: renamable $vgpr52 = V_ALIGNBIT_B32_e64 $vgpr17, $vgpr16, 1, implicit $exec
773773
; GFX90A-NEXT: renamable $vgpr17 = V_CNDMASK_B32_e64 0, 0, 0, 1, $sgpr12_sgpr13, implicit $exec
774-
; GFX90A-NEXT: renamable $vgpr15 = V_ALIGNBIT_B32_opsel_e64 0, $vgpr15, 0, $vgpr14, 0, 1, 0, 0, implicit $exec
774+
; GFX90A-NEXT: renamable $vgpr15 = V_ALIGNBIT_B32_e64 $vgpr15, $vgpr14, 1, implicit $exec
775775
; GFX90A-NEXT: renamable $sgpr52_sgpr53 = S_XOR_B64 $exec, -1, implicit-def dead $scc
776776
; GFX90A-NEXT: renamable $sgpr62_sgpr63 = S_OR_B64 renamable $sgpr36_sgpr37, $exec, implicit-def dead $scc
777777
; GFX90A-NEXT: renamable $vgpr10 = COPY renamable $vgpr14, implicit $exec

‎llvm/test/MC/AMDGPU/gfx10_asm_vop3.s‎

Lines changed: 0 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -3628,18 +3628,6 @@ v_alignbit_b32 v5, v1, v2, exec_lo
36283628
v_alignbit_b32 v5, v1, v2, exec_hi
36293629
// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0x05,0xfe,0x01]
36303630

3631-
v_alignbit_b32 v5, v1, v2, v3 op_sel:[1]
3632-
// GFX10: v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x4e,0xd5,0x01,0x05,0x0e,0x04]
3633-
3634-
v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,1]
3635-
// GFX10: v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,1,0,0] ; encoding: [0x05,0x18,0x4e,0xd5,0x01,0x05,0x0e,0x04]
3636-
3637-
v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,1,1]
3638-
// GFX10: v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,1,1,0] ; encoding: [0x05,0x38,0x4e,0xd5,0x01,0x05,0x0e,0x04]
3639-
3640-
v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,1,1,1]
3641-
// GFX10: v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0x4e,0xd5,0x01,0x05,0x0e,0x04]
3642-
36433631
v_alignbyte_b32 v5, v1, v2, v3
36443632
// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0x05,0x0e,0x04]
36453633

@@ -3727,18 +3715,6 @@ v_alignbyte_b32 v5, v1, v2, exec_lo
37273715
v_alignbyte_b32 v5, v1, v2, exec_hi
37283716
// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0x05,0xfe,0x01]
37293717

3730-
v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1]
3731-
// GFX10: v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x4f,0xd5,0x01,0x05,0x0e,0x04]
3732-
3733-
v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,1]
3734-
// GFX10: v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,1,0,0] ; encoding: [0x05,0x18,0x4f,0xd5,0x01,0x05,0x0e,0x04]
3735-
3736-
v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,1,1]
3737-
// GFX10: v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,1,1,0] ; encoding: [0x05,0x38,0x4f,0xd5,0x01,0x05,0x0e,0x04]
3738-
3739-
v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,1,1,1]
3740-
// GFX10: v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0x4f,0xd5,0x01,0x05,0x0e,0x04]
3741-
37423718
v_mullit_f32 v5, v1, v2, v3
37433719
// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0x0e,0x04]
37443720

‎llvm/test/MC/AMDGPU/gfx7_err_pos.s‎

Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -44,16 +44,3 @@ s_load_dword s5, s[2:3], glc
4444
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: cache policy is not supported for SMRD instructions
4545
// CHECK-NEXT:{{^}}s_load_dword s5, s[2:3], glc
4646
// CHECK-NEXT:{{^}} ^
47-
48-
//==============================================================================
49-
// not a valid operand
50-
51-
v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,1,1,1]
52-
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
53-
// CHECK-NEXT:{{^}}v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,1,1,1]
54-
// CHECK-NEXT:{{^}} ^
55-
56-
v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,1,1,1]
57-
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
58-
// CHECK-NEXT:{{^}}v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,1,1,1]
59-
// CHECK-NEXT:{{^}} ^

‎llvm/test/MC/AMDGPU/gfx8_err_pos.s‎

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -49,13 +49,3 @@ v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PRESERV
4949
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
5050
// CHECK-NEXT:{{^}}v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:BYTE_0 src1_sel:WORD_0
5151
// CHECK-NEXT:{{^}} ^
52-
53-
v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,1,1,1]
54-
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
55-
// CHECK-NEXT:{{^}}v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,1,1,1]
56-
// CHECK-NEXT:{{^}} ^
57-
58-
v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,1,1,1]
59-
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
60-
// CHECK-NEXT:{{^}}v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,1,1,1]
61-
// CHECK-NEXT:{{^}} ^

‎llvm/test/MC/AMDGPU/gfx9_asm_vop3_e64.s‎

Lines changed: 0 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -2829,18 +2829,6 @@ v_alignbit_b32 v5, v1, v2, src_execz
28292829
v_alignbit_b32 v5, v1, v2, src_scc
28302830
// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xf6,0x03]
28312831

2832-
v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0xce,0xd1,0x01,0x05,0x0e,0x04]
2833-
// CHECK: [0x05,0x08,0xce,0xd1,0x01,0x05,0x0e,0x04]
2834-
2835-
v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,1,0,0] ; encoding: [0x05,0x18,0xce,0xd1,0x01,0x05,0x0e,0x04]
2836-
// CHECK: [0x05,0x18,0xce,0xd1,0x01,0x05,0x0e,0x04]
2837-
2838-
v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,1,1,0] ; encoding: [0x05,0x38,0xce,0xd1,0x01,0x05,0x0e,0x04]
2839-
// CHECK: [0x05,0x38,0xce,0xd1,0x01,0x05,0x0e,0x04]
2840-
2841-
v_alignbit_b32 v5, v1, v2, v3 op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0xce,0xd1,0x01,0x05,0x0e,0x04]
2842-
// CHECK: [0x05,0x78,0xce,0xd1,0x01,0x05,0x0e,0x04]
2843-
28442832
v_alignbyte_b32 v5, v1, v2, v3
28452833
// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0x0e,0x04]
28462834

@@ -3012,18 +3000,6 @@ v_alignbyte_b32 v5, v1, v2, src_execz
30123000
v_alignbyte_b32 v5, v1, v2, src_scc
30133001
// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xf6,0x03]
30143002

3015-
v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1]
3016-
// CHECK: v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0xcf,0xd1,0x01,0x05,0x0e,0x04]
3017-
3018-
v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,1]
3019-
// CHECK: v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,1,0,0] ; encoding: [0x05,0x18,0xcf,0xd1,0x01,0x05,0x0e,0x04]
3020-
3021-
v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,1,1]
3022-
// CHECK: v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,1,1,0] ; encoding: [0x05,0x38,0xcf,0xd1,0x01,0x05,0x0e,0x04]
3023-
3024-
v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,1,1,1]
3025-
// CHECK: v_alignbyte_b32 v5, v1, v2, v3 op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0xcf,0xd1,0x01,0x05,0x0e,0x04]
3026-
30273003
v_min3_f32 v5, v1, v2, v3
30283004
// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x04]
30293005

0 commit comments

Comments
 (0)