[amdgpu][nfc] Post-commit feedback on c39fba2

Author: JonChesterfield

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

@@ -2420,7 +2420,7 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
     assert(ST.useVGPRIndexMode());
     Register VecReg = MI.getOperand(0).getReg();
     bool IsUndef = MI.getOperand(1).isUndef();
-    MachineOperand Idx = MI.getOperand(3);
+    MachineOperand &Idx = MI.getOperand(3);
     Register SubReg = MI.getOperand(4).getImm();
 
     MachineInstr *SetOn = BuildMI(MBB, MI, DL, get(AMDGPU::S_SET_GPR_IDX_ON))

llvm/test/CodeGen/AMDGPU/copy-to-reg-frameindex.ll

@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx90a | FileCheck %s
 
 define amdgpu_kernel void @copy_to_reg_frameindex(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) {
 ; CHECK-LABEL: copy_to_reg_frameindex:
@@ -20,19 +20,18 @@ define amdgpu_kernel void @copy_to_reg_frameindex(ptr addrspace(1) %out, i32 %a,
 ; CHECK-NEXT:    s_endpgm
 entry:
   %B = srem i32 %c, -1
-  %alloca = alloca [16 x i32], align 4, addrspace(5)
   br label %loop
 
 loop:
+  %promotealloca = phi <16 x i32> [ undef, %entry ], [ %0, %loop ]
   %inc = phi i32 [ 0, %entry ], [ %inc.i, %loop ]
-  %ptr = getelementptr [16 x i32], ptr addrspace(5) %alloca, i32 0, i32 %inc
-  store i32 %inc, ptr addrspace(5) %ptr, align 4
+  %0 = insertelement <16 x i32> %promotealloca, i32 %inc, i32 %inc
   %inc.i = add i32 %inc, %B
   %cnd = icmp uge i32 %inc.i, 16
   br i1 %cnd, label %done, label %loop
 
 done:
-  %tmp1 = load i32, ptr addrspace(5) %alloca, align 4
-  store i32 %tmp1, ptr addrspace(1) %out, align 4
+  %1 = extractelement <16 x i32> %0, i32 0
+  store i32 %1, ptr addrspace(1) %out, align 4
   ret void
 }