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[IR] Consolidate OneNthElements IIT descriptors. NFCI (llvm#141492)
This replaces LLVMHalfElementsVectorType and LLVMOne{3,4,5,6,7,8}ElementsVectorType with one parameterized IIT descriptor. The type signature is encoded as the argument index of the vector type to match followed by the divisor N, and inside IITDescriptor this is stored as two 16 bit parts, similarly to LLVMVectorOfAnyPointersToElt. This also allows us to use a foreach to declare the [de]interleave intrinsics.
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-237
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4 files changed

+50
-237
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‎llvm/include/llvm/IR/Intrinsics.h‎

Lines changed: 14 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -151,13 +151,7 @@ namespace Intrinsic {
151151
Argument,
152152
ExtendArgument,
153153
TruncArgument,
154-
HalfVecArgument,
155-
OneThirdVecArgument,
156-
OneFourthVecArgument,
157-
OneFifthVecArgument,
158-
OneSixthVecArgument,
159-
OneSeventhVecArgument,
160-
OneEighthVecArgument,
154+
OneNthEltsVecArgument,
161155
SameVecWidthArgument,
162156
VecOfAnyPtrsToElt,
163157
VecElementArgument,
@@ -169,12 +163,6 @@ namespace Intrinsic {
169163
AArch64Svcount,
170164
} Kind;
171165

172-
// These six have to be contiguous.
173-
static_assert(OneFourthVecArgument == OneThirdVecArgument + 1 &&
174-
OneFifthVecArgument == OneFourthVecArgument + 1 &&
175-
OneSixthVecArgument == OneFifthVecArgument + 1 &&
176-
OneSeventhVecArgument == OneSixthVecArgument + 1 &&
177-
OneEighthVecArgument == OneSeventhVecArgument + 1);
178166
union {
179167
unsigned Integer_Width;
180168
unsigned Float_Width;
@@ -193,20 +181,16 @@ namespace Intrinsic {
193181

194182
unsigned getArgumentNumber() const {
195183
assert(Kind == Argument || Kind == ExtendArgument ||
196-
Kind == TruncArgument || Kind == HalfVecArgument ||
197-
(Kind >= OneThirdVecArgument && Kind <= OneEighthVecArgument) ||
198-
Kind == SameVecWidthArgument || Kind == VecElementArgument ||
199-
Kind == Subdivide2Argument || Kind == Subdivide4Argument ||
200-
Kind == VecOfBitcastsToInt);
184+
Kind == TruncArgument || Kind == SameVecWidthArgument ||
185+
Kind == VecElementArgument || Kind == Subdivide2Argument ||
186+
Kind == Subdivide4Argument || Kind == VecOfBitcastsToInt);
201187
return Argument_Info >> 3;
202188
}
203189
ArgKind getArgumentKind() const {
204190
assert(Kind == Argument || Kind == ExtendArgument ||
205-
Kind == TruncArgument || Kind == HalfVecArgument ||
206-
(Kind >= OneThirdVecArgument && Kind <= OneEighthVecArgument) ||
207-
Kind == SameVecWidthArgument || Kind == VecElementArgument ||
208-
Kind == Subdivide2Argument || Kind == Subdivide4Argument ||
209-
Kind == VecOfBitcastsToInt);
191+
Kind == TruncArgument || Kind == SameVecWidthArgument ||
192+
Kind == VecElementArgument || Kind == Subdivide2Argument ||
193+
Kind == Subdivide4Argument || Kind == VecOfBitcastsToInt);
210194
return (ArgKind)(Argument_Info & 7);
211195
}
212196

@@ -216,8 +200,14 @@ namespace Intrinsic {
216200
assert(Kind == VecOfAnyPtrsToElt);
217201
return Argument_Info >> 16;
218202
}
203+
// OneNthEltsVecArguments uses both a divisor N and a reference argument for
204+
// the full-width vector to match
205+
unsigned getVectorDivisor() const {
206+
assert(Kind == OneNthEltsVecArgument);
207+
return Argument_Info >> 16;
208+
}
219209
unsigned getRefArgNumber() const {
220-
assert(Kind == VecOfAnyPtrsToElt);
210+
assert(Kind == VecOfAnyPtrsToElt || Kind == OneNthEltsVecArgument);
221211
return Argument_Info & 0xFFFF;
222212
}
223213

‎llvm/include/llvm/IR/Intrinsics.td‎

Lines changed: 20 additions & 141 deletions
Original file line numberDiff line numberDiff line change
@@ -306,7 +306,7 @@ def IIT_TRUNC_ARG : IIT_Base<26>;
306306
def IIT_ANYPTR : IIT_Base<27>;
307307
def IIT_V1 : IIT_Vec<1, 28>;
308308
def IIT_VARARG : IIT_VT<isVoid, 29>;
309-
def IIT_HALF_VEC_ARG : IIT_Base<30>;
309+
def IIT_ONE_NTH_ELTS_VEC_ARG : IIT_Base<30>;
310310
def IIT_SAME_VEC_WIDTH_ARG : IIT_Base<31>;
311311
def IIT_VEC_OF_ANYPTRS_TO_ELT : IIT_Base<34>;
312312
def IIT_I128 : IIT_Int<128, 35>;
@@ -335,14 +335,8 @@ def IIT_I4 : IIT_Int<4, 58>;
335335
def IIT_AARCH64_SVCOUNT : IIT_VT<aarch64svcount, 59>;
336336
def IIT_V6 : IIT_Vec<6, 60>;
337337
def IIT_V10 : IIT_Vec<10, 61>;
338-
def IIT_ONE_THIRD_VEC_ARG : IIT_Base<62>;
339-
def IIT_ONE_FIFTH_VEC_ARG : IIT_Base<63>;
340-
def IIT_ONE_SEVENTH_VEC_ARG : IIT_Base<64>;
341-
def IIT_V2048: IIT_Vec<2048, 65>;
342-
def IIT_V4096: IIT_Vec<4096, 66>;
343-
def IIT_ONE_FOURTH_VEC_ARG : IIT_Base<67>;
344-
def IIT_ONE_SIXTH_VEC_ARG : IIT_Base<68>;
345-
def IIT_ONE_EIGHTH_VEC_ARG : IIT_Base<69>;
338+
def IIT_V2048: IIT_Vec<2048, 62>;
339+
def IIT_V4096: IIT_Vec<4096, 63>;
346340
}
347341

348342
defvar IIT_all_FixedTypes = !filter(iit, IIT_all,
@@ -479,27 +473,15 @@ class LLVMVectorOfAnyPointersToElt<int num>
479473
class LLVMVectorElementType<int num> : LLVMMatchType<num, IIT_VEC_ELEMENT>;
480474

481475
// Match the type of another intrinsic parameter that is expected to be a
482-
// vector type, but change the element count to be half as many.
483-
class LLVMHalfElementsVectorType<int num>
484-
: LLVMMatchType<num, IIT_HALF_VEC_ARG>;
485-
486-
class LLVMOneThirdElementsVectorType<int num>
487-
: LLVMMatchType<num, IIT_ONE_THIRD_VEC_ARG>;
488-
489-
class LLVMOneFourthElementsVectorType<int num>
490-
: LLVMMatchType<num, IIT_ONE_FOURTH_VEC_ARG>;
491-
492-
class LLVMOneFifthElementsVectorType<int num>
493-
: LLVMMatchType<num, IIT_ONE_FIFTH_VEC_ARG>;
494-
495-
class LLVMOneSixthElementsVectorType<int num>
496-
: LLVMMatchType<num, IIT_ONE_SIXTH_VEC_ARG>;
497-
498-
class LLVMOneSeventhElementsVectorType<int num>
499-
: LLVMMatchType<num, IIT_ONE_SEVENTH_VEC_ARG>;
500-
501-
class LLVMOneEighthElementsVectorType<int num>
502-
: LLVMMatchType<num, IIT_ONE_EIGHTH_VEC_ARG>;
476+
// vector type, but change the element count to be 1/n of it.
477+
class LLVMOneNthElementsVectorType<int idx, int n>
478+
: LLVMMatchType<idx, IIT_ONE_NTH_ELTS_VEC_ARG> {
479+
let Sig = [
480+
IIT_ONE_NTH_ELTS_VEC_ARG.Number,
481+
EncNextArgN<idx>.ret,
482+
n,
483+
];
484+
}
503485

504486
// Match the type of another intrinsic parameter that is expected to be a
505487
// vector type (i.e. <N x iM>) but with each element subdivided to
@@ -2771,118 +2753,15 @@ def int_vector_extract : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
27712753
[llvm_anyvector_ty, llvm_i64_ty],
27722754
[IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<1>>]>;
27732755

2756+
foreach n = 2...8 in {
2757+
def int_vector_interleave#n : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
2758+
!listsplat(LLVMOneNthElementsVectorType<0, n>, n),
2759+
[IntrNoMem]>;
27742760

2775-
def int_vector_interleave2 : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
2776-
[LLVMHalfElementsVectorType<0>,
2777-
LLVMHalfElementsVectorType<0>],
2778-
[IntrNoMem]>;
2779-
2780-
def int_vector_deinterleave2 : DefaultAttrsIntrinsic<[LLVMHalfElementsVectorType<0>,
2781-
LLVMHalfElementsVectorType<0>],
2782-
[llvm_anyvector_ty],
2783-
[IntrNoMem]>;
2784-
2785-
def int_vector_interleave3 : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
2786-
[LLVMOneThirdElementsVectorType<0>,
2787-
LLVMOneThirdElementsVectorType<0>,
2788-
LLVMOneThirdElementsVectorType<0>],
2789-
[IntrNoMem]>;
2790-
2791-
def int_vector_deinterleave3 : DefaultAttrsIntrinsic<[LLVMOneThirdElementsVectorType<0>,
2792-
LLVMOneThirdElementsVectorType<0>,
2793-
LLVMOneThirdElementsVectorType<0>],
2794-
[llvm_anyvector_ty],
2795-
[IntrNoMem]>;
2796-
2797-
def int_vector_interleave4 : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
2798-
[LLVMOneFourthElementsVectorType<0>,
2799-
LLVMOneFourthElementsVectorType<0>,
2800-
LLVMOneFourthElementsVectorType<0>,
2801-
LLVMOneFourthElementsVectorType<0>],
2802-
[IntrNoMem]>;
2803-
2804-
def int_vector_deinterleave4 : DefaultAttrsIntrinsic<[LLVMOneFourthElementsVectorType<0>,
2805-
LLVMOneFourthElementsVectorType<0>,
2806-
LLVMOneFourthElementsVectorType<0>,
2807-
LLVMOneFourthElementsVectorType<0>],
2808-
[llvm_anyvector_ty],
2809-
[IntrNoMem]>;
2810-
2811-
def int_vector_interleave5 : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
2812-
[LLVMOneFifthElementsVectorType<0>,
2813-
LLVMOneFifthElementsVectorType<0>,
2814-
LLVMOneFifthElementsVectorType<0>,
2815-
LLVMOneFifthElementsVectorType<0>,
2816-
LLVMOneFifthElementsVectorType<0>],
2817-
[IntrNoMem]>;
2818-
2819-
def int_vector_deinterleave5 : DefaultAttrsIntrinsic<[LLVMOneFifthElementsVectorType<0>,
2820-
LLVMOneFifthElementsVectorType<0>,
2821-
LLVMOneFifthElementsVectorType<0>,
2822-
LLVMOneFifthElementsVectorType<0>,
2823-
LLVMOneFifthElementsVectorType<0>],
2824-
[llvm_anyvector_ty],
2825-
[IntrNoMem]>;
2826-
2827-
def int_vector_interleave6 : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
2828-
[LLVMOneSixthElementsVectorType<0>,
2829-
LLVMOneSixthElementsVectorType<0>,
2830-
LLVMOneSixthElementsVectorType<0>,
2831-
LLVMOneSixthElementsVectorType<0>,
2832-
LLVMOneSixthElementsVectorType<0>,
2833-
LLVMOneSixthElementsVectorType<0>],
2834-
[IntrNoMem]>;
2835-
2836-
def int_vector_deinterleave6 : DefaultAttrsIntrinsic<[LLVMOneSixthElementsVectorType<0>,
2837-
LLVMOneSixthElementsVectorType<0>,
2838-
LLVMOneSixthElementsVectorType<0>,
2839-
LLVMOneSixthElementsVectorType<0>,
2840-
LLVMOneSixthElementsVectorType<0>,
2841-
LLVMOneSixthElementsVectorType<0>],
2842-
[llvm_anyvector_ty],
2843-
[IntrNoMem]>;
2844-
2845-
def int_vector_interleave7 : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
2846-
[LLVMOneSeventhElementsVectorType<0>,
2847-
LLVMOneSeventhElementsVectorType<0>,
2848-
LLVMOneSeventhElementsVectorType<0>,
2849-
LLVMOneSeventhElementsVectorType<0>,
2850-
LLVMOneSeventhElementsVectorType<0>,
2851-
LLVMOneSeventhElementsVectorType<0>,
2852-
LLVMOneSeventhElementsVectorType<0>],
2853-
[IntrNoMem]>;
2854-
2855-
def int_vector_deinterleave7 : DefaultAttrsIntrinsic<[LLVMOneSeventhElementsVectorType<0>,
2856-
LLVMOneSeventhElementsVectorType<0>,
2857-
LLVMOneSeventhElementsVectorType<0>,
2858-
LLVMOneSeventhElementsVectorType<0>,
2859-
LLVMOneSeventhElementsVectorType<0>,
2860-
LLVMOneSeventhElementsVectorType<0>,
2861-
LLVMOneSeventhElementsVectorType<0>],
2862-
[llvm_anyvector_ty],
2863-
[IntrNoMem]>;
2864-
2865-
def int_vector_interleave8 : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
2866-
[LLVMOneEighthElementsVectorType<0>,
2867-
LLVMOneEighthElementsVectorType<0>,
2868-
LLVMOneEighthElementsVectorType<0>,
2869-
LLVMOneEighthElementsVectorType<0>,
2870-
LLVMOneEighthElementsVectorType<0>,
2871-
LLVMOneEighthElementsVectorType<0>,
2872-
LLVMOneEighthElementsVectorType<0>,
2873-
LLVMOneEighthElementsVectorType<0>],
2874-
[IntrNoMem]>;
2875-
2876-
def int_vector_deinterleave8 : DefaultAttrsIntrinsic<[LLVMOneEighthElementsVectorType<0>,
2877-
LLVMOneEighthElementsVectorType<0>,
2878-
LLVMOneEighthElementsVectorType<0>,
2879-
LLVMOneEighthElementsVectorType<0>,
2880-
LLVMOneEighthElementsVectorType<0>,
2881-
LLVMOneEighthElementsVectorType<0>,
2882-
LLVMOneEighthElementsVectorType<0>,
2883-
LLVMOneEighthElementsVectorType<0>],
2884-
[llvm_anyvector_ty],
2885-
[IntrNoMem]>;
2761+
def int_vector_deinterleave#n : DefaultAttrsIntrinsic<!listsplat(LLVMOneNthElementsVectorType<0, n>, n),
2762+
[llvm_anyvector_ty],
2763+
[IntrNoMem]>;
2764+
}
28862765

28872766
//===-------------- Intrinsics to perform partial reduction ---------------===//
28882767

‎llvm/include/llvm/IR/IntrinsicsAArch64.td‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -186,7 +186,7 @@ let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.".
186186
[IntrNoMem]>;
187187
class AdvSIMD_2VectorArg_Tied_Narrow_Intrinsic
188188
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
189-
[LLVMHalfElementsVectorType<0>, llvm_anyvector_ty],
189+
[LLVMOneNthElementsVectorType<0, 2>, llvm_anyvector_ty],
190190
[IntrNoMem]>;
191191
class AdvSIMD_2VectorArg_Lane_Intrinsic
192192
: DefaultAttrsIntrinsic<[llvm_anyint_ty],
@@ -207,11 +207,11 @@ let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.".
207207
[IntrNoMem]>;
208208
class AdvSIMD_3VectorArg_Tied_Narrow_Intrinsic
209209
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
210-
[LLVMHalfElementsVectorType<0>, llvm_anyvector_ty,
210+
[LLVMOneNthElementsVectorType<0, 2>, llvm_anyvector_ty,
211211
LLVMMatchType<1>], [IntrNoMem]>;
212212
class AdvSIMD_3VectorArg_Scalar_Tied_Narrow_Intrinsic
213213
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
214-
[LLVMHalfElementsVectorType<0>, llvm_anyvector_ty, llvm_i32_ty],
214+
[LLVMOneNthElementsVectorType<0, 2>, llvm_anyvector_ty, llvm_i32_ty],
215215
[IntrNoMem]>;
216216
class AdvSIMD_CvtFxToFP_Intrinsic
217217
: DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty],
@@ -1330,7 +1330,7 @@ let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.".
13301330
[IntrNoMem, ImmArg<ArgIndex<0>>]>;
13311331

13321332
class AdvSIMD_SVE_PUNPKHI_Intrinsic
1333-
: DefaultAttrsIntrinsic<[LLVMHalfElementsVectorType<0>],
1333+
: DefaultAttrsIntrinsic<[LLVMOneNthElementsVectorType<0, 2>],
13341334
[llvm_anyvector_ty],
13351335
[IntrNoMem]>;
13361336

@@ -4229,4 +4229,4 @@ let TargetPrefix = "aarch64" in {
42294229
def int_aarch64_sme_fp8_fvdot_lane_za16_vg1x2 : SME_FP8_ZA_LANE_VGx2_Intrinsic;
42304230
def int_aarch64_sme_fp8_fvdotb_lane_za32_vg1x4 : SME_FP8_ZA_LANE_VGx2_Intrinsic;
42314231
def int_aarch64_sme_fp8_fvdott_lane_za32_vg1x4 : SME_FP8_ZA_LANE_VGx2_Intrinsic;
4232-
}
4232+
}

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