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[RISCV] Add SpacemiT XSMTVDot (SpacemiT Vector Dot Product) extension. (llvm#151706)
The full spec can be found at spacemit-x60 processor support scope: Section 2.1.2.2 (Features): https://developer.spacemit.com/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb#2.1 This patch only supports assembler.
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clang/test/Driver/print-supported-extensions-riscv.c

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@@ -194,6 +194,7 @@
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// CHECK-NEXT: xsfvqmaccqoq 1.0 'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))
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// CHECK-NEXT: xsifivecdiscarddlone 1.0 'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)
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// CHECK-NEXT: xsifivecflushdlone 1.0 'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)
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// CHECK-NEXT: xsmtvdot 1.0 'XSMTVDot' (SpacemiT Vector Dot Product Extension)
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// CHECK-NEXT: xtheadba 1.0 'XTHeadBa' (T-Head address calculation instructions)
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// CHECK-NEXT: xtheadbb 1.0 'XTHeadBb' (T-Head basic bit-manipulation instructions)
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// CHECK-NEXT: xtheadbs 1.0 'XTHeadBs' (T-Head single-bit instructions)

clang/test/Driver/riscv-cpus.c

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@@ -157,6 +157,7 @@
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// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svinval"
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// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svnapot"
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// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svpbmt"
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// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+xsmtvdot"
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// MCPU-SPACEMIT-X60-SAME: "-target-abi" "lp64d"
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// We cannot check much for -mcpu=native, but it should be replaced by a valid CPU string.

llvm/docs/RISCVUsage.rst

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@@ -531,6 +531,10 @@ The current vendor extensions supported are:
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``XAndesVDot``
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LLVM implements `version 5.0.0 of the Andes Vector Dot Product Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification.
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``XSMTVDot``
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SpacemiT defines `Intrinsic Matrix Extension (IME) specification <https://github.com/space-mit/riscv-ime-extension-spec/releases/tag/v0429>`__.
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LLVM implement the hardware-adapted subset for SpacemiT X60, defined in the `feature document <https://developer.spacemit.com/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb#2.1>`__ by SpacemiT. All instructions are prefixed with `smt.` as described in the implementation guide. Note that this implemented subset is `version 1.0.0 of the SpacemiT Vector Dot Product Extension specification`, which is strictly a subset of the full IME specification to reflect the capabilities of SpacemiT X60 hardware correctly.
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Experimental C Intrinsics
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=========================
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llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

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@@ -672,6 +672,8 @@ static constexpr FeatureBitset XAndesGroup = {
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RISCV::FeatureVendorXAndesVSIntLoad, RISCV::FeatureVendorXAndesVPackFPH,
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RISCV::FeatureVendorXAndesVDot};
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static constexpr FeatureBitset XSMTGroup = {RISCV::FeatureVendorXSMTVDot};
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static constexpr DecoderListEntry DecoderList32[]{
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// Vendor Extensions
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{DecoderTableXCV32, XCVFeatureGroup, "CORE-V extensions"},
@@ -692,6 +694,7 @@ static constexpr DecoderListEntry DecoderList32[]{
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{RISCV::FeatureVendorXMIPSCBOP},
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"MIPS mips.pref"},
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{DecoderTableXAndes32, XAndesGroup, "Andes extensions"},
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{DecoderTableXSMT32, XSMTGroup, "SpacemiT extensions"},
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// Standard Extensions
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{DecoderTable32, {}, "standard 32-bit instructions"},
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{DecoderTableRV32Only32, {}, "RV32-only standard 32-bit instructions"},

llvm/lib/Target/RISCV/RISCVFeatures.td

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@@ -1642,6 +1642,14 @@ def HasVendorXAndesVDot
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AssemblerPredicate<(all_of FeatureVendorXAndesVDot),
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"'XAndesVDot' (Andes Vector Dot Product Extension)">;
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def FeatureVendorXSMTVDot
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: RISCVExtension<1, 0, "SpacemiT Vector Dot Product Extension",
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[FeatureStdExtZve32f]>;
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def HasVendorXSMTVDot
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: Predicate<"Subtarget->hasVendorXSMTVDot()">,
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AssemblerPredicate<(all_of FeatureVendorXSMTVDot),
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"'XSMTVDot' (SpacemiT Vector Dot Product Extension)">;
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//===----------------------------------------------------------------------===//
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// LLVM specific features and extensions
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//===----------------------------------------------------------------------===//

llvm/lib/Target/RISCV/RISCVInstrInfo.td

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@@ -2381,6 +2381,7 @@ include "RISCVInstrInfoXqccmp.td"
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include "RISCVInstrInfoXMips.td"
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include "RISCVInstrInfoXRivos.td"
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include "RISCVInstrInfoXAndes.td"
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include "RISCVInstrInfoXSpacemiT.td"
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//===----------------------------------------------------------------------===//
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// Global ISel
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//===-- RISCVInstrInfoXSpacemiT.td -------------------------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the vendor extensions defined by SpacemiT.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Operand definitions.
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//===----------------------------------------------------------------------===//
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class SMTVDotOpcode<bits<7> val> {
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bits<7> Value = val;
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}
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class SMTVEncoding2<bits<2> val> {
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bits<2> Value = val;
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}
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def OPMMA : SMTVDotOpcode<0b1110001>;
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def OPMMA_SLIDE : SMTVDotOpcode<0b1110011>;
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//===----------------------------------------------------------------------===//
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// Vector Dot-Product Sign Encoding
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// Defines the signed/unsigned mixing modes for vector dot-product operations.
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// Encoding format: [1:0] bits
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// 00: UU (Unsigned x Unsigned)
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// 01: US (Unsigned x Signed)
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// 10: SU (Signed x Unsigned)
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// 11: SS (Signed x Signed)
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//===----------------------------------------------------------------------===//
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def SMT_VDot_UU : SMTVEncoding2<0b00>;
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def SMT_VDot_US : SMTVEncoding2<0b01>;
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def SMT_VDot_SU : SMTVEncoding2<0b10>;
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def SMT_VDot_SS : SMTVEncoding2<0b11>;
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//===----------------------------------------------------------------------===//
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// Vector Dot-Product Sliding Window Modes
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// Encoding format: [1:0] bits
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// 00: Slide1 (1-element sliding stride)
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// 01: Slide2 (2-element sliding stride)
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// 10: Slide3 (3-element sliding stride)
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// 11: Reserved
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//
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// Used in sliding-window dot-product operations:
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// vd = vs1 • vs2.slide{1|2|3} // • = dot product
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//===----------------------------------------------------------------------===//
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def SMT_VDot_Slide1 : SMTVEncoding2<0b00>;
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def SMT_VDot_Slide2 : SMTVEncoding2<0b01>;
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def SMT_VDot_Slide3 : SMTVEncoding2<0b10>;
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//===----------------------------------------------------------------------===//
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// Instruction formats
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
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// Base vector dot product (no slide) format.
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class RVInstSMTVDot<SMTVEncoding2 sign, string opcodestr, string argstr>
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: RVInst<(outs VRM2:$vd), (ins VR:$vs1, VR:$vs2), opcodestr, argstr, [], InstFormatR> {
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bits<5> vd;
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bits<5> vs1;
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bits<5> vs2;
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let Inst{31-25} = OPMMA.Value;
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let Inst{24-20} = vs2;
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let Inst{19-15} = vs1;
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let Inst{14} = 0b0;
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let Inst{13-12} = sign.Value;
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let Inst{11-8} = vd{4-1};
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let Inst{7} = 0b0;
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let Inst{6-0} = OPC_CUSTOM_1.Value;
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}
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// Sliding-window vector dot product format.
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class RVInstSMTVDotSlide<SMTVEncoding2 funct2, SMTVEncoding2 sign, string opcodestr, string argstr>
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: RVInst<(outs VRM2:$vd), (ins VRM2:$vs1, VR:$vs2), opcodestr, argstr, [], InstFormatR> {
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bits<5> vd;
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bits<5> vs1;
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bits<5> vs2;
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let Inst{31-25} = OPMMA_SLIDE.Value;
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let Inst{24-20} = vs2;
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let Inst{19-16} = vs1{4-1};
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let Inst{15-14} = funct2.Value;
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let Inst{13-12} = sign.Value;
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let Inst{11-8} = vd{4-1};
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let Inst{7} = 0b0;
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let Inst{6-0} = OPC_CUSTOM_1.Value;
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}
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}
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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let DecoderNamespace = "XSMT" in {
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let Predicates = [HasVendorXSMTVDot], ElementsDependOn = EltDepsVL in {
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// Base vector dot product (no slide) instructions
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// NOTE: Destination registers (vd) MUST be even-numbered (v0, v2, ..., v30)
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// due to hardware alignment constraints. Using odd registers may cause undefined behavior.
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def VMADOT : RVInstSMTVDot<SMT_VDot_SS, "smt.vmadot", "$vd, $vs1, $vs2">;
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def VMADOTU : RVInstSMTVDot<SMT_VDot_UU, "smt.vmadotu", "$vd, $vs1, $vs2">;
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def VMADOTSU : RVInstSMTVDot<SMT_VDot_SU, "smt.vmadotsu", "$vd, $vs1, $vs2">;
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def VMADOTUS : RVInstSMTVDot<SMT_VDot_US, "smt.vmadotus", "$vd, $vs1, $vs2">;
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//===----------------------------------------------------------------------===//
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// Sliding-window Vector Dot Product Instructions
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//
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// The numeric suffix (1, 2, 3) specifies the stride of the sliding window:
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// 1: Window slides by 1 element per operation
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// 2: Window slides by 2 elements per operation
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// 3: Window slides by 3 elements per operation
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//
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// These instructions compute dot products with overlapping operand windows
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// where the window position increments by <N> elements between computations.
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//===----------------------------------------------------------------------===//
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// NOTE: Destination registers (vd) and first source register (vs1) MUST be
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// even-numbered (v0, v2, ..., v30) due to hardware alignment constraints.
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// Using odd registers may cause undefined behavior.
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def VMADOT1 : RVInstSMTVDotSlide<SMT_VDot_Slide1, SMT_VDot_SS, "smt.vmadot1", "$vd, $vs1, $vs2">;
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def VMADOT1U : RVInstSMTVDotSlide<SMT_VDot_Slide1, SMT_VDot_UU, "smt.vmadot1u", "$vd, $vs1, $vs2">;
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def VMADOT1SU : RVInstSMTVDotSlide<SMT_VDot_Slide1, SMT_VDot_SU, "smt.vmadot1su", "$vd, $vs1, $vs2">;
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def VMADOT1US : RVInstSMTVDotSlide<SMT_VDot_Slide1, SMT_VDot_US, "smt.vmadot1us", "$vd, $vs1, $vs2">;
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def VMADOT2 : RVInstSMTVDotSlide<SMT_VDot_Slide2, SMT_VDot_SS, "smt.vmadot2", "$vd, $vs1, $vs2">;
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def VMADOT2U : RVInstSMTVDotSlide<SMT_VDot_Slide2, SMT_VDot_UU, "smt.vmadot2u", "$vd, $vs1, $vs2">;
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def VMADOT2SU : RVInstSMTVDotSlide<SMT_VDot_Slide2, SMT_VDot_SU, "smt.vmadot2su", "$vd, $vs1, $vs2">;
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def VMADOT2US : RVInstSMTVDotSlide<SMT_VDot_Slide2, SMT_VDot_US, "smt.vmadot2us", "$vd, $vs1, $vs2">;
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def VMADOT3 : RVInstSMTVDotSlide<SMT_VDot_Slide3, SMT_VDot_SS, "smt.vmadot3", "$vd, $vs1, $vs2">;
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def VMADOT3U : RVInstSMTVDotSlide<SMT_VDot_Slide3, SMT_VDot_UU, "smt.vmadot3u", "$vd, $vs1, $vs2">;
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def VMADOT3SU : RVInstSMTVDotSlide<SMT_VDot_Slide3, SMT_VDot_SU, "smt.vmadot3su", "$vd, $vs1, $vs2">;
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def VMADOT3US : RVInstSMTVDotSlide<SMT_VDot_Slide3, SMT_VDot_US, "smt.vmadot3us", "$vd, $vs1, $vs2">;
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}
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}

llvm/lib/Target/RISCV/RISCVProcessors.td

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@@ -673,6 +673,7 @@ def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
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FeatureStdExtZvfh,
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FeatureStdExtZvkt,
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FeatureStdExtZvl256b,
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FeatureVendorXSMTVDot,
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FeatureUnalignedScalarMem]),
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[TuneDLenFactor2,
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TuneOptimizedNF2SegmentLoadStore,

llvm/test/CodeGen/RISCV/features-info.ll

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; CHECK-NEXT: xsfvqmaccqoq - 'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4)).
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; CHECK-NEXT: xsifivecdiscarddlone - 'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction).
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; CHECK-NEXT: xsifivecflushdlone - 'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction).
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; CHECK-NEXT: xsmtvdot - 'XSMTVDot' (SpacemiT Vector Dot Product Extension).
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; CHECK-NEXT: xtheadba - 'XTHeadBa' (T-Head address calculation instructions).
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; CHECK-NEXT: xtheadbb - 'XTHeadBb' (T-Head basic bit-manipulation instructions).
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; CHECK-NEXT: xtheadbs - 'XTHeadBs' (T-Head single-bit instructions).
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# RUN: not llvm-mc -triple riscv32 -mattr=+xsmtvdot < %s 2>&1 \
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# RUN: | FileCheck %s
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# RUN: not llvm-mc -triple riscv64 -mattr=+xsmtvdot < %s 2>&1 \
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# RUN: | FileCheck %s
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# NoSlide
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smt.vmadot v1, v2, v2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
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smt.vmadotu v1, v2, v2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
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smt.vmadotsu v1, v2, v2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
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smt.vmadotus v1, v2, v2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
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# Slide = 1
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smt.vmadot1 v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
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smt.vmadot1u v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
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smt.vmadot1su v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
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smt.vmadot1us v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
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smt.vmadot1 v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
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smt.vmadot1u v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
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smt.vmadot1su v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
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smt.vmadot1us v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
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smt.vmadot1 v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
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smt.vmadot1u v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
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smt.vmadot1su v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
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smt.vmadot1us v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
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# Slide = 2
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smt.vmadot2 v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
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smt.vmadot2u v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
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smt.vmadot2su v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
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smt.vmadot2us v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
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smt.vmadot2 v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
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smt.vmadot2u v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
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smt.vmadot2su v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
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smt.vmadot2us v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
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smt.vmadot2 v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
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smt.vmadot2u v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
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smt.vmadot2su v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
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smt.vmadot2us v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
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# Slide = 3
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smt.vmadot3 v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
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smt.vmadot3u v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
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smt.vmadot3su v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
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smt.vmadot3us v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
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smt.vmadot3 v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
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smt.vmadot3u v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
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smt.vmadot3su v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
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smt.vmadot3us v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
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smt.vmadot3 v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
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smt.vmadot3u v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
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smt.vmadot3su v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
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smt.vmadot3us v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction

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