Skip to content

Commit 7f18465

Browse files
ronliebronlieb
committed
merge main into amd-staging
2 parents 0c4c05e + b67796f commit 7f18465

24 files changed

+8772
-198
lines changed

‎.github/workflows/build-ci-container-windows.yml‎

Lines changed: 10 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -56,7 +56,7 @@ jobs:
5656
- build-ci-container-windows
5757
permissions:
5858
packages: write
59-
runs-on: windows-2022
59+
runs-on: ubuntu-24.04
6060
env:
6161
GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
6262
steps:
@@ -66,8 +66,12 @@ jobs:
6666
name: container
6767
- name: Push Container
6868
run: |
69-
docker load -i ${{ needs.build-ci-container-windows.outputs.container-filename }}
70-
docker tag ${{ needs.build-ci-container-windows.outputs.container-name-tag }} ${{ needs.build-ci-container-windows.outputs.container-name }}:latest
71-
docker login -u ${{ github.actor }} -p $env:GITHUB_TOKEN ghcr.io
72-
docker push ${{ needs.build-ci-container-windows.outputs.container-name-tag }}
73-
docker push ${{ needs.build-ci-container-windows.outputs.container-name }}:latest
69+
sudo apt-get update
70+
sudo apt-get install -y skopeo
71+
skopeo login -u ${{ github.actor }} -p ${{ secrets.GITHUB_TOKEN }} ghcr.io
72+
skopeo copy docker-archive:${{ needs.build-ci-container-windows.outputs.container-filename }} \
73+
--dest-compress-format zstd \
74+
docker://${{ needs.build-ci-container-windows.outputs.container-name-tag }}
75+
skopeo copy docker-archive:${{ needs.build-ci-container-windows.outputs.container-filename }} \
76+
--dest-compress-format zstd \
77+
docker://${{ needs.build-ci-container-windows.outputs.container-name }}:latest

‎clang/lib/Format/WhitespaceManager.cpp‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1232,7 +1232,10 @@ void WhitespaceManager::alignArrayInitializers() {
12321232
bool FoundComplete = false;
12331233
for (unsigned InsideIndex = ChangeIndex + 1; InsideIndex < ChangeEnd;
12341234
++InsideIndex) {
1235-
if (Changes[InsideIndex].Tok == C.Tok->MatchingParen) {
1235+
const auto *Tok = Changes[InsideIndex].Tok;
1236+
if (Tok->is(tok::pp_define))
1237+
break;
1238+
if (Tok == C.Tok->MatchingParen) {
12361239
alignArrayInitializers(ChangeIndex, InsideIndex + 1);
12371240
ChangeIndex = InsideIndex + 1;
12381241
FoundComplete = true;

‎clang/unittests/Format/FormatTest.cpp‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22272,6 +22272,19 @@ TEST_F(FormatTest, CatchAlignArrayOfStructuresLeftAlignment) {
2227222272
"});",
2227322273
Style);
2227422274

22275+
verifyNoCrash(
22276+
"PANEL_Ic PANEL_ic[PANEL_IC_NUMBER] =\n"
22277+
" {\n"
22278+
" {PIC(0), PIC(0), PIC(99), PIC(81), 0}, // Backbox\n"
22279+
" {PIC(1), PIC(83), PIC(191), PIC(137), 0}, // AK47\n"
22280+
"\n"
22281+
"#define PICALL1(a, b, c, d) \\\n"
22282+
" { PIC(a), PIC(b), PIC(c), PIC(d), 1 }\n"
22283+
"\n"
22284+
" PICALL1(1, 1, 75, 50),\n"
22285+
"};",
22286+
Style);
22287+
2227522288
Style.AlignEscapedNewlines = FormatStyle::ENAS_DontAlign;
2227622289
verifyFormat("#define FOO \\\n"
2227722290
" int foo[][2] = { \\\n"

‎llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.cpp‎

Lines changed: 22 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -111,4 +111,25 @@ bool LoongArchTTIImpl::shouldExpandReduction(const IntrinsicInst *II) const {
111111
}
112112
}
113113

114-
// TODO: Implement more hooks to provide TTI machinery for LoongArch.
114+
LoongArchTTIImpl::TTI::MemCmpExpansionOptions
115+
LoongArchTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
116+
TTI::MemCmpExpansionOptions Options;
117+
118+
if (!ST->hasUAL())
119+
return Options;
120+
121+
Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize);
122+
Options.NumLoadsPerBlock = Options.MaxNumLoads;
123+
Options.AllowOverlappingLoads = true;
124+
125+
// TODO: Support for vectors.
126+
if (ST->is64Bit()) {
127+
Options.LoadSizes = {8, 4, 2, 1};
128+
Options.AllowedTailExpansions = {3, 5, 6};
129+
} else {
130+
Options.LoadSizes = {4, 2, 1};
131+
Options.AllowedTailExpansions = {3};
132+
}
133+
134+
return Options;
135+
}

‎llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -55,7 +55,8 @@ class LoongArchTTIImpl : public BasicTTIImplBase<LoongArchTTIImpl> {
5555

5656
bool shouldExpandReduction(const IntrinsicInst *II) const override;
5757

58-
// TODO: Implement more hooks to provide TTI machinery for LoongArch.
58+
TTI::MemCmpExpansionOptions
59+
enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const override;
5960
};
6061

6162
} // end namespace llvm

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

Lines changed: 76 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -87,6 +87,11 @@ static cl::opt<bool>
8787
"be combined with a shift"),
8888
cl::init(true));
8989

90+
// TODO: Support more ops
91+
static const unsigned ZvfbfaVPOps[] = {ISD::VP_FNEG, ISD::VP_FABS,
92+
ISD::VP_FCOPYSIGN};
93+
static const unsigned ZvfbfaOps[] = {ISD::FNEG, ISD::FABS, ISD::FCOPYSIGN};
94+
9095
RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
9196
const RISCVSubtarget &STI)
9297
: TargetLowering(TM), Subtarget(STI) {
@@ -1208,6 +1213,61 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
12081213
}
12091214
};
12101215

1216+
// Sets common actions for zvfbfa, some of instructions are supported
1217+
// natively so that we don't need to promote them.
1218+
const auto SetZvfbfaActions = [&](MVT VT) {
1219+
setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom);
1220+
setOperationAction({ISD::STRICT_FP_ROUND, ISD::STRICT_FP_EXTEND}, VT,
1221+
Custom);
1222+
setOperationAction({ISD::VP_FP_ROUND, ISD::VP_FP_EXTEND}, VT, Custom);
1223+
setOperationAction({ISD::LRINT, ISD::LLRINT}, VT, Custom);
1224+
setOperationAction({ISD::LROUND, ISD::LLROUND}, VT, Custom);
1225+
setOperationAction({ISD::VP_MERGE, ISD::VP_SELECT, ISD::SELECT}, VT,
1226+
Custom);
1227+
setOperationAction(ISD::SELECT_CC, VT, Expand);
1228+
setOperationAction({ISD::VP_SINT_TO_FP, ISD::VP_UINT_TO_FP}, VT, Custom);
1229+
setOperationAction({ISD::INSERT_VECTOR_ELT, ISD::CONCAT_VECTORS,
1230+
ISD::INSERT_SUBVECTOR, ISD::EXTRACT_SUBVECTOR,
1231+
ISD::VECTOR_DEINTERLEAVE, ISD::VECTOR_INTERLEAVE,
1232+
ISD::VECTOR_REVERSE, ISD::VECTOR_SPLICE,
1233+
ISD::VECTOR_COMPRESS},
1234+
VT, Custom);
1235+
setOperationAction(ISD::EXPERIMENTAL_VP_SPLICE, VT, Custom);
1236+
setOperationAction(ISD::EXPERIMENTAL_VP_REVERSE, VT, Custom);
1237+
1238+
setOperationAction(ISD::FCOPYSIGN, VT, Legal);
1239+
setOperationAction(ZvfbfaVPOps, VT, Custom);
1240+
1241+
MVT EltVT = VT.getVectorElementType();
1242+
if (isTypeLegal(EltVT))
1243+
setOperationAction({ISD::SPLAT_VECTOR, ISD::EXPERIMENTAL_VP_SPLAT,
1244+
ISD::EXTRACT_VECTOR_ELT},
1245+
VT, Custom);
1246+
else
1247+
setOperationAction({ISD::SPLAT_VECTOR, ISD::EXPERIMENTAL_VP_SPLAT},
1248+
EltVT, Custom);
1249+
setOperationAction({ISD::LOAD, ISD::STORE, ISD::MLOAD, ISD::MSTORE,
1250+
ISD::MGATHER, ISD::MSCATTER, ISD::VP_LOAD,
1251+
ISD::VP_STORE, ISD::EXPERIMENTAL_VP_STRIDED_LOAD,
1252+
ISD::EXPERIMENTAL_VP_STRIDED_STORE, ISD::VP_GATHER,
1253+
ISD::VP_SCATTER},
1254+
VT, Custom);
1255+
setOperationAction(ISD::VP_LOAD_FF, VT, Custom);
1256+
1257+
// Expand FP operations that need libcalls.
1258+
setOperationAction(FloatingPointLibCallOps, VT, Expand);
1259+
1260+
// Custom split nxv32[b]f16 since nxv32[b]f32 is not legal.
1261+
if (getLMUL(VT) == RISCVVType::LMUL_8) {
1262+
setOperationAction(ZvfhminZvfbfminPromoteOps, VT, Custom);
1263+
setOperationAction(ZvfhminZvfbfminPromoteVPOps, VT, Custom);
1264+
} else {
1265+
MVT F32VecVT = MVT::getVectorVT(MVT::f32, VT.getVectorElementCount());
1266+
setOperationPromotedToType(ZvfhminZvfbfminPromoteOps, VT, F32VecVT);
1267+
setOperationPromotedToType(ZvfhminZvfbfminPromoteVPOps, VT, F32VecVT);
1268+
}
1269+
};
1270+
12111271
if (Subtarget.hasVInstructionsF16()) {
12121272
for (MVT VT : F16VecVTs) {
12131273
if (!isTypeLegal(VT))
@@ -1222,7 +1282,13 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
12221282
}
12231283
}
12241284

1225-
if (Subtarget.hasVInstructionsBF16Minimal()) {
1285+
if (Subtarget.hasVInstructionsBF16()) {
1286+
for (MVT VT : BF16VecVTs) {
1287+
if (!isTypeLegal(VT))
1288+
continue;
1289+
SetZvfbfaActions(VT);
1290+
}
1291+
} else if (Subtarget.hasVInstructionsBF16Minimal()) {
12261292
for (MVT VT : BF16VecVTs) {
12271293
if (!isTypeLegal(VT))
12281294
continue;
@@ -1501,6 +1567,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
15011567
// available.
15021568
setOperationAction(ISD::BUILD_VECTOR, MVT::bf16, Custom);
15031569
}
1570+
if (Subtarget.hasStdExtZvfbfa()) {
1571+
setOperationAction(ZvfbfaOps, VT, Custom);
1572+
setOperationAction(ZvfbfaVPOps, VT, Custom);
1573+
}
15041574
setOperationAction(
15051575
{ISD::VP_MERGE, ISD::VP_SELECT, ISD::VSELECT, ISD::SELECT}, VT,
15061576
Custom);
@@ -7245,7 +7315,11 @@ static bool isPromotedOpNeedingSplit(SDValue Op,
72457315
return (Op.getValueType() == MVT::nxv32f16 &&
72467316
(Subtarget.hasVInstructionsF16Minimal() &&
72477317
!Subtarget.hasVInstructionsF16())) ||
7248-
Op.getValueType() == MVT::nxv32bf16;
7318+
(Op.getValueType() == MVT::nxv32bf16 &&
7319+
Subtarget.hasVInstructionsBF16Minimal() &&
7320+
(!Subtarget.hasVInstructionsBF16() ||
7321+
(!llvm::is_contained(ZvfbfaOps, Op.getOpcode()) &&
7322+
!llvm::is_contained(ZvfbfaVPOps, Op.getOpcode()))));
72497323
}
72507324

72517325
static SDValue SplitVectorOp(SDValue Op, SelectionDAG &DAG) {

‎llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td‎

Lines changed: 82 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -701,5 +701,86 @@ let Predicates = [HasStdExtZvfbfa] in {
701701
FRM_DYN,
702702
fvti.AVL, fvti.Log2SEW, TA_MA)>;
703703
}
704-
}
704+
705+
foreach vti = AllBF16Vectors in {
706+
// 13.12. Vector Floating-Point Sign-Injection Instructions
707+
def : Pat<(fabs (vti.Vector vti.RegClass:$rs)),
708+
(!cast<Instruction>("PseudoVFSGNJX_ALT_VV_"# vti.LMul.MX#"_E"#vti.SEW)
709+
(vti.Vector (IMPLICIT_DEF)),
710+
vti.RegClass:$rs, vti.RegClass:$rs, vti.AVL, vti.Log2SEW, TA_MA)>;
711+
// Handle fneg with VFSGNJN using the same input for both operands.
712+
def : Pat<(fneg (vti.Vector vti.RegClass:$rs)),
713+
(!cast<Instruction>("PseudoVFSGNJN_ALT_VV_"# vti.LMul.MX#"_E"#vti.SEW)
714+
(vti.Vector (IMPLICIT_DEF)),
715+
vti.RegClass:$rs, vti.RegClass:$rs, vti.AVL, vti.Log2SEW, TA_MA)>;
716+
717+
def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1),
718+
(vti.Vector vti.RegClass:$rs2))),
719+
(!cast<Instruction>("PseudoVFSGNJ_ALT_VV_"# vti.LMul.MX#"_E"#vti.SEW)
720+
(vti.Vector (IMPLICIT_DEF)),
721+
vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL, vti.Log2SEW, TA_MA)>;
722+
def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1),
723+
(vti.Vector (SplatFPOp vti.ScalarRegClass:$rs2)))),
724+
(!cast<Instruction>("PseudoVFSGNJ_ALT_V"#vti.ScalarSuffix#"_"#vti.LMul.MX#"_E"#vti.SEW)
725+
(vti.Vector (IMPLICIT_DEF)),
726+
vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, vti.AVL, vti.Log2SEW, TA_MA)>;
727+
728+
def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1),
729+
(vti.Vector (fneg vti.RegClass:$rs2)))),
730+
(!cast<Instruction>("PseudoVFSGNJN_ALT_VV_"# vti.LMul.MX#"_E"#vti.SEW)
731+
(vti.Vector (IMPLICIT_DEF)),
732+
vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL, vti.Log2SEW, TA_MA)>;
733+
def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1),
734+
(vti.Vector (fneg (SplatFPOp vti.ScalarRegClass:$rs2))))),
735+
(!cast<Instruction>("PseudoVFSGNJN_ALT_V"#vti.ScalarSuffix#"_"#vti.LMul.MX#"_E"#vti.SEW)
736+
(vti.Vector (IMPLICIT_DEF)),
737+
vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, vti.AVL, vti.Log2SEW, TA_MA)>;
738+
739+
// 13.12. Vector Floating-Point Sign-Injection Instructions
740+
def : Pat<(riscv_fabs_vl (vti.Vector vti.RegClass:$rs), (vti.Mask VMV0:$vm),
741+
VLOpFrag),
742+
(!cast<Instruction>("PseudoVFSGNJX_ALT_VV_"# vti.LMul.MX #"_E"#vti.SEW#"_MASK")
743+
(vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs,
744+
vti.RegClass:$rs, (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW,
745+
TA_MA)>;
746+
// Handle fneg with VFSGNJN using the same input for both operands.
747+
def : Pat<(riscv_fneg_vl (vti.Vector vti.RegClass:$rs), (vti.Mask VMV0:$vm),
748+
VLOpFrag),
749+
(!cast<Instruction>("PseudoVFSGNJN_ALT_VV_"# vti.LMul.MX#"_E"#vti.SEW #"_MASK")
750+
(vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs,
751+
vti.RegClass:$rs, (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW,
752+
TA_MA)>;
753+
754+
def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1),
755+
(vti.Vector vti.RegClass:$rs2),
756+
vti.RegClass:$passthru,
757+
(vti.Mask VMV0:$vm),
758+
VLOpFrag),
759+
(!cast<Instruction>("PseudoVFSGNJ_ALT_VV_"# vti.LMul.MX#"_E"#vti.SEW#"_MASK")
760+
vti.RegClass:$passthru, vti.RegClass:$rs1,
761+
vti.RegClass:$rs2, (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW,
762+
TAIL_AGNOSTIC)>;
763+
764+
def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1),
765+
(riscv_fneg_vl vti.RegClass:$rs2,
766+
(vti.Mask true_mask),
767+
VLOpFrag),
768+
srcvalue,
769+
(vti.Mask true_mask),
770+
VLOpFrag),
771+
(!cast<Instruction>("PseudoVFSGNJN_ALT_VV_"# vti.LMul.MX#"_E"#vti.SEW)
772+
(vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1,
773+
vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW, TA_MA)>;
774+
775+
def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1),
776+
(SplatFPOp vti.ScalarRegClass:$rs2),
777+
vti.RegClass:$passthru,
778+
(vti.Mask VMV0:$vm),
779+
VLOpFrag),
780+
(!cast<Instruction>("PseudoVFSGNJ_ALT_V"#vti.ScalarSuffix#"_"# vti.LMul.MX#"_E"#vti.SEW#"_MASK")
781+
vti.RegClass:$passthru, vti.RegClass:$rs1,
782+
vti.ScalarRegClass:$rs2, (vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW,
783+
TAIL_AGNOSTIC)>;
784+
}
785+
}
705786
} // Predicates = [HasStdExtZvfbfa]

0 commit comments

Comments
 (0)