Skip to content

Commit 7f2dcaa

Browse files
4vtomat4vtomat
authored
[NFC][RISCV] Move Zvfbf* relative stuffs to RISCVInstrInfoZvfbf.td (llvm#159619)
1 parent 8c18932 commit 7f2dcaa

File tree

5 files changed

+66
-60
lines changed

5 files changed

+66
-60
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfoV.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1838,5 +1838,5 @@ let Predicates = [HasVInstructionsI64, IsRV64] in {
18381838
}
18391839
} // Predicates = [HasVInstructionsI64, IsRV64]
18401840

1841-
include "RISCVInstrInfoZvfbf.td"
18421841
include "RISCVInstrInfoVPseudos.td"
1842+
include "RISCVInstrInfoZvfbf.td"

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td‎

Lines changed: 0 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -6450,8 +6450,6 @@ defm PseudoVFWMACC : VPseudoVWMAC_VV_VF_RM;
64506450
defm PseudoVFWNMACC : VPseudoVWMAC_VV_VF_RM;
64516451
defm PseudoVFWMSAC : VPseudoVWMAC_VV_VF_RM;
64526452
defm PseudoVFWNMSAC : VPseudoVWMAC_VV_VF_RM;
6453-
let Predicates = [HasStdExtZvfbfwma] in
6454-
defm PseudoVFWMACCBF16 : VPseudoVWMAC_VV_VF_BF_RM;
64556453
}
64566454

64576455
//===----------------------------------------------------------------------===//
@@ -6544,7 +6542,6 @@ defm PseudoVFWCVT_F_XU : VPseudoVWCVTF_V;
65446542
defm PseudoVFWCVT_F_X : VPseudoVWCVTF_V;
65456543

65466544
defm PseudoVFWCVT_F_F : VPseudoVWCVTD_V;
6547-
defm PseudoVFWCVTBF16_F_F : VPseudoVWCVTD_V;
65486545
} // mayRaiseFPException = true
65496546

65506547
//===----------------------------------------------------------------------===//
@@ -6561,7 +6558,6 @@ defm PseudoVFNCVT_F_XU : VPseudoVNCVTF_W_RM;
65616558
defm PseudoVFNCVT_F_X : VPseudoVNCVTF_W_RM;
65626559

65636560
defm PseudoVFNCVT_F_F : VPseudoVNCVTD_W_RM;
6564-
defm PseudoVFNCVTBF16_F_F : VPseudoVNCVTD_W_RM;
65656561

65666562
defm PseudoVFNCVT_ROD_F_F : VPseudoVNCVTD_W;
65676563
} // mayRaiseFPException = true
@@ -7090,9 +7086,6 @@ defm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwmsac", "PseudoVFWMSAC",
70907086
AllWidenableFloatVectors, isSEWAware=1>;
70917087
defm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwnmsac", "PseudoVFWNMSAC",
70927088
AllWidenableFloatVectors, isSEWAware=1>;
7093-
let Predicates = [HasStdExtZvfbfwma] in
7094-
defm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwmaccbf16", "PseudoVFWMACCBF16",
7095-
AllWidenableBFloatToFloatVectors, isSEWAware=1>;
70967089

70977090
//===----------------------------------------------------------------------===//
70987091
// 13.8. Vector Floating-Point Square-Root Instruction
@@ -7206,8 +7199,6 @@ defm : VPatConversionWF_VI<"int_riscv_vfwcvt_f_x_v", "PseudoVFWCVT_F_X",
72067199
isSEWAware=1>;
72077200
defm : VPatConversionWF_VF<"int_riscv_vfwcvt_f_f_v", "PseudoVFWCVT_F_F",
72087201
isSEWAware=1>;
7209-
defm : VPatConversionWF_VF_BF<"int_riscv_vfwcvtbf16_f_f_v",
7210-
"PseudoVFWCVTBF16_F_F", isSEWAware=1>;
72117202

72127203
//===----------------------------------------------------------------------===//
72137204
// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions
@@ -7224,8 +7215,6 @@ defm : VPatConversionVF_WI_RM<"int_riscv_vfncvt_f_x_w", "PseudoVFNCVT_F_X",
72247215
isSEWAware=1>;
72257216
defm : VPatConversionVF_WF_RM<"int_riscv_vfncvt_f_f_w", "PseudoVFNCVT_F_F",
72267217
AllWidenableFloatVectors, isSEWAware=1>;
7227-
defm : VPatConversionVF_WF_BF_RM<"int_riscv_vfncvtbf16_f_f_w",
7228-
"PseudoVFNCVTBF16_F_F", isSEWAware=1>;
72297218
defm : VPatConversionVF_WF<"int_riscv_vfncvt_rod_f_f_w", "PseudoVFNCVT_ROD_F_F",
72307219
isSEWAware=1>;
72317220

‎llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td‎

Lines changed: 0 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1315,8 +1315,6 @@ foreach fvti = AllFloatVectors in {
13151315
// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
13161316
defm : VPatWidenFPMulAccSDNode_VV_VF_RM<"PseudoVFWMACC",
13171317
AllWidenableFloatVectors>;
1318-
defm : VPatWidenFPMulAccSDNode_VV_VF_RM<"PseudoVFWMACCBF16",
1319-
AllWidenableBFloatToFloatVectors>;
13201318
defm : VPatWidenFPNegMulAccSDNode_VV_VF_RM<"PseudoVFWNMACC">;
13211319
defm : VPatWidenFPMulSacSDNode_VV_VF_RM<"PseudoVFWMSAC">;
13221320
defm : VPatWidenFPNegMulSacSDNode_VV_VF_RM<"PseudoVFWNMSAC">;
@@ -1460,20 +1458,6 @@ foreach fvtiToFWti = AllWidenableFloatVectors in {
14601458
fvti.AVL, fvti.Log2SEW, TA_MA)>;
14611459
}
14621460

1463-
foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in {
1464-
defvar fvti = fvtiToFWti.Vti;
1465-
defvar fwti = fvtiToFWti.Wti;
1466-
let Predicates = [HasVInstructionsBF16Minimal] in
1467-
def : Pat<(fvti.Vector (fpround (fwti.Vector fwti.RegClass:$rs1))),
1468-
(!cast<Instruction>("PseudoVFNCVTBF16_F_F_W_"#fvti.LMul.MX#"_E"#fvti.SEW)
1469-
(fvti.Vector (IMPLICIT_DEF)),
1470-
fwti.RegClass:$rs1,
1471-
// Value to indicate no rounding mode change in
1472-
// RISCVInsertReadWriteCSR
1473-
FRM_DYN,
1474-
fvti.AVL, fvti.Log2SEW, TA_MA)>;
1475-
}
1476-
14771461
//===----------------------------------------------------------------------===//
14781462
// Vector Element Extracts
14791463
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td‎

Lines changed: 0 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -2322,8 +2322,6 @@ defm : VPatFPMulAddVL_VV_VF_RM<any_riscv_vfnmsub_vl, "PseudoVFNMSUB">;
23222322

23232323
// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
23242324
defm : VPatWidenFPMulAccVL_VV_VF_RM<riscv_vfwmadd_vl, "PseudoVFWMACC">;
2325-
defm : VPatWidenFPMulAccVL_VV_VF_RM<riscv_vfwmadd_vl, "PseudoVFWMACCBF16",
2326-
AllWidenableBFloatToFloatVectors>;
23272325
defm : VPatWidenFPMulAccVL_VV_VF_RM<riscv_vfwnmadd_vl, "PseudoVFWNMACC">;
23282326
defm : VPatWidenFPMulAccVL_VV_VF_RM<riscv_vfwmsub_vl, "PseudoVFWMSAC">;
23292327
defm : VPatWidenFPMulAccVL_VV_VF_RM<riscv_vfwnmsub_vl, "PseudoVFWNMSAC">;
@@ -2541,20 +2539,6 @@ foreach fvtiToFWti = AllWidenableFloatVectors in {
25412539
GPR:$vl, fvti.Log2SEW, TA_MA)>;
25422540
}
25432541

2544-
foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in {
2545-
defvar fvti = fvtiToFWti.Vti;
2546-
defvar fwti = fvtiToFWti.Wti;
2547-
let Predicates = [HasVInstructionsBF16Minimal] in
2548-
def : Pat<(fwti.Vector (any_riscv_fpextend_vl
2549-
(fvti.Vector fvti.RegClass:$rs1),
2550-
(fvti.Mask VMV0:$vm),
2551-
VLOpFrag)),
2552-
(!cast<Instruction>("PseudoVFWCVTBF16_F_F_V_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK")
2553-
(fwti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1,
2554-
(fvti.Mask VMV0:$vm),
2555-
GPR:$vl, fvti.Log2SEW, TA_MA)>;
2556-
}
2557-
25582542
// 13.19 Narrowing Floating-Point/Integer Type-Convert Instructions
25592543
defm : VPatNConvertFP2I_RM_VL_W<riscv_vfcvt_rm_xu_f_vl, "PseudoVFNCVT_XU_F_W">;
25602544
defm : VPatNConvertFP2I_RM_VL_W<riscv_vfcvt_rm_x_f_vl, "PseudoVFNCVT_X_F_W">;
@@ -2596,22 +2580,6 @@ foreach fvtiToFWti = AllWidenableFloatVectors in {
25962580
}
25972581
}
25982582

2599-
foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in {
2600-
defvar fvti = fvtiToFWti.Vti;
2601-
defvar fwti = fvtiToFWti.Wti;
2602-
let Predicates = [HasVInstructionsBF16Minimal] in
2603-
def : Pat<(fvti.Vector (any_riscv_fpround_vl
2604-
(fwti.Vector fwti.RegClass:$rs1),
2605-
(fwti.Mask VMV0:$vm), VLOpFrag)),
2606-
(!cast<Instruction>("PseudoVFNCVTBF16_F_F_W_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK")
2607-
(fvti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1,
2608-
(fwti.Mask VMV0:$vm),
2609-
// Value to indicate no rounding mode change in
2610-
// RISCVInsertReadWriteCSR
2611-
FRM_DYN,
2612-
GPR:$vl, fvti.Log2SEW, TA_MA)>;
2613-
}
2614-
26152583
// 14. Vector Reduction Operations
26162584

26172585
// 14.1. Vector Single-Width Integer Reduction Instructions

‎llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td‎

Lines changed: 65 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,3 +32,68 @@ let Predicates = [HasStdExtZvfbfwma],
3232
DestEEW = EEWSEWx2 in {
3333
defm VFWMACCBF16_V : VWMAC_FV_V_F<"vfwmaccbf16", 0b111011>;
3434
}
35+
36+
//===----------------------------------------------------------------------===//
37+
// Pseudo instructions
38+
//===----------------------------------------------------------------------===//
39+
let Predicates = [HasStdExtZvfbfmin] in {
40+
defm PseudoVFWCVTBF16_F_F : VPseudoVWCVTD_V;
41+
defm PseudoVFNCVTBF16_F_F : VPseudoVNCVTD_W_RM;
42+
}
43+
44+
let mayRaiseFPException = true, Predicates = [HasStdExtZvfbfwma] in
45+
defm PseudoVFWMACCBF16 : VPseudoVWMAC_VV_VF_BF_RM;
46+
47+
//===----------------------------------------------------------------------===//
48+
// Patterns
49+
//===----------------------------------------------------------------------===//
50+
let Predicates = [HasStdExtZvfbfmin] in {
51+
defm : VPatConversionWF_VF_BF<"int_riscv_vfwcvtbf16_f_f_v",
52+
"PseudoVFWCVTBF16_F_F", isSEWAware=1>;
53+
defm : VPatConversionVF_WF_BF_RM<"int_riscv_vfncvtbf16_f_f_w",
54+
"PseudoVFNCVTBF16_F_F", isSEWAware=1>;
55+
56+
foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in {
57+
defvar fvti = fvtiToFWti.Vti;
58+
defvar fwti = fvtiToFWti.Wti;
59+
let Predicates = [HasVInstructionsBF16Minimal] in
60+
def : Pat<(fwti.Vector (any_riscv_fpextend_vl
61+
(fvti.Vector fvti.RegClass:$rs1),
62+
(fvti.Mask VMV0:$vm),
63+
VLOpFrag)),
64+
(!cast<Instruction>("PseudoVFWCVTBF16_F_F_V_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK")
65+
(fwti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1,
66+
(fvti.Mask VMV0:$vm),
67+
GPR:$vl, fvti.Log2SEW, TA_MA)>;
68+
69+
let Predicates = [HasVInstructionsBF16Minimal] in
70+
def : Pat<(fvti.Vector (any_riscv_fpround_vl
71+
(fwti.Vector fwti.RegClass:$rs1),
72+
(fwti.Mask VMV0:$vm), VLOpFrag)),
73+
(!cast<Instruction>("PseudoVFNCVTBF16_F_F_W_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK")
74+
(fvti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1,
75+
(fwti.Mask VMV0:$vm),
76+
// Value to indicate no rounding mode change in
77+
// RISCVInsertReadWriteCSR
78+
FRM_DYN,
79+
GPR:$vl, fvti.Log2SEW, TA_MA)>;
80+
let Predicates = [HasVInstructionsBF16Minimal] in
81+
def : Pat<(fvti.Vector (fpround (fwti.Vector fwti.RegClass:$rs1))),
82+
(!cast<Instruction>("PseudoVFNCVTBF16_F_F_W_"#fvti.LMul.MX#"_E"#fvti.SEW)
83+
(fvti.Vector (IMPLICIT_DEF)),
84+
fwti.RegClass:$rs1,
85+
// Value to indicate no rounding mode change in
86+
// RISCVInsertReadWriteCSR
87+
FRM_DYN,
88+
fvti.AVL, fvti.Log2SEW, TA_MA)>;
89+
}
90+
}
91+
92+
let Predicates = [HasStdExtZvfbfwma] in {
93+
defm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwmaccbf16", "PseudoVFWMACCBF16",
94+
AllWidenableBFloatToFloatVectors, isSEWAware=1>;
95+
defm : VPatWidenFPMulAccVL_VV_VF_RM<riscv_vfwmadd_vl, "PseudoVFWMACCBF16",
96+
AllWidenableBFloatToFloatVectors>;
97+
defm : VPatWidenFPMulAccSDNode_VV_VF_RM<"PseudoVFWMACCBF16",
98+
AllWidenableBFloatToFloatVectors>;
99+
}

0 commit comments

Comments
 (0)