SPARCMCCodeEmitter: Set PCRel at fixup creation

Author: MaskRay

llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp

@@ -91,6 +91,21 @@ class SparcMCCodeEmitter : public MCCodeEmitter {
 
 } // end anonymous namespace
 
+static void addFixup(SmallVectorImpl<MCFixup> &Fixups, uint32_t Offset,
+                     const MCExpr *Value, uint16_t Kind) {
+  bool PCRel = false;
+  switch (Kind) {
+  case ELF::R_SPARC_PC10:
+  case ELF::R_SPARC_PC22:
+  case ELF::R_SPARC_WDISP10:
+  case ELF::R_SPARC_WDISP16:
+  case ELF::R_SPARC_WDISP19:
+  case ELF::R_SPARC_WDISP22:
+    PCRel = true;
+  }
+  Fixups.push_back(MCFixup::create(Offset, Value, Kind, PCRel));
+}
+
 void SparcMCCodeEmitter::encodeInstruction(const MCInst &MI,
                                            SmallVectorImpl<char> &CB,
                                            SmallVectorImpl<MCFixup> &Fixups,
@@ -135,7 +150,7 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
   assert(MO.isExpr());
   const MCExpr *Expr = MO.getExpr();
   if (auto *SExpr = dyn_cast<MCSpecifierExpr>(Expr)) {
-    Fixups.push_back(MCFixup::create(0, Expr, SExpr->getSpecifier()));
+    addFixup(Fixups, 0, Expr, SExpr->getSpecifier());
     return 0;
   }
 
@@ -165,10 +180,10 @@ unsigned SparcMCCodeEmitter::getSImm5OpValue(const MCInst &MI, unsigned OpNo,
     return CE->getValue();
 
   if (auto *SExpr = dyn_cast<MCSpecifierExpr>(Expr)) {
-    Fixups.push_back(MCFixup::create(0, Expr, SExpr->getSpecifier()));
+    addFixup(Fixups, 0, Expr, SExpr->getSpecifier());
     return 0;
   }
-  Fixups.push_back(MCFixup::create(0, Expr, ELF::R_SPARC_5));
+  addFixup(Fixups, 0, Expr, ELF::R_SPARC_5);
   return 0;
 }
 
@@ -191,10 +206,10 @@ SparcMCCodeEmitter::getSImm13OpValue(const MCInst &MI, unsigned OpNo,
     return CE->getValue();
 
   if (auto *SExpr = dyn_cast<MCSpecifierExpr>(Expr)) {
-    Fixups.push_back(MCFixup::create(0, Expr, SExpr->getSpecifier()));
+    addFixup(Fixups, 0, Expr, SExpr->getSpecifier());
     return 0;
   }
-  Fixups.push_back(MCFixup::create(0, Expr, Sparc::fixup_sparc_13));
+  addFixup(Fixups, 0, Expr, Sparc::fixup_sparc_13);
   return 0;
 }
 
@@ -209,7 +224,7 @@ getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
   }
 
   const MCOperand &MO = MI.getOperand(OpNo);
-  Fixups.push_back(MCFixup::create(0, MO.getExpr(), Sparc::fixup_sparc_call30));
+  addFixup(Fixups, 0, MO.getExpr(), Sparc::fixup_sparc_call30);
   return 0;
 }
 
@@ -221,7 +236,7 @@ getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
   if (MO.isReg() || MO.isImm())
     return getMachineOpValue(MI, MO, Fixups, STI);
 
-  Fixups.push_back(MCFixup::create(0, MO.getExpr(), ELF::R_SPARC_WDISP22));
+  addFixup(Fixups, 0, MO.getExpr(), ELF::R_SPARC_WDISP22);
   return 0;
 }
 
@@ -232,7 +247,7 @@ unsigned SparcMCCodeEmitter::getBranchPredTargetOpValue(
   if (MO.isReg() || MO.isImm())
     return getMachineOpValue(MI, MO, Fixups, STI);
 
-  Fixups.push_back(MCFixup::create(0, MO.getExpr(), ELF::R_SPARC_WDISP19));
+  addFixup(Fixups, 0, MO.getExpr(), ELF::R_SPARC_WDISP19);
   return 0;
 }
 
@@ -243,8 +258,7 @@ unsigned SparcMCCodeEmitter::getBranchOnRegTargetOpValue(
   if (MO.isReg() || MO.isImm())
     return getMachineOpValue(MI, MO, Fixups, STI);
 
-  Fixups.push_back(MCFixup::create(0, MO.getExpr(), ELF::R_SPARC_WDISP16));
-
+  addFixup(Fixups, 0, MO.getExpr(), ELF::R_SPARC_WDISP16);
   return 0;
 }
 
@@ -255,8 +269,7 @@ unsigned SparcMCCodeEmitter::getCompareAndBranchTargetOpValue(
   if (MO.isImm())
     return getMachineOpValue(MI, MO, Fixups, STI);
 
-  Fixups.push_back(MCFixup::create(0, MO.getExpr(), ELF::R_SPARC_WDISP10));
-
+  addFixup(Fixups, 0, MO.getExpr(), ELF::R_SPARC_WDISP10);
   return 0;
 }