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[AArch64] FEAT_SPEv1p2 is optional in v8.7-A and v9.2-A (llvm#123336)
The FEAT_SPEv1p2 feature (known to LLVM as FeatureSPE_EEF and +spe-eef) was incorrectly marked as a required feature of Armv8.7-A (and later), which is incorrect because it is optional, and some CPUs do not implement it. This moves it to the default features list, so that it is still enabled by -march=armv8.7-a, but can be configured individually for each processor. For Cortex-A520 and Cortex-A520AE, I've checked that these do not have any of the FEAT_SPE* features, so updated the tests accordingly. All other Arm-designed v8.7A+ and v9.2A+ CPUs should continue to have it enabled. For Ampere1B and Fujitsu Monaka, these CPUs do not have the feature, so I've removed it from their tests. For Apple M4, I haven't found any reference for whether that CPU should have this feature, so I've added it to the CPU definition to avoid this being a functional change.
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‎clang/test/CodeGen/AArch64/targetattr.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -218,7 +218,7 @@ void applem4() {}
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// CHECK: attributes #[[ATTR15]] = { noinline nounwind optnone "branch-target-enforcement" "guarded-control-stack" "no-trapping-math"="true" "sign-return-address"="non-leaf" "sign-return-address-key"="a_key" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
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// CHECK: attributes #[[ATTR16]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
220220
// CHECK: attributes #[[ATTR17]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-v9.3a" }
221-
// CHECK: attributes #[[ATTR18]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="apple-m4" "target-features"="+aes,+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fpac,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+sha3,+sme,+sme-f64f64,+sme-i16i64,+sme2,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8a,+wfxt" }
221+
// CHECK: attributes #[[ATTR18]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="apple-m4" "target-features"="+aes,+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fpac,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+sha3,+sme,+sme-f64f64,+sme-i16i64,+sme2,+spe-eef,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8a,+wfxt" }
222222
//.
223223
// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
224224
// CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}

‎clang/test/Driver/print-enabled-extensions/aarch64-ampere1b.c‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,6 @@
5151
// CHECK-NEXT: FEAT_SHA3, FEAT_SHA512 Enable SHA512 and SHA3 support
5252
// CHECK-NEXT: FEAT_SM4, FEAT_SM3 Enable SM3 and SM4 support
5353
// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
54-
// CHECK-NEXT: FEAT_SPEv1p2 Enable extra register in the Statistical Profiling Extension
5554
// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
5655
// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions
5756
// CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension

‎clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520.c‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -46,7 +46,6 @@
4646
// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier
4747
// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
4848
// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
49-
// CHECK-NEXT: FEAT_SPEv1p2 Enable extra register in the Statistical Profiling Extension
5049
// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
5150
// CHECK-NEXT: FEAT_SVE Enable Scalable Vector Extension (SVE) instructions
5251
// CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions

‎clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520ae.c‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -46,7 +46,6 @@
4646
// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier
4747
// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
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// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
49-
// CHECK-NEXT: FEAT_SPEv1p2 Enable extra register in the Statistical Profiling Extension
5049
// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
5150
// CHECK-NEXT: FEAT_SVE Enable Scalable Vector Extension (SVE) instructions
5251
// CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions

‎clang/test/Driver/print-enabled-extensions/aarch64-fujitsu-monaka.c‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -63,7 +63,6 @@
6363
// CHECK-NEXT: FEAT_SM4, FEAT_SM3 Enable SM3 and SM4 support
6464
// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
6565
// CHECK-NEXT: FEAT_SPECRES2 Enable Speculation Restriction Instruction
66-
// CHECK-NEXT: FEAT_SPEv1p2 Enable extra register in the Statistical Profiling Extension
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// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
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// CHECK-NEXT: FEAT_SVE Enable Scalable Vector Extension (SVE) instructions
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// CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions
@@ -77,4 +76,4 @@
7776
// CHECK-NEXT: FEAT_UAO Enable Armv8.2-A UAO PState
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// CHECK-NEXT: FEAT_VHE Enable Armv8.1-A Virtual Host extension
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// CHECK-NEXT: FEAT_WFxT Enable Armv8.7-A WFET and WFIT instruction
80-
// CHECK-NEXT: FEAT_XS Enable Armv8.7-A limited-TLB-maintenance instruction
79+
// CHECK-NEXT: FEAT_XS Enable Armv8.7-A limited-TLB-maintenance instruction

‎llvm/lib/Target/AArch64/AArch64Features.td‎

Lines changed: 9 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -859,8 +859,8 @@ def HasV8_6aOps : Architecture64<8, 6, "a", "v8.6a",
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FeatureEnhancedCounterVirtualization, FeatureMatMulInt8],
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!listconcat(HasV8_5aOps.DefaultExts, [FeatureBF16, FeatureMatMulInt8])>;
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def HasV8_7aOps : Architecture64<8, 7, "a", "v8.7a",
862-
[HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX, FeatureSPE_EEF],
863-
!listconcat(HasV8_6aOps.DefaultExts, [FeatureWFxT])>;
862+
[HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX],
863+
!listconcat(HasV8_6aOps.DefaultExts, [FeatureWFxT, FeatureSPE_EEF])>;
864864
def HasV8_8aOps : Architecture64<8, 8, "a", "v8.8a",
865865
[HasV8_7aOps, FeatureHBC, FeatureMOPS, FeatureNMI],
866866
!listconcat(HasV8_7aOps.DefaultExts, [FeatureMOPS, FeatureHBC])>;
@@ -875,17 +875,19 @@ def HasV9_0aOps : Architecture64<9, 0, "a", "v9a",
875875
FeatureSVE2])>;
876876
def HasV9_1aOps : Architecture64<9, 1, "a", "v9.1a",
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[HasV8_6aOps, HasV9_0aOps],
878-
!listconcat(HasV9_0aOps.DefaultExts, [FeatureBF16, FeatureMatMulInt8, FeatureRME])>;
878+
!listconcat(HasV9_0aOps.DefaultExts, HasV8_6aOps.DefaultExts,
879+
[FeatureRME])>;
879880
def HasV9_2aOps : Architecture64<9, 2, "a", "v9.2a",
880881
[HasV8_7aOps, HasV9_1aOps],
881-
!listconcat(HasV9_1aOps.DefaultExts, [FeatureMEC, FeatureWFxT])>;
882+
!listconcat(HasV9_1aOps.DefaultExts, HasV8_7aOps.DefaultExts,
883+
[FeatureMEC])>;
882884
def HasV9_3aOps : Architecture64<9, 3, "a", "v9.3a",
883885
[HasV8_8aOps, HasV9_2aOps],
884-
!listconcat(HasV9_2aOps.DefaultExts, [FeatureMOPS, FeatureHBC])>;
886+
!listconcat(HasV9_2aOps.DefaultExts, HasV8_8aOps.DefaultExts, [])>;
885887
def HasV9_4aOps : Architecture64<9, 4, "a", "v9.4a",
886888
[HasV8_9aOps, HasV9_3aOps],
887-
!listconcat(HasV9_3aOps.DefaultExts, [FeatureSPECRES2, FeatureCSSC,
888-
FeatureRASv2, FeatureSVE2p1])>;
889+
!listconcat(HasV9_3aOps.DefaultExts, HasV8_9aOps.DefaultExts,
890+
[FeatureSVE2p1])>;
889891
def HasV9_5aOps : Architecture64<9, 5, "a", "v9.5a",
890892
[HasV9_4aOps, FeatureCPA],
891893
!listconcat(HasV9_4aOps.DefaultExts, [FeatureCPA, FeatureLUT, FeatureFAMINMAX])>;

‎llvm/lib/Target/AArch64/AArch64Processors.td‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -929,7 +929,8 @@ def ProcessorFeatures {
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FeatureComplxNum, FeatureCRC, FeatureJS,
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FeatureLSE, FeaturePAuth, FeatureFPAC,
931931
FeatureRAS, FeatureRCPC, FeatureRDM,
932-
FeatureDotProd, FeatureMatMulInt8];
932+
FeatureDotProd, FeatureMatMulInt8,
933+
FeatureSPE_EEF];
933934
list<SubtargetFeature> ExynosM3 = [HasV8_0aOps, FeatureCRC, FeatureSHA2, FeatureAES,
934935
FeaturePerfMon, FeatureNEON, FeatureFPARMv8];
935936
list<SubtargetFeature> ExynosM4 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureDotProd,

‎llvm/test/MC/AArch64/spe.s‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
// RUN: llvm-mc -triple aarch64 -mattr +spe-eef -show-encoding %s 2>%t | FileCheck %s
2-
// RUN: llvm-mc -triple aarch64 -mattr +v8.7a -show-encoding %s 2>%t | FileCheck %s
2+
// RUN: not llvm-mc -triple aarch64 -mattr +v8.7a %s 2>&1 | FileCheck --check-prefix=CHECK-NO-SPE-EEF-ERR %s
33
// RUN: not llvm-mc -triple aarch64 < %s 2>&1 | FileCheck --check-prefix=CHECK-NO-SPE-EEF-ERR %s
44

55
msr PMSNEVFR_EL1, x0

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