[AMDGPU] Change SGPR layout to striped caller/callee saved (llvm#127353) (llvm#1103)

Author: shiltian

llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td

@@ -155,7 +155,15 @@ def CSR_AMDGPU_AGPRs : CalleeSavedRegs<
 >;
 
 def CSR_AMDGPU_SGPRs : CalleeSavedRegs<
-  (sequence "SGPR%u", 30, 105)
+  // Ensure that s30-s31 (return address), s32 (stack pointer), s33 (frame pointer),
+  // and s34 (base pointer) are callee-saved. The striped layout starts from s40,
+  // with a stripe width of 8. The last stripe is 10 wide instead of 8, to avoid
+  // ending with a 2-wide stripe.
+  (add (sequence "SGPR%u", 30, 39),
+       (sequence "SGPR%u", 48, 55),
+       (sequence "SGPR%u", 64, 71),
+       (sequence "SGPR%u", 80, 87),
+       (sequence "SGPR%u", 96, 105))
 >;
 
 def CSR_AMDGPU_SI_Gfx_SGPRs : CalleeSavedRegs<

llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

@@ -2041,6 +2041,9 @@ void SILoadStoreOptimizer::processBaseWithConstOffset(const MachineOperand &Base
     BaseLo = *Src0;
   }
 
+  if (!BaseLo.isReg())
+    return;
+
   Src0 = TII->getNamedOperand(*BaseHiDef, AMDGPU::OpName::src0);
   Src1 = TII->getNamedOperand(*BaseHiDef, AMDGPU::OpName::src1);
 
@@ -2053,6 +2056,9 @@ void SILoadStoreOptimizer::processBaseWithConstOffset(const MachineOperand &Base
   uint64_t Offset1 = Src1->getImm();
   BaseHi = *Src0;
 
+  if (!BaseHi.isReg())
+    return;
+
   Addr.Base.LoReg = BaseLo.getReg();
   Addr.Base.HiReg = BaseHi.getReg();
   Addr.Base.LoSubReg = BaseLo.getSubReg();