[Comgr][SPIRV][Cache] Support for caching of spirv converstion to bitcode (#524)

Author: jmmartinez

amd/comgr/CMakeLists.txt

@@ -82,6 +82,7 @@ set(SOURCES
   src/comgr-metadata.cpp
   src/comgr-objdump.cpp
   src/comgr-signal.cpp
+  src/comgr-spirv-command.cpp
   src/comgr-symbol.cpp
   src/comgr-symbolizer.cpp
   src/time-stat/time-stat.cpp)

amd/comgr/src/comgr-cache-command.h

@@ -50,7 +50,8 @@ class raw_ostream;
 namespace COMGR {
 class CachedCommandAdaptor {
 public:
-  using ActionClass = clang::driver::Action::ActionClass;
+  using ActionClass =
+      std::underlying_type_t<clang::driver::Action::ActionClass>;
   using HashAlgorithm = llvm::SHA256;
   using Identifier = llvm::SmallString<64>;
 

amd/comgr/src/comgr-compiler.cpp

@@ -42,6 +42,7 @@
 #include "comgr-device-libs.h"
 #include "comgr-diagnostic-handler.h"
 #include "comgr-env.h"
+#include "comgr-spirv-command.h"
 #include "lld/Common/CommonLinkerContext.h"
 #include "lld/Common/Driver.h"
 #include "clang/CodeGen/CodeGenAction.h"
@@ -86,10 +87,6 @@
 #include "llvm/Support/WithColor.h"
 #include "llvm/TargetParser/Host.h"
 
-#ifndef COMGR_DISABLE_SPIRV
-#include "LLVMSPIRVLib/LLVMSPIRVLib.h"
-#endif
-
 #include "time-stat/ts-interface.h"
 
 #include <csignal>
@@ -1899,9 +1896,7 @@ amd_comgr_status_t AMDGPUCompiler::translateSpirvToBitcode() {
     return Status;
   }
 
-  LLVMContext Context;
-  Context.setDiagnosticHandler(
-      std::make_unique<AMDGPUCompilerDiagnosticHandler>(this->LogS), true);
+  auto Cache = CommandCache::get(LogS);
 
   for (auto *Input : InSet->DataObjects) {
 
@@ -1915,28 +1910,19 @@ amd_comgr_status_t AMDGPUCompiler::translateSpirvToBitcode() {
       return AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT;
     }
 
-    // TODO: With C++23, we should investigate replacing with spanstream
-    // to avoid memory copies:
-    //  https://en.cppreference.com/w/cpp/io/basic_ispanstream
-    std::istringstream ISS(std::string(Input->Data, Input->Size));
-
-    llvm::Module *M;
-    std::string Err;
-
-    SPIRV::TranslatorOpts Opts;
-    Opts.enableAllExtensions();
-    Opts.setDesiredBIsRepresentation(SPIRV::BIsRepresentation::OpenCL20);
+    SmallString<0> OutBuf;
+    SPIRVCommand SPIRV(Input, OutBuf);
 
-    if (!llvm::readSpirv(Context, Opts, ISS, M, Err)) {
-      LogS << "Failed to load SPIR-V as LLVM Module: " << Err << '\n';
-      return AMD_COMGR_STATUS_ERROR;
+    amd_comgr_status_t Status;
+    if (!Cache) {
+      Status = SPIRV.execute(LogS);
+    } else {
+      Status = Cache->execute(SPIRV, LogS);
     }
 
-    SmallString<0> OutBuf;
-    BitcodeWriter Writer(OutBuf);
-    Writer.writeModule(*M, false, nullptr, false, nullptr);
-    Writer.writeSymtab();
-    Writer.writeStrtab();
+    if (Status) {
+      return Status;
+    }
 
     amd_comgr_data_t OutputT;
     if (auto Status = amd_comgr_create_data(AMD_COMGR_DATA_KIND_BC, &OutputT)) {

amd/comgr/src/comgr-spirv-command.cpp

@@ -0,0 +1,109 @@
+/*******************************************************************************
+ *
+ * University of Illinois/NCSA
+ * Open Source License
+ *
+ * Copyright (c) 2003-2017 University of Illinois at Urbana-Champaign.
+ * Modifications (c) 2018 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * with the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ *     * Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimers.
+ *
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimers in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *     * Neither the names of the LLVM Team, University of Illinois at
+ *       Urbana-Champaign, nor the names of its contributors may be used to
+ *       endorse or promote products derived from this Software without specific
+ *       prior written permission.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+ * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH
+ * THE SOFTWARE.
+ *
+ ******************************************************************************/
+
+#include "comgr-spirv-command.h"
+
+#ifndef COMGR_DISABLE_SPIRV
+#include "comgr-diagnostic-handler.h"
+
+#include <LLVMSPIRVLib/LLVMSPIRVLib.h>
+#include <llvm/Bitcode/BitcodeWriter.h>
+#include <llvm/IR/LLVMContext.h>
+
+#include <sstream>
+#endif
+
+namespace COMGR {
+using namespace llvm;
+Error SPIRVCommand::writeExecuteOutput(StringRef CachedBuffer) {
+  assert(OutputBuffer.empty());
+  OutputBuffer.reserve(CachedBuffer.size());
+  OutputBuffer.insert(OutputBuffer.end(), CachedBuffer.begin(),
+                      CachedBuffer.end());
+  return Error::success();
+}
+
+Expected<StringRef> SPIRVCommand::readExecuteOutput() {
+  return StringRef(OutputBuffer.data(), OutputBuffer.size());
+}
+
+amd_comgr_status_t SPIRVCommand::execute(raw_ostream &LogS) {
+#ifndef COMGR_DISABLE_SPIRV
+  LLVMContext Context;
+  Context.setDiagnosticHandler(
+      std::make_unique<AMDGPUCompilerDiagnosticHandler>(LogS), true);
+
+  // TODO: With C++23, we should investigate replacing with spanstream
+  // to avoid memory copies:
+  //  https://en.cppreference.com/w/cpp/io/basic_ispanstream
+  std::istringstream ISS(std::string(InputBuffer.data(), InputBuffer.size()));
+
+  Module *M;
+  std::string Err;
+
+  if (!readSpirv(Context, ISS, M, Err)) {
+    LogS << "Failed to load SPIR-V as LLVM Module: " << Err << '\n';
+    return AMD_COMGR_STATUS_ERROR;
+  }
+
+  BitcodeWriter Writer(OutputBuffer);
+  Writer.writeModule(*M, false, nullptr, false, nullptr);
+  Writer.writeSymtab();
+  Writer.writeStrtab();
+  return AMD_COMGR_STATUS_SUCCESS;
+#else
+  return AMD_COMGR_STATUS_ERROR;
+#endif
+}
+
+SPIRVCommand::ActionClass SPIRVCommand::getClass() const {
+  // return an action class that is not allocated to distinguish it from any
+  // clang action
+  return clang::driver::Action::ActionClass::JobClassLast + 1;
+}
+
+void SPIRVCommand::addOptionsIdentifier(HashAlgorithm &) const {
+  // do nothing, there are no options
+  return;
+}
+
+Error SPIRVCommand::addInputIdentifier(HashAlgorithm &H) const {
+  addString(H, InputBuffer);
+  return Error::success();
+}
+} // namespace COMGR

amd/comgr/src/comgr-spirv-command.h

@@ -0,0 +1,69 @@
+/*******************************************************************************
+ *
+ * University of Illinois/NCSA
+ * Open Source License
+ *
+ * Copyright (c) 2003-2017 University of Illinois at Urbana-Champaign.
+ * Modifications (c) 2018 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * with the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ *     * Redistributions of source code must retain the above copyright notice,
+ *       this list of conditions and the following disclaimers.
+ *
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimers in the
+ *       documentation and/or other materials provided with the distribution.
+ *
+ *     * Neither the names of the LLVM Team, University of Illinois at
+ *       Urbana-Champaign, nor the names of its contributors may be used to
+ *       endorse or promote products derived from this Software without specific
+ *       prior written permission.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+ * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH
+ * THE SOFTWARE.
+ *
+ ******************************************************************************/
+
+#ifndef COMGR_SPIRV_COMMAND_H
+#define COMGR_SPIRV_COMMAND_H
+
+#include "comgr-cache-command.h"
+#include "comgr.h"
+
+namespace COMGR {
+class SPIRVCommand : public CachedCommandAdaptor {
+public:
+  llvm::StringRef InputBuffer;
+  llvm::SmallVectorImpl<char> &OutputBuffer;
+
+public:
+  SPIRVCommand(DataObject *Input, llvm::SmallVectorImpl<char> &OutputBuffer)
+      : InputBuffer(Input->Data, Input->Size), OutputBuffer(OutputBuffer) {}
+
+  bool canCache() const final { return true; }
+  llvm::Error writeExecuteOutput(llvm::StringRef CachedBuffer) final;
+  llvm::Expected<llvm::StringRef> readExecuteOutput() final;
+  amd_comgr_status_t execute(llvm::raw_ostream &LogS) final;
+
+  ~SPIRVCommand() override = default;
+
+protected:
+  ActionClass getClass() const override;
+  void addOptionsIdentifier(HashAlgorithm &) const override;
+  llvm::Error addInputIdentifier(HashAlgorithm &) const override;
+};
+} // namespace COMGR
+
+#endif

amd/comgr/test-lit/spirv-translator-cached.cl

@@ -0,0 +1,17 @@
+// REQUIRES: comgr-has-spirv
+// COM: Same as spirv-translator but with the cache
+
+// COM: Generate a spirv-targeted LLVM IR file from an OpenCL kernel
+// RUN: clang -c -emit-llvm --target=spirv64 %s -o %t.bc
+
+// COM: Translate LLVM IR to SPIRV format
+// RUN: amd-llvm-spirv --spirv-target-env=CL2.0 %t.bc -o %t.spv
+
+// COM: Run Comgr Translator to covert SPIRV back to LLVM IR
+// RUN: export AMD_COMGR_CACHE=1
+// RUN: AMD_COMGR_CACHE_DIR=%t.cache spirv-translator %t.spv -o %t.translated.bc
+// RUN: COUNT=$(ls "%t.cache" | wc -l)
+// RUN: [ 2 -eq $COUNT ]
+
+// COM: Dissasemble LLVM IR bitcode to LLVM IR text
+// RUN: llvm-dis %t.translated.bc -o - | FileCheck %S/spirv-translator.cl