2626#include " llvm/MC/MCSubtargetInfo.h"
2727#include " llvm/MC/TargetRegistry.h"
2828#include " llvm/Support/Compiler.h"
29- #include < bitset>
3029
3130#define GET_INSTRINFO_MC_DESC
3231#define ENABLE_INSTR_PREDICATE_VERIFIER
@@ -96,79 +95,10 @@ createLoongArchAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS,
9695namespace {
9796
9897class LoongArchMCInstrAnalysis : public MCInstrAnalysis {
99- int64_t GPRState[31 ] = {};
100- std::bitset<31 > GPRValidMask;
101-
102- static bool isGPR (MCRegister Reg) {
103- return Reg >= LoongArch::R0 && Reg <= LoongArch::R31;
104- }
105-
106- static unsigned getRegIndex (MCRegister Reg) {
107- assert (isGPR (Reg) && Reg != LoongArch::R0 && " Invalid GPR reg" );
108- return Reg - LoongArch::R1;
109- }
110-
111- void setGPRState (MCRegister Reg, std::optional<int64_t > Value) {
112- if (Reg == LoongArch::R0)
113- return ;
114-
115- auto Index = getRegIndex (Reg);
116-
117- if (Value) {
118- GPRState[Index] = *Value;
119- GPRValidMask.set (Index);
120- } else {
121- GPRValidMask.reset (Index);
122- }
123- }
124-
125- std::optional<int64_t > getGPRState (MCRegister Reg) const {
126- if (Reg == LoongArch::R0)
127- return 0 ;
128-
129- auto Index = getRegIndex (Reg);
130-
131- if (GPRValidMask.test (Index))
132- return GPRState[Index];
133- return std::nullopt ;
134- }
135-
13698public:
13799 explicit LoongArchMCInstrAnalysis (const MCInstrInfo *Info)
138100 : MCInstrAnalysis(Info) {}
139101
140- void resetState () override { GPRValidMask.reset (); }
141-
142- void updateState (const MCInst &Inst, uint64_t Addr) override {
143- // Terminators mark the end of a basic block which means the sequentially
144- // next instruction will be the first of another basic block and the current
145- // state will typically not be valid anymore. For calls, we assume all
146- // registers may be clobbered by the callee (TODO: should we take the
147- // calling convention into account?).
148- if (isTerminator (Inst) || isCall (Inst)) {
149- resetState ();
150- return ;
151- }
152-
153- switch (Inst.getOpcode ()) {
154- default : {
155- // Clear the state of all defined registers for instructions that we don't
156- // explicitly support.
157- auto NumDefs = Info->get (Inst.getOpcode ()).getNumDefs ();
158- for (unsigned I = 0 ; I < NumDefs; ++I) {
159- auto DefReg = Inst.getOperand (I).getReg ();
160- if (isGPR (DefReg))
161- setGPRState (DefReg, std::nullopt );
162- }
163- break ;
164- }
165- case LoongArch::PCADDU18I:
166- setGPRState (Inst.getOperand (0 ).getReg (),
167- Addr + SignExtend64<32 >(Inst.getOperand (1 ).getImm () << 18 ));
168- break ;
169- }
170- }
171-
172102 bool evaluateBranch (const MCInst &Inst, uint64_t Addr, uint64_t Size,
173103 uint64_t &Target) const override {
174104 unsigned NumOps = Inst.getNumOperands ();
@@ -178,14 +108,6 @@ class LoongArchMCInstrAnalysis : public MCInstrAnalysis {
178108 return true ;
179109 }
180110
181- if (Inst.getOpcode () == LoongArch::JIRL) {
182- if (auto TargetRegState = getGPRState (Inst.getOperand (1 ).getReg ())) {
183- Target = *TargetRegState + Inst.getOperand (2 ).getImm ();
184- return true ;
185- }
186- return false ;
187- }
188-
189111 return false ;
190112 }
191113
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