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[RFC][AMDGPU] Remove old llvm.amdgcn.buffer.* and tbuffer intrinsics (llvm#93801)
Relanding may need MIOpen to change intrinsic usage They have been superseded by llvm.amdgcn.raw.buffer.* and llvm.amdgcn.struct.buffer.*. Change-Id: Ief3057b3a8c1d9a0b9188a506424a43929c1c47a
1 parent ff7f99b commit 90c5c16

36 files changed

+122
-4037
lines changed

‎llvm/docs/TableGen/BackGuide.rst‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -761,7 +761,7 @@ over time. The output looks like this.
761761
762762
-------------------- Global Variables (5) --------------------
763763
764-
AMDGPUBufferIntrinsics = [int_amdgcn_buffer_load_format, ...
764+
AMDGPUBufferIntrinsics = [int_amdgcn_s_buffer_load, ...
765765
AMDGPUImageDimAtomicIntrinsics = [int_amdgcn_image_atomic_swap_1d, ...
766766
...
767767
-------------------- Classes (758) --------------------

‎llvm/include/llvm/IR/IntrinsicsAMDGPU.td‎

Lines changed: 3 additions & 107 deletions
Original file line numberDiff line numberDiff line change
@@ -1094,18 +1094,6 @@ def int_amdgcn_make_buffer_rsrc : DefaultAttrsIntrinsic <
10941094

10951095
defset list<AMDGPURsrcIntrinsic> AMDGPUBufferIntrinsics = {
10961096

1097-
class AMDGPUBufferLoad<LLVMType data_ty = llvm_any_ty> : DefaultAttrsIntrinsic <
1098-
[data_ty],
1099-
[llvm_v4i32_ty, // rsrc(SGPR)
1100-
llvm_i32_ty, // vindex(VGPR)
1101-
llvm_i32_ty, // offset(SGPR/VGPR/imm)
1102-
llvm_i1_ty, // glc(imm)
1103-
llvm_i1_ty], // slc(imm)
1104-
[IntrReadMem, ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>], "", [SDNPMemOperand]>,
1105-
AMDGPURsrcIntrinsic<0>;
1106-
def int_amdgcn_buffer_load_format : AMDGPUBufferLoad<llvm_anyfloat_ty>;
1107-
def int_amdgcn_buffer_load : AMDGPUBufferLoad;
1108-
11091097
// Generate a buffer_load instruction that may be optimized to s_buffer_load if
11101098
// the offset argument is uniform.
11111099
def int_amdgcn_s_buffer_load : DefaultAttrsIntrinsic <
@@ -1122,25 +1110,12 @@ def int_amdgcn_s_buffer_load : DefaultAttrsIntrinsic <
11221110
[IntrNoMem, ImmArg<ArgIndex<2>>]>,
11231111
AMDGPURsrcIntrinsic<0>;
11241112

1125-
class AMDGPUBufferStore<LLVMType data_ty = llvm_any_ty> : DefaultAttrsIntrinsic <
1126-
[],
1127-
[data_ty, // vdata(VGPR)
1128-
llvm_v4i32_ty, // rsrc(SGPR)
1129-
llvm_i32_ty, // vindex(VGPR)
1130-
llvm_i32_ty, // offset(SGPR/VGPR/imm)
1131-
llvm_i1_ty, // glc(imm)
1132-
llvm_i1_ty], // slc(imm)
1133-
[IntrWriteMem, ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>], "", [SDNPMemOperand]>,
1134-
AMDGPURsrcIntrinsic<1>;
1135-
def int_amdgcn_buffer_store_format : AMDGPUBufferStore<llvm_anyfloat_ty>;
1136-
def int_amdgcn_buffer_store : AMDGPUBufferStore;
1137-
1138-
// New buffer intrinsics with separate raw and struct variants. The raw
1113+
// Buffer intrinsics with separate raw and struct variants. The raw
11391114
// variant never has an index. The struct variant always has an index, even if
11401115
// it is const 0. A struct intrinsic with constant 0 index is different to the
11411116
// corresponding raw intrinsic on gfx9+ because the behavior of bound checking
11421117
// and swizzling changes depending on whether idxen is set in the instruction.
1143-
// These new instrinsics also keep the offset and soffset arguments separate as
1118+
// These instrinsics also keep the offset and soffset arguments separate as
11441119
// they behave differently in bounds checking and swizzling.
11451120

11461121
// The versions of these intrinsics that take <4 x i32> arguments are deprecated
@@ -1521,41 +1496,7 @@ def int_amdgcn_struct_buffer_atomic_fmax : AMDGPUStructBufferAtomic<llvm_anyfloa
15211496
def int_amdgcn_struct_ptr_buffer_atomic_fmin : AMDGPUStructPtrBufferAtomic<llvm_anyfloat_ty>;
15221497
def int_amdgcn_struct_ptr_buffer_atomic_fmax : AMDGPUStructPtrBufferAtomic<llvm_anyfloat_ty>;
15231498

1524-
// Obsolescent tbuffer intrinsics.
1525-
def int_amdgcn_tbuffer_load : DefaultAttrsIntrinsic <
1526-
[llvm_any_ty], // overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32
1527-
[llvm_v4i32_ty, // rsrc(SGPR)
1528-
llvm_i32_ty, // vindex(VGPR)
1529-
llvm_i32_ty, // voffset(VGPR)
1530-
llvm_i32_ty, // soffset(SGPR)
1531-
llvm_i32_ty, // offset(imm)
1532-
llvm_i32_ty, // dfmt(imm)
1533-
llvm_i32_ty, // nfmt(imm)
1534-
llvm_i1_ty, // glc(imm)
1535-
llvm_i1_ty], // slc(imm)
1536-
[IntrReadMem,
1537-
ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>, ImmArg<ArgIndex<6>>,
1538-
ImmArg<ArgIndex<7>>, ImmArg<ArgIndex<8>>], "", [SDNPMemOperand]>,
1539-
AMDGPURsrcIntrinsic<0>;
1540-
1541-
def int_amdgcn_tbuffer_store : DefaultAttrsIntrinsic <
1542-
[],
1543-
[llvm_any_ty, // vdata(VGPR), overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32
1544-
llvm_v4i32_ty, // rsrc(SGPR)
1545-
llvm_i32_ty, // vindex(VGPR)
1546-
llvm_i32_ty, // voffset(VGPR)
1547-
llvm_i32_ty, // soffset(SGPR)
1548-
llvm_i32_ty, // offset(imm)
1549-
llvm_i32_ty, // dfmt(imm)
1550-
llvm_i32_ty, // nfmt(imm)
1551-
llvm_i1_ty, // glc(imm)
1552-
llvm_i1_ty], // slc(imm)
1553-
[IntrWriteMem, ImmArg<ArgIndex<5>>,
1554-
ImmArg<ArgIndex<6>>, ImmArg<ArgIndex<7>>,
1555-
ImmArg<ArgIndex<8>>, ImmArg<ArgIndex<9>>], "", [SDNPMemOperand]>,
1556-
AMDGPURsrcIntrinsic<1>;
1557-
1558-
// New tbuffer intrinsics, with:
1499+
// tbuffer intrinsics, with:
15591500
// - raw and struct variants
15601501
// - joint format field
15611502
// - joint cachepolicy field
@@ -1702,51 +1643,6 @@ def int_amdgcn_struct_tbuffer_store : DefaultAttrsIntrinsic <
17021643
ImmArg<ArgIndex<5>>, ImmArg<ArgIndex<6>>], "", [SDNPMemOperand]>,
17031644
AMDGPURsrcIntrinsic<1>;
17041645

1705-
class AMDGPUBufferAtomic : Intrinsic <
1706-
[llvm_anyint_ty],
1707-
[LLVMMatchType<0>, // vdata(VGPR)
1708-
llvm_v4i32_ty, // rsrc(SGPR)
1709-
llvm_i32_ty, // vindex(VGPR)
1710-
llvm_i32_ty, // offset(SGPR/VGPR/imm)
1711-
llvm_i1_ty], // slc(imm)
1712-
[ImmArg<ArgIndex<4>>, IntrWillReturn, IntrNoCallback, IntrNoFree], "", [SDNPMemOperand]>,
1713-
AMDGPURsrcIntrinsic<1, 0>;
1714-
def int_amdgcn_buffer_atomic_swap : AMDGPUBufferAtomic;
1715-
def int_amdgcn_buffer_atomic_add : AMDGPUBufferAtomic;
1716-
def int_amdgcn_buffer_atomic_sub : AMDGPUBufferAtomic;
1717-
def int_amdgcn_buffer_atomic_smin : AMDGPUBufferAtomic;
1718-
def int_amdgcn_buffer_atomic_umin : AMDGPUBufferAtomic;
1719-
def int_amdgcn_buffer_atomic_smax : AMDGPUBufferAtomic;
1720-
def int_amdgcn_buffer_atomic_umax : AMDGPUBufferAtomic;
1721-
def int_amdgcn_buffer_atomic_and : AMDGPUBufferAtomic;
1722-
def int_amdgcn_buffer_atomic_or : AMDGPUBufferAtomic;
1723-
def int_amdgcn_buffer_atomic_xor : AMDGPUBufferAtomic;
1724-
def int_amdgcn_buffer_atomic_cmpswap : Intrinsic<
1725-
[llvm_i32_ty],
1726-
[llvm_i32_ty, // src(VGPR)
1727-
llvm_i32_ty, // cmp(VGPR)
1728-
llvm_v4i32_ty, // rsrc(SGPR)
1729-
llvm_i32_ty, // vindex(VGPR)
1730-
llvm_i32_ty, // offset(SGPR/VGPR/imm)
1731-
llvm_i1_ty], // slc(imm)
1732-
[ImmArg<ArgIndex<5>>, IntrWillReturn, IntrNoCallback, IntrNoFree], "", [SDNPMemOperand]>,
1733-
AMDGPURsrcIntrinsic<2, 0>;
1734-
1735-
def int_amdgcn_buffer_atomic_csub : AMDGPUBufferAtomic;
1736-
1737-
class AMDGPUBufferAtomicFP : Intrinsic <
1738-
[llvm_anyfloat_ty],
1739-
[LLVMMatchType<0>, // vdata(VGPR)
1740-
llvm_v4i32_ty, // rsrc(SGPR)
1741-
llvm_i32_ty, // vindex(VGPR)
1742-
llvm_i32_ty, // offset(SGPR/VGPR/imm)
1743-
llvm_i1_ty], // slc(imm)
1744-
[ImmArg<ArgIndex<4>>, IntrWillReturn, IntrNoCallback, IntrNoFree], "", [SDNPMemOperand]>,
1745-
AMDGPURsrcIntrinsic<1, 0>;
1746-
1747-
// Legacy form of the intrinsic. raw and struct forms should be preferred.
1748-
def int_amdgcn_buffer_atomic_fadd : AMDGPUBufferAtomicFP;
1749-
17501646
class AMDGPURawBufferLoadLDS : Intrinsic <
17511647
[],
17521648
[llvm_v4i32_ty, // rsrc(SGPR)

‎llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp‎

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -266,63 +266,54 @@ void AMDGPUAtomicOptimizerImpl::visitIntrinsicInst(IntrinsicInst &I) {
266266
switch (I.getIntrinsicID()) {
267267
default:
268268
return;
269-
case Intrinsic::amdgcn_buffer_atomic_add:
270269
case Intrinsic::amdgcn_struct_buffer_atomic_add:
271270
case Intrinsic::amdgcn_struct_ptr_buffer_atomic_add:
272271
case Intrinsic::amdgcn_raw_buffer_atomic_add:
273272
case Intrinsic::amdgcn_raw_ptr_buffer_atomic_add:
274273
Op = AtomicRMWInst::Add;
275274
break;
276-
case Intrinsic::amdgcn_buffer_atomic_sub:
277275
case Intrinsic::amdgcn_struct_buffer_atomic_sub:
278276
case Intrinsic::amdgcn_struct_ptr_buffer_atomic_sub:
279277
case Intrinsic::amdgcn_raw_buffer_atomic_sub:
280278
case Intrinsic::amdgcn_raw_ptr_buffer_atomic_sub:
281279
Op = AtomicRMWInst::Sub;
282280
break;
283-
case Intrinsic::amdgcn_buffer_atomic_and:
284281
case Intrinsic::amdgcn_struct_buffer_atomic_and:
285282
case Intrinsic::amdgcn_struct_ptr_buffer_atomic_and:
286283
case Intrinsic::amdgcn_raw_buffer_atomic_and:
287284
case Intrinsic::amdgcn_raw_ptr_buffer_atomic_and:
288285
Op = AtomicRMWInst::And;
289286
break;
290-
case Intrinsic::amdgcn_buffer_atomic_or:
291287
case Intrinsic::amdgcn_struct_buffer_atomic_or:
292288
case Intrinsic::amdgcn_struct_ptr_buffer_atomic_or:
293289
case Intrinsic::amdgcn_raw_buffer_atomic_or:
294290
case Intrinsic::amdgcn_raw_ptr_buffer_atomic_or:
295291
Op = AtomicRMWInst::Or;
296292
break;
297-
case Intrinsic::amdgcn_buffer_atomic_xor:
298293
case Intrinsic::amdgcn_struct_buffer_atomic_xor:
299294
case Intrinsic::amdgcn_struct_ptr_buffer_atomic_xor:
300295
case Intrinsic::amdgcn_raw_buffer_atomic_xor:
301296
case Intrinsic::amdgcn_raw_ptr_buffer_atomic_xor:
302297
Op = AtomicRMWInst::Xor;
303298
break;
304-
case Intrinsic::amdgcn_buffer_atomic_smin:
305299
case Intrinsic::amdgcn_struct_buffer_atomic_smin:
306300
case Intrinsic::amdgcn_struct_ptr_buffer_atomic_smin:
307301
case Intrinsic::amdgcn_raw_buffer_atomic_smin:
308302
case Intrinsic::amdgcn_raw_ptr_buffer_atomic_smin:
309303
Op = AtomicRMWInst::Min;
310304
break;
311-
case Intrinsic::amdgcn_buffer_atomic_umin:
312305
case Intrinsic::amdgcn_struct_buffer_atomic_umin:
313306
case Intrinsic::amdgcn_struct_ptr_buffer_atomic_umin:
314307
case Intrinsic::amdgcn_raw_buffer_atomic_umin:
315308
case Intrinsic::amdgcn_raw_ptr_buffer_atomic_umin:
316309
Op = AtomicRMWInst::UMin;
317310
break;
318-
case Intrinsic::amdgcn_buffer_atomic_smax:
319311
case Intrinsic::amdgcn_struct_buffer_atomic_smax:
320312
case Intrinsic::amdgcn_struct_ptr_buffer_atomic_smax:
321313
case Intrinsic::amdgcn_raw_buffer_atomic_smax:
322314
case Intrinsic::amdgcn_raw_ptr_buffer_atomic_smax:
323315
Op = AtomicRMWInst::Max;
324316
break;
325-
case Intrinsic::amdgcn_buffer_atomic_umax:
326317
case Intrinsic::amdgcn_struct_buffer_atomic_umax:
327318
case Intrinsic::amdgcn_struct_ptr_buffer_atomic_umax:
328319
case Intrinsic::amdgcn_raw_buffer_atomic_umax:

‎llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp‎

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1220,12 +1220,10 @@ GCNTTIImpl::instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const {
12201220
return IC.replaceInstUsesWith(II, ConstantInt::getFalse(II.getType()));
12211221
break;
12221222
}
1223-
case Intrinsic::amdgcn_buffer_store_format:
12241223
case Intrinsic::amdgcn_raw_buffer_store_format:
12251224
case Intrinsic::amdgcn_struct_buffer_store_format:
12261225
case Intrinsic::amdgcn_raw_tbuffer_store:
12271226
case Intrinsic::amdgcn_struct_tbuffer_store:
1228-
case Intrinsic::amdgcn_tbuffer_store:
12291227
case Intrinsic::amdgcn_image_store_1d:
12301228
case Intrinsic::amdgcn_image_store_1darray:
12311229
case Intrinsic::amdgcn_image_store_2d:
@@ -1438,8 +1436,6 @@ std::optional<Value *> GCNTTIImpl::simplifyDemandedVectorEltsIntrinsic(
14381436
std::function<void(Instruction *, unsigned, APInt, APInt &)>
14391437
SimplifyAndSetOp) const {
14401438
switch (II.getIntrinsicID()) {
1441-
case Intrinsic::amdgcn_buffer_load:
1442-
case Intrinsic::amdgcn_buffer_load_format:
14431439
case Intrinsic::amdgcn_raw_buffer_load:
14441440
case Intrinsic::amdgcn_raw_ptr_buffer_load:
14451441
case Intrinsic::amdgcn_raw_buffer_load_format:
@@ -1453,7 +1449,6 @@ std::optional<Value *> GCNTTIImpl::simplifyDemandedVectorEltsIntrinsic(
14531449
case Intrinsic::amdgcn_struct_ptr_buffer_load_format:
14541450
case Intrinsic::amdgcn_struct_tbuffer_load:
14551451
case Intrinsic::amdgcn_struct_ptr_tbuffer_load:
1456-
case Intrinsic::amdgcn_tbuffer_load:
14571452
return simplifyAMDGCNMemoryIntrinsicDemanded(IC, II, DemandedElts);
14581453
default: {
14591454
if (getAMDGPUImageDMaskIntrinsic(II.getIntrinsicID())) {

‎llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -316,7 +316,6 @@ def : SourceOfDivergence<int_amdgcn_struct_ptr_buffer_atomic_fmin>;
316316
def : SourceOfDivergence<int_amdgcn_struct_ptr_buffer_atomic_fmax>;
317317
def : SourceOfDivergence<int_amdgcn_struct_ptr_buffer_atomic_cmpswap>;
318318
def : SourceOfDivergence<int_amdgcn_struct_ptr_buffer_atomic_cond_sub_u32>;
319-
def : SourceOfDivergence<int_amdgcn_buffer_atomic_csub>;
320319
def : SourceOfDivergence<int_amdgcn_ps_live>;
321320
def : SourceOfDivergence<int_amdgcn_live_mask>;
322321
def : SourceOfDivergence<int_amdgcn_ds_swizzle>;

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