@@ -396,6 +396,8 @@ namespace {
396396 bool PromoteLoad(SDValue Op);
397397
398398 SDValue foldShiftToAvg(SDNode *N);
399+ // Fold `a bitwiseop (~b +/- c)` -> `a bitwiseop ~(b -/+ c)`
400+ SDValue foldBitwiseOpWithNeg(SDNode *N, const SDLoc &DL, EVT VT);
399401
400402 SDValue combineMinNumMaxNum(const SDLoc &DL, EVT VT, SDValue LHS,
401403 SDValue RHS, SDValue True, SDValue False,
@@ -7541,6 +7543,12 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
75417543 return DAG.getNode(ISD::AND, DL, VT, X,
75427544 DAG.getNOT(DL, DAG.getNode(Opc, DL, VT, Y, Z), VT));
75437545
7546+ // Fold (and X, (add (not Y), Z)) -> (and X, (not (sub Y, Z)))
7547+ // Fold (and X, (sub (not Y), Z)) -> (and X, (not (add Y, Z)))
7548+ if (TLI.hasAndNot(SDValue(N, 0)))
7549+ if (SDValue Folded = foldBitwiseOpWithNeg(N, DL, VT))
7550+ return Folded;
7551+
75447552 // Fold (and (srl X, C), 1) -> (srl X, BW-1) for signbit extraction
75457553 // If we are shifting down an extended sign bit, see if we can simplify
75467554 // this to shifting the MSB directly to expose further simplifications.
@@ -11652,6 +11660,22 @@ SDValue DAGCombiner::foldShiftToAvg(SDNode *N) {
1165211660 return DAG.getNode(FloorISD, SDLoc(N), N->getValueType(0), {A, B});
1165311661}
1165411662
11663+ SDValue DAGCombiner::foldBitwiseOpWithNeg(SDNode *N, const SDLoc &DL, EVT VT) {
11664+ unsigned Opc = N->getOpcode();
11665+ SDValue X, Y, Z;
11666+ if (sd_match(
11667+ N, m_BitwiseLogic(m_Value(X), m_Add(m_Not(m_Value(Y)), m_Value(Z)))))
11668+ return DAG.getNode(Opc, DL, VT, X,
11669+ DAG.getNOT(DL, DAG.getNode(ISD::SUB, DL, VT, Y, Z), VT));
11670+
11671+ if (sd_match(N, m_BitwiseLogic(m_Value(X), m_Sub(m_OneUse(m_Not(m_Value(Y))),
11672+ m_Value(Z)))))
11673+ return DAG.getNode(Opc, DL, VT, X,
11674+ DAG.getNOT(DL, DAG.getNode(ISD::ADD, DL, VT, Y, Z), VT));
11675+
11676+ return SDValue();
11677+ }
11678+
1165511679/// Generate Min/Max node
1165611680SDValue DAGCombiner::combineMinNumMaxNum(const SDLoc &DL, EVT VT, SDValue LHS,
1165711681 SDValue RHS, SDValue True,
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