Skip to content

Commit 9318432

Browse files
sgundapabcahoon
sgundapa
authored and
bcahoon
committed
Scalarize the vector inputs to llvm.lround intrinsic by default. (llvm#101054)
Verifier is updated in a different patch to let the vector types for llvm.lround and llvm.llround intrinsics. (cherry picked from commit e78156a) Change-Id: Ib239157be7ce9901923453697c2bbccdcc3bfa4a
1 parent 14584c7 commit 9318432

File tree

9 files changed

+424
-96
lines changed

9 files changed

+424
-96
lines changed

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4767,6 +4767,8 @@ LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
47674767
case G_INTRINSIC_LLRINT:
47684768
case G_INTRINSIC_ROUND:
47694769
case G_INTRINSIC_ROUNDEVEN:
4770+
case G_LROUND:
4771+
case G_LLROUND:
47704772
case G_INTRINSIC_TRUNC:
47714773
case G_FCOS:
47724774
case G_FSIN:

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp‎

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -506,7 +506,7 @@ namespace {
506506
SDValue visitUINT_TO_FP(SDNode *N);
507507
SDValue visitFP_TO_SINT(SDNode *N);
508508
SDValue visitFP_TO_UINT(SDNode *N);
509-
SDValue visitXRINT(SDNode *N);
509+
SDValue visitXROUND(SDNode *N);
510510
SDValue visitFP_ROUND(SDNode *N);
511511
SDValue visitFP_EXTEND(SDNode *N);
512512
SDValue visitFNEG(SDNode *N);
@@ -1925,8 +1925,10 @@ SDValue DAGCombiner::visit(SDNode *N) {
19251925
case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
19261926
case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
19271927
case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1928+
case ISD::LROUND:
1929+
case ISD::LLROUND:
19281930
case ISD::LRINT:
1929-
case ISD::LLRINT: return visitXRINT(N);
1931+
case ISD::LLRINT: return visitXROUND(N);
19301932
case ISD::FP_ROUND: return visitFP_ROUND(N);
19311933
case ISD::FP_EXTEND: return visitFP_EXTEND(N);
19321934
case ISD::FNEG: return visitFNEG(N);
@@ -17856,15 +17858,17 @@ SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
1785617858
return FoldIntToFPToInt(N, DAG);
1785717859
}
1785817860

17859-
SDValue DAGCombiner::visitXRINT(SDNode *N) {
17861+
SDValue DAGCombiner::visitXROUND(SDNode *N) {
1786017862
SDValue N0 = N->getOperand(0);
1786117863
EVT VT = N->getValueType(0);
1786217864

1786317865
// fold (lrint|llrint undef) -> undef
17866+
// fold (lround|llround undef) -> undef
1786417867
if (N0.isUndef())
1786517868
return DAG.getUNDEF(VT);
1786617869

1786717870
// fold (lrint|llrint c1fp) -> c1
17871+
// fold (lround|llround c1fp) -> c1
1786817872
if (DAG.isConstantFPBuildVectorOrConstantFP(N0))
1786917873
return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N0);
1787017874

‎llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2409,6 +2409,8 @@ bool DAGTypeLegalizer::PromoteFloatOperand(SDNode *N, unsigned OpNo) {
24092409
case ISD::FCOPYSIGN: R = PromoteFloatOp_FCOPYSIGN(N, OpNo); break;
24102410
case ISD::FP_TO_SINT:
24112411
case ISD::FP_TO_UINT:
2412+
case ISD::LROUND:
2413+
case ISD::LLROUND:
24122414
case ISD::LRINT:
24132415
case ISD::LLRINT: R = PromoteFloatOp_UnaryOp(N, OpNo); break;
24142416
case ISD::FP_TO_SINT_SAT:

‎llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1046,7 +1046,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
10461046
SDValue WidenVecRes_Convert(SDNode *N);
10471047
SDValue WidenVecRes_Convert_StrictFP(SDNode *N);
10481048
SDValue WidenVecRes_FP_TO_XINT_SAT(SDNode *N);
1049-
SDValue WidenVecRes_XRINT(SDNode *N);
1049+
SDValue WidenVecRes_XROUND(SDNode *N);
10501050
SDValue WidenVecRes_FCOPYSIGN(SDNode *N);
10511051
SDValue WidenVecRes_UnarySameEltsWithScalarArg(SDNode *N);
10521052
SDValue WidenVecRes_ExpOp(SDNode *N);

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -473,6 +473,8 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
473473
Node->getValueType(0), Scale);
474474
break;
475475
}
476+
case ISD::LROUND:
477+
case ISD::LLROUND:
476478
case ISD::LRINT:
477479
case ISD::LLRINT:
478480
case ISD::SINT_TO_FP:

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp‎

Lines changed: 14 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -110,6 +110,8 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
110110
case ISD::LLRINT:
111111
case ISD::FROUND:
112112
case ISD::FROUNDEVEN:
113+
case ISD::LROUND:
114+
case ISD::LLROUND:
113115
case ISD::FSIN:
114116
case ISD::FSINH:
115117
case ISD::FSQRT:
@@ -750,6 +752,8 @@ bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
750752
case ISD::FP_TO_UINT:
751753
case ISD::SINT_TO_FP:
752754
case ISD::UINT_TO_FP:
755+
case ISD::LROUND:
756+
case ISD::LLROUND:
753757
case ISD::LRINT:
754758
case ISD::LLRINT:
755759
Res = ScalarizeVecOp_UnaryOp(N);
@@ -1197,6 +1201,8 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
11971201
case ISD::VP_FROUND:
11981202
case ISD::FROUNDEVEN:
11991203
case ISD::VP_FROUNDEVEN:
1204+
case ISD::LROUND:
1205+
case ISD::LLROUND:
12001206
case ISD::FSIN:
12011207
case ISD::FSINH:
12021208
case ISD::FSQRT: case ISD::VP_SQRT:
@@ -3197,6 +3203,8 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
31973203
case ISD::ZERO_EXTEND:
31983204
case ISD::ANY_EXTEND:
31993205
case ISD::FTRUNC:
3206+
case ISD::LROUND:
3207+
case ISD::LLROUND:
32003208
case ISD::LRINT:
32013209
case ISD::LLRINT:
32023210
Res = SplitVecOp_UnaryOp(N);
@@ -4519,7 +4527,9 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
45194527
case ISD::LLRINT:
45204528
case ISD::VP_LRINT:
45214529
case ISD::VP_LLRINT:
4522-
Res = WidenVecRes_XRINT(N);
4530+
case ISD::LROUND:
4531+
case ISD::LLROUND:
4532+
Res = WidenVecRes_XROUND(N);
45234533
break;
45244534

45254535
case ISD::FABS:
@@ -5136,7 +5146,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_FP_TO_XINT_SAT(SDNode *N) {
51365146
return DAG.getNode(N->getOpcode(), dl, WidenVT, Src, N->getOperand(1));
51375147
}
51385148

5139-
SDValue DAGTypeLegalizer::WidenVecRes_XRINT(SDNode *N) {
5149+
SDValue DAGTypeLegalizer::WidenVecRes_XROUND(SDNode *N) {
51405150
SDLoc dl(N);
51415151
EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
51425152
ElementCount WidenNumElts = WidenVT.getVectorElementCount();
@@ -6385,6 +6395,8 @@ bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
63856395
case ISD::VSELECT: Res = WidenVecOp_VSELECT(N); break;
63866396
case ISD::FLDEXP:
63876397
case ISD::FCOPYSIGN:
6398+
case ISD::LROUND:
6399+
case ISD::LLROUND:
63886400
case ISD::LRINT:
63896401
case ISD::LLRINT:
63906402
Res = WidenVecOp_UnrollVectorOp(N);

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5420,6 +5420,8 @@ bool SelectionDAG::isKnownNeverNaN(SDValue Op, bool SNaN, unsigned Depth) const
54205420
case ISD::FCEIL:
54215421
case ISD::FROUND:
54225422
case ISD::FROUNDEVEN:
5423+
case ISD::LROUND:
5424+
case ISD::LLROUND:
54235425
case ISD::FRINT:
54245426
case ISD::LRINT:
54255427
case ISD::LLRINT:

‎llvm/lib/CodeGen/TargetLoweringBase.cpp‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -768,8 +768,9 @@ void TargetLoweringBase::initActions() {
768768
setOperationAction(
769769
{ISD::FCOPYSIGN, ISD::SIGN_EXTEND_INREG, ISD::ANY_EXTEND_VECTOR_INREG,
770770
ISD::SIGN_EXTEND_VECTOR_INREG, ISD::ZERO_EXTEND_VECTOR_INREG,
771-
ISD::SPLAT_VECTOR, ISD::LRINT, ISD::LLRINT, ISD::FTAN, ISD::FACOS,
772-
ISD::FASIN, ISD::FATAN, ISD::FCOSH, ISD::FSINH, ISD::FTANH},
771+
ISD::SPLAT_VECTOR, ISD::LRINT, ISD::LLRINT, ISD::LROUND,
772+
ISD::LLROUND, ISD::FTAN, ISD::FACOS, ISD::FASIN, ISD::FATAN,
773+
ISD::FCOSH, ISD::FSINH, ISD::FTANH},
773774
VT, Expand);
774775

775776
// Constrained floating-point operations default to expand.

0 commit comments

Comments
 (0)