Merge commit '9d37e61fc77d' into amd-staging

Author: ronlieb

llvm/include/llvm/Analysis/TargetTransformInfo.h

@@ -1771,6 +1771,10 @@ class TargetTransformInfo {
   /// scalable version of the vectorized loop.
   bool preferFixedOverScalableIfEqualCost() const;
 
+  /// \returns True if target prefers SLP vectorizer with altermate opcode
+  /// vectorization, false - otherwise.
+  bool preferAlternateOpcodeVectorization() const;
+
   /// \returns True if the target prefers reductions in loop.
   bool preferInLoopReduction(unsigned Opcode, Type *Ty) const;
 
@@ -2325,6 +2329,7 @@ class TargetTransformInfo::Concept {
   virtual bool preferInLoopReduction(unsigned Opcode, Type *Ty) const = 0;
   virtual bool preferPredicatedReductionSelect(unsigned Opcode,
                                                Type *Ty) const = 0;
+  virtual bool preferAlternateOpcodeVectorization() const = 0;
   virtual bool preferEpilogueVectorization() const = 0;
 
   virtual bool shouldExpandReduction(const IntrinsicInst *II) const = 0;
@@ -3135,6 +3140,9 @@ class TargetTransformInfo::Model final : public TargetTransformInfo::Concept {
   bool preferInLoopReduction(unsigned Opcode, Type *Ty) const override {
     return Impl.preferInLoopReduction(Opcode, Ty);
   }
+  bool preferAlternateOpcodeVectorization() const override {
+    return Impl.preferAlternateOpcodeVectorization();
+  }
   bool preferPredicatedReductionSelect(unsigned Opcode,
                                        Type *Ty) const override {
     return Impl.preferPredicatedReductionSelect(Opcode, Ty);

llvm/include/llvm/Analysis/TargetTransformInfoImpl.h

@@ -1007,6 +1007,7 @@ class TargetTransformInfoImplBase {
   bool preferFixedOverScalableIfEqualCost() const { return false; }
 
   bool preferInLoopReduction(unsigned Opcode, Type *Ty) const { return false; }
+  bool preferAlternateOpcodeVectorization() const { return true; }
 
   bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty) const {
     return false;

llvm/lib/Analysis/TargetTransformInfo.cpp

@@ -1384,6 +1384,10 @@ bool TargetTransformInfo::preferInLoopReduction(unsigned Opcode,
   return TTIImpl->preferInLoopReduction(Opcode, Ty);
 }
 
+bool TargetTransformInfo::preferAlternateOpcodeVectorization() const {
+  return TTIImpl->preferAlternateOpcodeVectorization();
+}
+
 bool TargetTransformInfo::preferPredicatedReductionSelect(unsigned Opcode,
                                                           Type *Ty) const {
   return TTIImpl->preferPredicatedReductionSelect(Opcode, Ty);

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h

@@ -125,6 +125,8 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
 
   unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const;
 
+  bool preferAlternateOpcodeVectorization() const { return false; }
+
   bool preferEpilogueVectorization() const {
     // Epilogue vectorization is usually unprofitable - tail folding or
     // a smaller VF would have been better.  This a blunt hammer - we

llvm/lib/Target/X86/X86TargetTransformInfo.h

@@ -292,6 +292,7 @@ class X86TTIImpl : public BasicTTIImplBase<X86TTIImpl> {
 
   TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize,
                                                     bool IsZeroCmp) const;
+  bool preferAlternateOpcodeVectorization() const { return false; }
   bool prefersVectorizedAddressing() const;
   bool supportsEfficientVectorElementLoadStore() const;
   bool enableInterleavedAccessVectorization();