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Relanding the patch upstream patch commit bdb6320 in amd-staging.
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3 files changed

+48
-38
lines changed

3 files changed

+48
-38
lines changed

‎llvm/lib/Target/AMDGPU/SIFrameLowering.cpp

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2142,6 +2142,16 @@ bool SIFrameLowering::requiresStackPointerReference(
21422142
return frameTriviallyRequiresSP(MFI);
21432143
}
21442144

2145+
static bool isLiveIntoMBB(MCRegister Reg, MachineBasicBlock &MBB,
2146+
const TargetRegisterInfo *TRI) {
2147+
for (MCRegAliasIterator R(Reg, TRI, true); R.isValid(); ++R) {
2148+
if (MBB.isLiveIn(*R)) {
2149+
return true;
2150+
}
2151+
}
2152+
return false;
2153+
}
2154+
21452155
bool SIFrameLowering::spillCalleeSavedRegisters(
21462156
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
21472157
const ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
@@ -2161,12 +2171,11 @@ bool SIFrameLowering::spillCalleeSavedRegisters(
21612171
} else {
21622172
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(
21632173
Reg, Reg == RI->getReturnAddressReg(MF) ? MVT::i64 : MVT::i32);
2164-
const MachineRegisterInfo &MRI = MF.getRegInfo();
21652174
// If this value was already livein, we probably have a direct use of the
21662175
// incoming register value, so don't kill at the spill point. This happens
21672176
// since we pass some special inputs (workgroup IDs) in the callee saved
21682177
// range.
2169-
const bool IsLiveIn = MRI.isLiveIn(Reg);
2178+
const bool IsLiveIn = isLiveIntoMBB(Reg, MBB, TRI);
21702179
TII->storeRegToStackSlotCFI(MBB, MBBI, Reg, !IsLiveIn, CS.getFrameIdx(),
21712180
RC, TRI);
21722181
}

‎llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir

Lines changed: 21 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1,25 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=si-lower-sgpr-spills %s -o /dev/null 2>&1 | FileCheck -check-prefix=VERIFIER %s
2+
# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck %s
33

4-
# FIXME : Currently, MRI's liveIn check for registers does not take the corresponding live-in's sub-registers into account. As a result
5-
# in SILowerSGPRSpills, the SubReg spill gets marked KILLED even though its SuperReg is in the function Live-ins. This causes machine
6-
# verifier to now fail at direct usage of that SubReg, which intially should not be any problem before adding spill.
7-
8-
# VERIFIER: After SI lower SGPR spill instructions
9-
10-
# VERIFIER: *** Bad machine code: Using an undefined physical register ***
11-
# VERIFIER: - instruction: S_NOP 0, implicit $sgpr50
12-
# VERIFIER-NEXT: - operand 1: implicit $sgpr50
13-
14-
# VERIFIER: *** Bad machine code: Using an undefined physical register ***
15-
# VERIFIER: - instruction: S_NOP 0, implicit $sgpr52
16-
# VERIFIER-NEXT: - operand 1: implicit $sgpr52
17-
18-
# VERIFIER: *** Bad machine code: Using an undefined physical register ***
19-
# VERIFIER: - instruction: S_NOP 0, implicit $sgpr55
20-
# VERIFIER-NEXT: - operand 1: implicit $sgpr55
21-
22-
# VERIFIER: LLVM ERROR: Found 3 machine code errors.
234
---
245
name: spill_partial_live_csr_sgpr_test
256
tracksRegLiveness: true
@@ -31,6 +12,26 @@ body: |
3112
bb.0:
3213
liveins: $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55
3314
15+
; CHECK-LABEL: name: spill_partial_live_csr_sgpr_test
16+
; CHECK: liveins: $sgpr50, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $vgpr63, $sgpr50_sgpr51, $sgpr52_sgpr53, $sgpr54_sgpr55
17+
; CHECK-NEXT: {{ $}}
18+
; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr50, 0, $vgpr63
19+
; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr50, $vgpr63, 0, 32
20+
; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr52, 1, $vgpr63
21+
; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr52, $vgpr63, 1, 32
22+
; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr53, 2, $vgpr63
23+
; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr53, $vgpr63, 2, 32
24+
; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr54, 3, $vgpr63
25+
; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr54, $vgpr63, 3, 32
26+
; CHECK-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr55, 4, $vgpr63
27+
; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr55, $vgpr63, 4, 32
28+
; CHECK-NEXT: S_NOP 0, implicit $sgpr50
29+
; CHECK-NEXT: $sgpr50 = S_MOV_B32 0
30+
; CHECK-NEXT: S_NOP 0, implicit $sgpr52
31+
; CHECK-NEXT: $sgpr52_sgpr53 = S_MOV_B64 0
32+
; CHECK-NEXT: S_NOP 0, implicit $sgpr55
33+
; CHECK-NEXT: $sgpr54_sgpr55 = S_MOV_B64 0
34+
; CHECK-NEXT: $sgpr56 = S_MOV_B32 0
3435
S_NOP 0, implicit $sgpr50
3536
$sgpr50 = S_MOV_B32 0
3637
S_NOP 0, implicit $sgpr52

‎llvm/test/CodeGen/AMDGPU/spill-sgpr-to-virtual-vgpr.mir

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -55,37 +55,37 @@ body: |
5555
; GCN-LABEL: name: sgpr_spill_lane_crossover
5656
; GCN: liveins: $sgpr10, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $vgpr63, $sgpr30_sgpr31, $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71, $sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79, $sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87, $sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95
5757
; GCN-NEXT: {{ $}}
58-
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr64, 0, $vgpr63
58+
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr64, 0, $vgpr63
5959
; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr64, $vgpr63, 0, 32
60-
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr65, 1, $vgpr63
60+
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr65, 1, $vgpr63
6161
; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr65, $vgpr63, 1, 32
62-
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr66, 2, $vgpr63
62+
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr66, 2, $vgpr63
6363
; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr66, $vgpr63, 2, 32
64-
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr67, 3, $vgpr63
64+
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr67, 3, $vgpr63
6565
; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr67, $vgpr63, 3, 32
66-
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr68, 4, $vgpr63
66+
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr68, 4, $vgpr63
6767
; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr68, $vgpr63, 4, 32
68-
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr69, 5, $vgpr63
68+
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr69, 5, $vgpr63
6969
; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr69, $vgpr63, 5, 32
70-
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr70, 6, $vgpr63
70+
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr70, 6, $vgpr63
7171
; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr70, $vgpr63, 6, 32
72-
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr71, 7, $vgpr63
72+
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr71, 7, $vgpr63
7373
; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr71, $vgpr63, 7, 32
74-
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr80, 8, $vgpr63
74+
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr80, 8, $vgpr63
7575
; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr80, $vgpr63, 8, 32
76-
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr81, 9, $vgpr63
76+
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr81, 9, $vgpr63
7777
; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr81, $vgpr63, 9, 32
78-
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr82, 10, $vgpr63
78+
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr82, 10, $vgpr63
7979
; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr82, $vgpr63, 10, 32
80-
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr83, 11, $vgpr63
80+
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr83, 11, $vgpr63
8181
; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr83, $vgpr63, 11, 32
82-
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr84, 12, $vgpr63
82+
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr84, 12, $vgpr63
8383
; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr84, $vgpr63, 12, 32
84-
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr85, 13, $vgpr63
84+
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr85, 13, $vgpr63
8585
; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr85, $vgpr63, 13, 32
86-
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr86, 14, $vgpr63
86+
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr86, 14, $vgpr63
8787
; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr86, $vgpr63, 14, 32
88-
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR killed $sgpr87, 15, $vgpr63
88+
; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr87, 15, $vgpr63
8989
; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr87, $vgpr63, 15, 32
9090
; GCN-NEXT: S_NOP 0
9191
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF

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