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[RISCV] Add Andes XAndesVPackFPH (Andes Vector Packed FP16) extension. (llvm#138827)
The spec can be found at: https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release. This patch only supports assembler. Intrinsics support will be added in a later patch.
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‎clang/test/Driver/print-supported-extensions-riscv.c

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@@ -157,6 +157,7 @@
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// CHECK-NEXT: svpbmt 1.0 'Svpbmt' (Page-Based Memory Types)
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// CHECK-NEXT: svvptc 1.0 'Svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid)
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// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
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// CHECK-NEXT: xandesvpackfph 5.0 'XAndesVPackFPH' (Andes Vector Packed FP16 Extension)
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// CHECK-NEXT: xcvalu 1.0 'XCValu' (CORE-V ALU Operations)
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// CHECK-NEXT: xcvbi 1.0 'XCVbi' (CORE-V Immediate Branching)
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// CHECK-NEXT: xcvbitmanip 1.0 'XCVbitmanip' (CORE-V Bit Manipulation)

‎llvm/docs/RISCVUsage.rst

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@@ -508,6 +508,9 @@ The current vendor extensions supported are:
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``XAndesPerf``
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LLVM implements `version 5.0.0 of the Andes Performance Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification.
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``XAndesVPackFPH``
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LLVM implements `version 5.0.0 of the Andes Vector Packed FP16 Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification.
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Experimental C Intrinsics
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=========================
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‎llvm/docs/ReleaseNotes.md

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@@ -185,6 +185,7 @@ Changes to the RISC-V Backend
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interrupt handlers without using inline assembly.
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* Adds assembler support for the Andes `XAndesperf` (Andes Performance extension).
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* `-mcpu=sifive-p870` was added.
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* Adds assembler support for the Andes `XAndesvpackfph` (Andes Vector Packed FP16 extension).
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Changes to the WebAssembly Backend
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----------------------------------

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

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@@ -727,7 +727,8 @@ static constexpr FeatureBitset XTHeadGroup = {
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RISCV::FeatureVendorXTHeadMemPair, RISCV::FeatureVendorXTHeadSync,
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RISCV::FeatureVendorXTHeadVdot};
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static constexpr FeatureBitset XAndesGroup = {RISCV::FeatureVendorXAndesPerf};
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static constexpr FeatureBitset XAndesGroup = {
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RISCV::FeatureVendorXAndesPerf, RISCV::FeatureVendorXAndesVPackFPH};
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static constexpr DecoderListEntry DecoderList32[]{
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// Vendor Extensions

‎llvm/lib/Target/RISCV/RISCVFeatures.td

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@@ -1517,6 +1517,14 @@ def HasVendorXAndesPerf
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AssemblerPredicate<(all_of FeatureVendorXAndesPerf),
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"'XAndesPerf' (Andes Performance Extension)">;
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def FeatureVendorXAndesVPackFPH
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: RISCVExtension<5, 0, "Andes Vector Packed FP16 Extension",
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[FeatureStdExtZvfhmin]>;
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def HasVendorXAndesVPackFPH
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: Predicate<"Subtarget->hasVendorXAndesVPackFPH()">,
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AssemblerPredicate<(all_of FeatureVendorXAndesVPackFPH),
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"'XAndesVPackFPH' (Andes Vector Packed FP16 Extension)">;
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//===----------------------------------------------------------------------===//
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// LLVM specific features and extensions
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//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td

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@@ -315,6 +315,29 @@ class NDSRVInstSDGP<bits<3> funct3, string opcodestr>
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let mayStore = 1;
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}
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class NDSRVInstVFPMAD<bits<6> funct6, string opcodestr>
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: RVInst<(outs VR:$vd), (ins VR:$vs2, FPR32:$rs1, VMaskOp:$vm),
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opcodestr # "." # "vf", "$vd, $rs1, $vs2$vm", [], InstFormatR>,
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SchedBinaryMC<"WriteVFMulAddF", "ReadVFMulAddV", "ReadVFMulAddF"> {
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bits<5> vs2;
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bits<5> rs1;
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bits<5> vd;
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bit vm;
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let Inst{31-26} = funct6;
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let Inst{25} = vm;
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let Inst{24-20} = vs2;
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let Inst{19-15} = rs1;
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let Inst{14-12} = 0b100;
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let Inst{11-7} = vd;
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let Inst{6-0} = OPC_CUSTOM_2.Value;
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let hasSideEffects = 0;
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let mayLoad = 0;
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let mayStore = 0;
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let RVVConstraint = VMConstraint;
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}
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//===----------------------------------------------------------------------===//
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// XAndesPerf
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//===----------------------------------------------------------------------===//
@@ -365,6 +388,16 @@ def NDS_LDGP : NDSRVInstLDGP<0b011, "nds.ldgp">;
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def NDS_SDGP : NDSRVInstSDGP<0b111, "nds.sdgp">;
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} // Predicates = [HasVendorXAndesPerf, IsRV64]
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//===----------------------------------------------------------------------===//
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// XAndesVPackFPH
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//===----------------------------------------------------------------------===//
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let Predicates = [HasVendorXAndesVPackFPH],
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Uses = [FRM, VL, VTYPE], mayRaiseFPException = true in {
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def NDS_VFPMADT_VF : NDSRVInstVFPMAD<0b000010, "nds.vfpmadt">;
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def NDS_VFPMADB_VF : NDSRVInstVFPMAD<0b000011, "nds.vfpmadb">;
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}
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} // DecoderNamespace = "XAndes"
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// Patterns

‎llvm/test/CodeGen/RISCV/attributes.ll

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@@ -104,6 +104,7 @@
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisync %s -o - | FileCheck --check-prefix=RV32XQCISYNC %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisls %s -o - | FileCheck --check-prefix=RV32XQCISLS %s
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; RUN: llc -mtriple=riscv32 -mattr=+xandesperf %s -o - | FileCheck --check-prefix=RV32XANDESPERF %s
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; RUN: llc -mtriple=riscv32 -mattr=+xandesvpackfph %s -o - | FileCheck --check-prefix=RV32XANDESVPACKFPH %s
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; RUN: llc -mtriple=riscv32 -mattr=+zaamo %s -o - | FileCheck --check-prefix=RV32ZAAMO %s
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; RUN: llc -mtriple=riscv32 -mattr=+zalrsc %s -o - | FileCheck --check-prefix=RV32ZALRSC %s
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; RUN: llc -mtriple=riscv32 -mattr=+zca %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCA %s
@@ -254,6 +255,7 @@
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; RUN: llc -mtriple=riscv64 -mattr=+xtheadsync %s -o - | FileCheck --check-prefix=RV64XTHEADSYNC %s
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; RUN: llc -mtriple=riscv64 -mattr=+xtheadvdot %s -o - | FileCheck --check-prefixes=CHECK,RV64XTHEADVDOT %s
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; RUN: llc -mtriple=riscv64 -mattr=+xandesperf %s -o - | FileCheck --check-prefix=RV64XANDESPERF %s
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; RUN: llc -mtriple=riscv64 -mattr=+xandesvpackfph %s -o - | FileCheck --check-prefix=RV64XANDESVPACKFPH %s
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; RUN: llc -mtriple=riscv64 -mattr=+za64rs %s -o - | FileCheck --check-prefixes=CHECK,RV64ZA64RS %s
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; RUN: llc -mtriple=riscv64 -mattr=+za128rs %s -o - | FileCheck --check-prefixes=CHECK,RV64ZA128RS %s
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; RUN: llc -mtriple=riscv64 -mattr=+zama16b %s -o - | FileCheck --check-prefixes=CHECK,RV64ZAMA16B %s
@@ -447,6 +449,7 @@
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; RV32XQCISYNC: attribute 5, "rv32i2p1_zca1p0_xqcisync0p2"
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; RV32XQCISLS: .attribute 5, "rv32i2p1_xqcisls0p2"
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; RV32XANDESPERF: .attribute 5, "rv32i2p1_xandesperf5p0"
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; RV32XANDESVPACKFPH: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfhmin1p0_zvl32b1p0_xandesvpackfph5p0"
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; RV32ZAAMO: .attribute 5, "rv32i2p1_zaamo1p0"
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; RV32ZALRSC: .attribute 5, "rv32i2p1_zalrsc1p0"
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; RV32ZCA: .attribute 5, "rv32i2p1_zca1p0"
@@ -598,6 +601,7 @@
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; RV64XTHEADSYNC: .attribute 5, "rv64i2p1_xtheadsync1p0"
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; RV64XTHEADVDOT: .attribute 5, "rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0"
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; RV64XANDESPERF: .attribute 5, "rv64i2p1_xandesperf5p0"
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; RV64XANDESVPACKFPH: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfhmin1p0_zvl32b1p0_xandesvpackfph5p0"
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; RV64ZTSO: .attribute 5, "rv64i2p1_ztso1p0"
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; RV64ZAAMO: .attribute 5, "rv64i2p1_zaamo1p0"
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; RV64ZALRSC: .attribute 5, "rv64i2p1_zalrsc1p0"

‎llvm/test/CodeGen/RISCV/features-info.ll

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; CHECK-NEXT: ventana-veyron - Ventana Veyron-Series processors.
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; CHECK-NEXT: vxrm-pipeline-flush - VXRM writes causes pipeline flush.
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; CHECK-NEXT: xandesperf - 'XAndesPerf' (Andes Performance Extension).
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; CHECK-NEXT: xandesvpackfph - 'XAndesVPackFPH' (Andes Vector Packed FP16 Extension).
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; CHECK-NEXT: xcvalu - 'XCValu' (CORE-V ALU Operations).
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; CHECK-NEXT: xcvbi - 'XCVbi' (CORE-V Immediate Branching).
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; CHECK-NEXT: xcvbitmanip - 'XCVbitmanip' (CORE-V Bit Manipulation).

‎llvm/test/MC/RISCV/xandesvpackfph-valid.s

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# XAndesVPackFPH - Andes Vector Packed FP16 Extension
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# RUN: llvm-mc %s -triple=riscv32 -mattr=+xandesvpackfph -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ASM %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xandesvpackfph < %s \
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# RUN: | llvm-objdump --mattr=+xandesvpackfph -M no-aliases -d -r - \
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# RUN: | FileCheck -check-prefixes=CHECK-OBJ %s
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# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
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# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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# RUN: llvm-mc %s -triple=riscv64 -mattr=+xandesvpackfph -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ASM %s
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# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xandesvpackfph < %s \
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# RUN: | llvm-objdump --mattr=+xandesvpackfph -M no-aliases -d -r - \
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# RUN: | FileCheck -check-prefixes=CHECK-OBJ %s
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# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
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# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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# CHECK-OBJ: nds.vfpmadt.vf v8, fa0, v10
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# CHECK-ASM: nds.vfpmadt.vf v8, fa0, v10
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# CHECK-ASM: encoding: [0x5b,0x44,0xa5,0x0a]
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# CHECK-ERROR: instruction requires the following: 'XAndesVPackFPH' (Andes Vector Packed FP16 Extension){{$}}
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nds.vfpmadt.vf v8, fa0, v10
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# CHECK-OBJ: nds.vfpmadt.vf v8, fa0, v10, v0.t
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# CHECK-ASM: nds.vfpmadt.vf v8, fa0, v10, v0.t
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# CHECK-ASM: encoding: [0x5b,0x44,0xa5,0x08]
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# CHECK-ERROR: instruction requires the following: 'XAndesVPackFPH' (Andes Vector Packed FP16 Extension){{$}}
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nds.vfpmadt.vf v8, fa0, v10, v0.t
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# CHECK-OBJ: nds.vfpmadb.vf v8, fa0, v10
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# CHECK-ASM: nds.vfpmadb.vf v8, fa0, v10
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# CHECK-ASM: encoding: [0x5b,0x44,0xa5,0x0e]
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# CHECK-ERROR: instruction requires the following: 'XAndesVPackFPH' (Andes Vector Packed FP16 Extension){{$}}
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nds.vfpmadb.vf v8, fa0, v10
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# CHECK-OBJ: nds.vfpmadb.vf v8, fa0, v10, v0.t
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# CHECK-ASM: nds.vfpmadb.vf v8, fa0, v10, v0.t
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# CHECK-ASM: encoding: [0x5b,0x44,0xa5,0x0c]
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# CHECK-ERROR: instruction requires the following: 'XAndesVPackFPH' (Andes Vector Packed FP16 Extension){{$}}
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nds.vfpmadb.vf v8, fa0, v10, v0.t

‎llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

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@@ -1128,6 +1128,7 @@ R"(All available -march extensions for RISC-V
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svpbmt 1.0
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svvptc 1.0
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xandesperf 5.0
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xandesvpackfph 5.0
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xcvalu 1.0
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xcvbi 1.0
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xcvbitmanip 1.0

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