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[Mips] Use MCRegister. NFC
Use id() to get rid of some implicit conversions.
1 parent ecb7f5a commit 9e8cd73

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11 files changed

+276
-277
lines changed

11 files changed

+276
-277
lines changed

‎llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp‎

Lines changed: 201 additions & 205 deletions
Large diffs are not rendered by default.

‎llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -147,7 +147,7 @@ inline static MCRegister getMSARegFromFReg(MCRegister Reg) {
147147
else if (Reg >= Mips::D0_64 && Reg <= Mips::D31_64)
148148
return Reg - Mips::D0_64 + Mips::W0;
149149
else
150-
return Mips::NoRegister;
150+
return MCRegister();
151151
}
152152
}
153153

‎llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -46,7 +46,7 @@ void MipsELFStreamer::emitInstruction(const MCInst &Inst,
4646
if (!Op.isReg())
4747
continue;
4848

49-
unsigned Reg = Op.getReg();
49+
MCRegister Reg = Op.getReg();
5050
RegInfoRecord->SetPhysRegUsed(Reg, MCRegInfo);
5151
}
5252

‎llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -91,8 +91,8 @@ static void LowerLargeShift(MCInst& Inst) {
9191
void MipsMCCodeEmitter::LowerCompactBranch(MCInst& Inst) const {
9292
// Encoding may be illegal !(rs < rt), but this situation is
9393
// easily fixed.
94-
unsigned RegOp0 = Inst.getOperand(0).getReg();
95-
unsigned RegOp1 = Inst.getOperand(1).getReg();
94+
MCRegister RegOp0 = Inst.getOperand(0).getReg();
95+
MCRegister RegOp1 = Inst.getOperand(1).getReg();
9696

9797
unsigned Reg0 = Ctx.getRegisterInfo()->getEncodingValue(RegOp0);
9898
unsigned Reg1 = Ctx.getRegisterInfo()->getEncodingValue(RegOp1);
@@ -724,7 +724,7 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
724724
SmallVectorImpl<MCFixup> &Fixups,
725725
const MCSubtargetInfo &STI) const {
726726
if (MO.isReg()) {
727-
unsigned Reg = MO.getReg();
727+
MCRegister Reg = MO.getReg();
728728
unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
729729
return RegNo;
730730
} else if (MO.isImm()) {
@@ -1033,7 +1033,7 @@ MipsMCCodeEmitter::getRegisterListOpValue(const MCInst &MI, unsigned OpNo,
10331033
// placed before memory operand (register + imm).
10341034

10351035
for (unsigned I = OpNo, E = MI.getNumOperands() - 2; I < E; ++I) {
1036-
unsigned Reg = MI.getOperand(I).getReg();
1036+
MCRegister Reg = MI.getOperand(I).getReg();
10371037
unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
10381038
if (RegNo != 31)
10391039
res++;
@@ -1093,7 +1093,7 @@ MipsMCCodeEmitter::getMovePRegSingleOpValue(const MCInst &MI, unsigned OpNo,
10931093

10941094
MCOperand Op = MI.getOperand(OpNo);
10951095
assert(Op.isReg() && "Operand of movep is not a register!");
1096-
switch (Op.getReg()) {
1096+
switch (Op.getReg().id()) {
10971097
default:
10981098
llvm_unreachable("Unknown register for movep!");
10991099
case Mips::ZERO: return 0;

‎llvm/lib/Target/Mips/MCTargetDesc/MipsMCNaCl.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ static const Align MIPS_NACL_BUNDLE_ALIGN = Align(16);
1919

2020
bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
2121
bool *IsStore = nullptr);
22-
bool baseRegNeedsLoadStoreMask(unsigned Reg);
22+
bool baseRegNeedsLoadStoreMask(MCRegister Reg);
2323

2424
// This function creates an MCELFStreamer for Mips NaCl.
2525
MCELFStreamer *

‎llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -97,7 +97,7 @@ class MipsNaClELFStreamer : public MipsELFStreamer {
9797
}
9898
}
9999

100-
void emitMask(unsigned AddrReg, unsigned MaskReg,
100+
void emitMask(MCRegister AddrReg, unsigned MaskReg,
101101
const MCSubtargetInfo &STI) {
102102
MCInst MaskInst;
103103
MaskInst.setOpcode(Mips::AND);
@@ -110,7 +110,7 @@ class MipsNaClELFStreamer : public MipsELFStreamer {
110110
// Sandbox indirect branch or return instruction by inserting mask operation
111111
// before it.
112112
void sandboxIndirectJump(const MCInst &MI, const MCSubtargetInfo &STI) {
113-
unsigned AddrReg = MI.getOperand(0).getReg();
113+
MCRegister AddrReg = MI.getOperand(0).getReg();
114114

115115
emitBundleLock(false);
116116
emitMask(AddrReg, IndirectBranchMaskReg, STI);
@@ -126,13 +126,13 @@ class MipsNaClELFStreamer : public MipsELFStreamer {
126126
emitBundleLock(false);
127127
if (MaskBefore) {
128128
// Sandbox memory access.
129-
unsigned BaseReg = MI.getOperand(AddrIdx).getReg();
129+
MCRegister BaseReg = MI.getOperand(AddrIdx).getReg();
130130
emitMask(BaseReg, LoadStoreStackMaskReg, STI);
131131
}
132132
MipsELFStreamer::emitInstruction(MI, STI);
133133
if (MaskAfter) {
134134
// Sandbox SP change.
135-
unsigned SPReg = MI.getOperand(0).getReg();
135+
MCRegister SPReg = MI.getOperand(0).getReg();
136136
assert((Mips::SP == SPReg) && "Unexpected stack-pointer register.");
137137
emitMask(SPReg, LoadStoreStackMaskReg, STI);
138138
}
@@ -182,7 +182,7 @@ class MipsNaClELFStreamer : public MipsELFStreamer {
182182
// Start the sandboxing sequence by emitting call.
183183
emitBundleLock(true);
184184
if (IsIndirectCall) {
185-
unsigned TargetReg = Inst.getOperand(1).getReg();
185+
MCRegister TargetReg = Inst.getOperand(1).getReg();
186186
emitMask(TargetReg, IndirectBranchMaskReg, STI);
187187
}
188188
MipsELFStreamer::emitInstruction(Inst, STI);
@@ -253,7 +253,7 @@ bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
253253
}
254254
}
255255

256-
bool baseRegNeedsLoadStoreMask(unsigned Reg) {
256+
bool baseRegNeedsLoadStoreMask(MCRegister Reg) {
257257
// The contents of SP and thread pointer register do not require masking.
258258
return Reg != Mips::SP && Reg != Mips::T8;
259259
}

‎llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp‎

Lines changed: 31 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -81,8 +81,8 @@ void MipsTargetStreamer::emitDirectiveNaNLegacy() {}
8181
void MipsTargetStreamer::emitDirectiveOptionPic0() {}
8282
void MipsTargetStreamer::emitDirectiveOptionPic2() {}
8383
void MipsTargetStreamer::emitDirectiveInsn() { forbidModuleDirective(); }
84-
void MipsTargetStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
85-
unsigned ReturnReg) {}
84+
void MipsTargetStreamer::emitFrame(MCRegister StackReg, unsigned StackSize,
85+
MCRegister ReturnReg) {}
8686
void MipsTargetStreamer::emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) {}
8787
void MipsTargetStreamer::emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) {
8888
}
@@ -173,7 +173,7 @@ void MipsTargetStreamer::emitDirectiveSetNoOddSPReg() {
173173
forbidModuleDirective();
174174
}
175175

176-
void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
176+
void MipsTargetStreamer::emitR(unsigned Opcode, MCRegister Reg0, SMLoc IDLoc,
177177
const MCSubtargetInfo *STI) {
178178
MCInst TmpInst;
179179
TmpInst.setOpcode(Opcode);
@@ -182,7 +182,7 @@ void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
182182
getStreamer().emitInstruction(TmpInst, *STI);
183183
}
184184

185-
void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1,
185+
void MipsTargetStreamer::emitRX(unsigned Opcode, MCRegister Reg0, MCOperand Op1,
186186
SMLoc IDLoc, const MCSubtargetInfo *STI) {
187187
MCInst TmpInst;
188188
TmpInst.setOpcode(Opcode);
@@ -192,13 +192,14 @@ void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1,
192192
getStreamer().emitInstruction(TmpInst, *STI);
193193
}
194194

195-
void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm,
195+
void MipsTargetStreamer::emitRI(unsigned Opcode, MCRegister Reg0, int32_t Imm,
196196
SMLoc IDLoc, const MCSubtargetInfo *STI) {
197197
emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI);
198198
}
199199

200-
void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
201-
SMLoc IDLoc, const MCSubtargetInfo *STI) {
200+
void MipsTargetStreamer::emitRR(unsigned Opcode, MCRegister Reg0,
201+
MCRegister Reg1, SMLoc IDLoc,
202+
const MCSubtargetInfo *STI) {
202203
emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI);
203204
}
204205

@@ -212,8 +213,8 @@ void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2,
212213
getStreamer().emitInstruction(TmpInst, *STI);
213214
}
214215

215-
void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
216-
MCOperand Op2, SMLoc IDLoc,
216+
void MipsTargetStreamer::emitRRX(unsigned Opcode, MCRegister Reg0,
217+
MCRegister Reg1, MCOperand Op2, SMLoc IDLoc,
217218
const MCSubtargetInfo *STI) {
218219
MCInst TmpInst;
219220
TmpInst.setOpcode(Opcode);
@@ -224,14 +225,15 @@ void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
224225
getStreamer().emitInstruction(TmpInst, *STI);
225226
}
226227

227-
void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
228-
unsigned Reg2, SMLoc IDLoc,
228+
void MipsTargetStreamer::emitRRR(unsigned Opcode, MCRegister Reg0,
229+
MCRegister Reg1, MCRegister Reg2, SMLoc IDLoc,
229230
const MCSubtargetInfo *STI) {
230231
emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI);
231232
}
232233

233-
void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
234-
unsigned Reg2, MCOperand Op3, SMLoc IDLoc,
234+
void MipsTargetStreamer::emitRRRX(unsigned Opcode, MCRegister Reg0,
235+
MCRegister Reg1, MCRegister Reg2,
236+
MCOperand Op3, SMLoc IDLoc,
235237
const MCSubtargetInfo *STI) {
236238
MCInst TmpInst;
237239
TmpInst.setOpcode(Opcode);
@@ -243,14 +245,14 @@ void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
243245
getStreamer().emitInstruction(TmpInst, *STI);
244246
}
245247

246-
void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1,
247-
int16_t Imm, SMLoc IDLoc,
248+
void MipsTargetStreamer::emitRRI(unsigned Opcode, MCRegister Reg0,
249+
MCRegister Reg1, int16_t Imm, SMLoc IDLoc,
248250
const MCSubtargetInfo *STI) {
249251
emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI);
250252
}
251253

252-
void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0,
253-
unsigned Reg1, int16_t Imm0, int16_t Imm1,
254+
void MipsTargetStreamer::emitRRIII(unsigned Opcode, MCRegister Reg0,
255+
MCRegister Reg1, int16_t Imm0, int16_t Imm1,
254256
int16_t Imm2, SMLoc IDLoc,
255257
const MCSubtargetInfo *STI) {
256258
MCInst TmpInst;
@@ -264,14 +266,14 @@ void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0,
264266
getStreamer().emitInstruction(TmpInst, *STI);
265267
}
266268

267-
void MipsTargetStreamer::emitAddu(unsigned DstReg, unsigned SrcReg,
268-
unsigned TrgReg, bool Is64Bit,
269+
void MipsTargetStreamer::emitAddu(MCRegister DstReg, MCRegister SrcReg,
270+
MCRegister TrgReg, bool Is64Bit,
269271
const MCSubtargetInfo *STI) {
270272
emitRRR(Is64Bit ? Mips::DADDu : Mips::ADDu, DstReg, SrcReg, TrgReg, SMLoc(),
271273
STI);
272274
}
273275

274-
void MipsTargetStreamer::emitDSLL(unsigned DstReg, unsigned SrcReg,
276+
void MipsTargetStreamer::emitDSLL(MCRegister DstReg, MCRegister SrcReg,
275277
int16_t ShiftAmount, SMLoc IDLoc,
276278
const MCSubtargetInfo *STI) {
277279
if (ShiftAmount >= 32) {
@@ -313,7 +315,7 @@ void MipsTargetStreamer::emitGPRestore(int Offset, SMLoc IDLoc,
313315

314316
/// Emit a store instruction with an immediate offset.
315317
void MipsTargetStreamer::emitStoreWithImmOffset(
316-
unsigned Opcode, unsigned SrcReg, unsigned BaseReg, int64_t Offset,
318+
unsigned Opcode, MCRegister SrcReg, MCRegister BaseReg, int64_t Offset,
317319
function_ref<unsigned()> GetATReg, SMLoc IDLoc,
318320
const MCSubtargetInfo *STI) {
319321
if (isInt<16>(Offset)) {
@@ -325,7 +327,7 @@ void MipsTargetStreamer::emitStoreWithImmOffset(
325327
// add $at, $at, $8
326328
// sw $8, %lo(offset)($at)
327329

328-
unsigned ATReg = GetATReg();
330+
MCRegister ATReg = GetATReg();
329331
if (!ATReg)
330332
return;
331333

@@ -349,10 +351,9 @@ void MipsTargetStreamer::emitStoreWithImmOffset(
349351
/// permitted to be the same register iff DstReg is distinct from BaseReg and
350352
/// DstReg is a GPR. It is the callers responsibility to identify such cases
351353
/// and pass the appropriate register in TmpReg.
352-
void MipsTargetStreamer::emitLoadWithImmOffset(unsigned Opcode, unsigned DstReg,
353-
unsigned BaseReg, int64_t Offset,
354-
unsigned TmpReg, SMLoc IDLoc,
355-
const MCSubtargetInfo *STI) {
354+
void MipsTargetStreamer::emitLoadWithImmOffset(
355+
unsigned Opcode, MCRegister DstReg, MCRegister BaseReg, int64_t Offset,
356+
MCRegister TmpReg, SMLoc IDLoc, const MCSubtargetInfo *STI) {
356357
if (isInt<16>(Offset)) {
357358
emitRRI(Opcode, DstReg, BaseReg, Offset, IDLoc, STI);
358359
return;
@@ -519,8 +520,8 @@ void MipsTargetAsmStreamer::emitDirectiveInsn() {
519520
OS << "\t.insn\n";
520521
}
521522

522-
void MipsTargetAsmStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
523-
unsigned ReturnReg) {
523+
void MipsTargetAsmStreamer::emitFrame(MCRegister StackReg, unsigned StackSize,
524+
MCRegister ReturnReg) {
524525
OS << "\t.frame\t$"
525526
<< StringRef(MipsInstPrinter::getRegisterName(StackReg)).lower() << ","
526527
<< StackSize << ",$"
@@ -1113,8 +1114,8 @@ void MipsTargetELFStreamer::emitDirectiveInsn() {
11131114
MEF.createPendingLabelRelocs();
11141115
}
11151116

1116-
void MipsTargetELFStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
1117-
unsigned ReturnReg_) {
1117+
void MipsTargetELFStreamer::emitFrame(MCRegister StackReg, unsigned StackSize,
1118+
MCRegister ReturnReg_) {
11181119
MCContext &Context = getStreamer().getAssembler().getContext();
11191120
const MCRegisterInfo *RegInfo = Context.getRegisterInfo();
11201121

‎llvm/lib/Target/Mips/MipsAsmPrinter.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -380,7 +380,7 @@ void MipsAsmPrinter::emitFrameDirective() {
380380
const TargetRegisterInfo &RI = *MF->getSubtarget().getRegisterInfo();
381381

382382
Register stackReg = RI.getFrameRegister(*MF);
383-
unsigned returnReg = RI.getRARegister();
383+
MCRegister returnReg = RI.getRARegister();
384384
unsigned stackSize = MF->getFrameInfo().getStackSize();
385385

386386
getTargetStreamer().emitFrame(stackReg, stackSize, returnReg);

‎llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,7 @@ void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
7070
MIB.addReg(Mips::DSPEFI, Flag);
7171
}
7272

73-
unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
73+
MCRegister MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
7474
uint64_t RegNum = RegIdx->getAsZExtVal();
7575
return Mips::MSACtrlRegClass.getRegister(RegNum);
7676
}

‎llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@ class MipsSEDAGToDAGISel : public MipsDAGToDAGISel {
3030
void addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
3131
MachineFunction &MF);
3232

33-
unsigned getMSACtrlReg(const SDValue RegIdx) const;
33+
MCRegister getMSACtrlReg(const SDValue RegIdx) const;
3434

3535
bool replaceUsesWithZeroReg(MachineRegisterInfo *MRI, const MachineInstr&);
3636

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