[AMDGPU][Verifier] Check address space of alloca instruction (llvm#135820)

This PR updates the `Verifier` to enforce that `alloca` instructions on
AMDGPU must be in AS5. This prevents hitting a misleading backend error
like "unable to select FrameIndex," which makes it look like a backend
bug when it's actually an IR-level issue.

Author: shiltian

llvm/lib/IR/Verifier.cpp

@@ -4418,6 +4418,11 @@ void Verifier::visitAllocaInst(AllocaInst &AI) {
     verifySwiftErrorValue(&AI);
   }
 
+  if (TT.isAMDGPU()) {
+    Check(AI.getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS,
+          "alloca on amdgpu must be in addrspace(5)", &AI);
+  }
+
   visitInstruction(AI);
 }
 

llvm/test/CodeGen/AMDGPU/assert-wrong-alloca-addrspace.ll

@@ -16,8 +16,9 @@ define amdgpu_kernel void @offloading_kernel() {
 }
 
 define void @call_unknown() {
-  %1 = alloca ptr, align 8
-  %2 = call i32 %1()
+  %alloca = alloca ptr, align 8, addrspace(5)
+  %alloca.cast = addrspacecast ptr addrspace(5) %alloca to ptr
+  %ret = call i32 %alloca.cast()
   ret void
 }
 

llvm/test/CodeGen/AMDGPU/lower-indirect-lds-references.ll

@@ -35,8 +35,8 @@ entry:
 
 define void @alloca() {
 entry:
-  %0 = alloca i1
-  call void @llvm.dbg.def(metadata !11, metadata i1* %0), !dbg !5
+  %0 = alloca i1, addrspace(5)
+  call void @llvm.dbg.def(metadata !11, metadata ptr addrspace(5) %0), !dbg !5
   call void @llvm.dbg.kill(metadata !11), !dbg !7
   unreachable
 }

llvm/test/CodeGen/Generic/llvm.dbg.def_kill-dag-isel.ll

@@ -3,9 +3,6 @@
 
 ; Gracefully handle the alloca that is not in the alloca AS (=5)
 
-target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
-target triple = "amdgcn-amd-amdhsa"
-
 declare void @use(ptr)
 declare void @use2(ptr, ptr)