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z1.cciauto
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merge main into amd-staging
2 parents 9945658 + 569b6f6 commit aa522ca

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36 files changed

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36 files changed

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‎clang/include/clang/Parse/ParseHLSLRootSignature.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -73,6 +73,7 @@ class RootSignatureParser {
7373
/// Root Element parse methods:
7474
std::optional<llvm::hlsl::rootsig::RootFlags> parseRootFlags();
7575
std::optional<llvm::hlsl::rootsig::RootConstants> parseRootConstants();
76+
std::optional<llvm::hlsl::rootsig::RootDescriptor> parseRootDescriptor();
7677
std::optional<llvm::hlsl::rootsig::DescriptorTable> parseDescriptorTable();
7778
std::optional<llvm::hlsl::rootsig::DescriptorTableClause>
7879
parseDescriptorTableClause();

‎clang/lib/Parse/ParseHLSLRootSignature.cpp

Lines changed: 43 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,14 @@ bool RootSignatureParser::parse() {
4747
return true;
4848
Elements.push_back(*Table);
4949
}
50+
51+
if (tryConsumeExpectedToken(
52+
{TokenKind::kw_CBV, TokenKind::kw_SRV, TokenKind::kw_UAV})) {
53+
auto Descriptor = parseRootDescriptor();
54+
if (!Descriptor.has_value())
55+
return true;
56+
Elements.push_back(*Descriptor);
57+
}
5058
} while (tryConsumeExpectedToken(TokenKind::pu_comma));
5159

5260
return consumeExpectedToken(TokenKind::end_of_stream,
@@ -155,6 +163,41 @@ std::optional<RootConstants> RootSignatureParser::parseRootConstants() {
155163
return Constants;
156164
}
157165

166+
std::optional<RootDescriptor> RootSignatureParser::parseRootDescriptor() {
167+
assert((CurToken.TokKind == TokenKind::kw_CBV ||
168+
CurToken.TokKind == TokenKind::kw_SRV ||
169+
CurToken.TokKind == TokenKind::kw_UAV) &&
170+
"Expects to only be invoked starting at given keyword");
171+
172+
TokenKind DescriptorKind = CurToken.TokKind;
173+
174+
if (consumeExpectedToken(TokenKind::pu_l_paren, diag::err_expected_after,
175+
CurToken.TokKind))
176+
return std::nullopt;
177+
178+
RootDescriptor Descriptor;
179+
switch (DescriptorKind) {
180+
default:
181+
llvm_unreachable("Switch for consumed token was not provided");
182+
case TokenKind::kw_CBV:
183+
Descriptor.Type = DescriptorType::CBuffer;
184+
break;
185+
case TokenKind::kw_SRV:
186+
Descriptor.Type = DescriptorType::SRV;
187+
break;
188+
case TokenKind::kw_UAV:
189+
Descriptor.Type = DescriptorType::UAV;
190+
break;
191+
}
192+
193+
if (consumeExpectedToken(TokenKind::pu_r_paren,
194+
diag::err_hlsl_unexpected_end_of_params,
195+
/*param of=*/TokenKind::kw_RootConstants))
196+
return std::nullopt;
197+
198+
return Descriptor;
199+
}
200+
158201
std::optional<DescriptorTable> RootSignatureParser::parseDescriptorTable() {
159202
assert(CurToken.TokKind == TokenKind::kw_DescriptorTable &&
160203
"Expects to only be invoked starting at given keyword");

‎clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,30 @@
1+
// RUN: %clang --target=riscv32 -mcpu=andes-a25 --print-enabled-extensions | FileCheck %s
2+
// REQUIRES: riscv-registered-target
3+
4+
// CHECK: Extensions enabled for the given RISC-V target
5+
// CHECK-EMPTY:
6+
// CHECK-NEXT: Name Version Description
7+
// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set)
8+
// CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division)
9+
// CHECK-NEXT: a 2.1 'A' (Atomic Instructions)
10+
// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
11+
// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
12+
// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
13+
// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
14+
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
15+
// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
16+
// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
17+
// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations)
18+
// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional)
19+
// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
20+
// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
21+
// CHECK-NEXT: zcf 1.0 'Zcf' (Compressed Single-Precision Floating-Point Instructions)
22+
// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
23+
// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
24+
// CHECK-NEXT: zbc 1.0 'Zbc' (Carry-Less Multiplication)
25+
// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
26+
// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
27+
// CHECK-EMPTY:
28+
// CHECK-NEXT: Experimental extensions
29+
// CHECK-EMPTY:
30+
// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0_xandesperf5p0

‎clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,29 @@
1+
// RUN: %clang --target=riscv64 -mcpu=andes-ax25 --print-enabled-extensions | FileCheck %s
2+
// REQUIRES: riscv-registered-target
3+
4+
// CHECK: Extensions enabled for the given RISC-V target
5+
// CHECK-EMPTY:
6+
// CHECK-NEXT: Name Version Description
7+
// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set)
8+
// CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division)
9+
// CHECK-NEXT: a 2.1 'A' (Atomic Instructions)
10+
// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
11+
// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
12+
// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
13+
// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
14+
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
15+
// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
16+
// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
17+
// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations)
18+
// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional)
19+
// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
20+
// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
21+
// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
22+
// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
23+
// CHECK-NEXT: zbc 1.0 'Zbc' (Carry-Less Multiplication)
24+
// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
25+
// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
26+
// CHECK-EMPTY:
27+
// CHECK-NEXT: Experimental extensions
28+
// CHECK-EMPTY:
29+
// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0_xandesperf5p0

‎clang/test/Driver/riscv-cpus.c

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -699,6 +699,22 @@
699699
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr7 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR7 %s
700700
// MTUNE-SYNTACORE-SCR7: "-tune-cpu" "syntacore-scr7"
701701

702+
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=andes-a25 | FileCheck -check-prefix=MCPU-ANDES-A25 %s
703+
// MCPU-ANDES-A25: "-target-cpu" "andes-a25"
704+
// COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-andes-a25.c`
705+
// MCPU-ANDES-A25-SAME: "-target-abi" "ilp32d"
706+
707+
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=andes-a25 | FileCheck -check-prefix=MTUNE-ANDES-A25 %s
708+
// MTUNE-ANDES-A25: "-tune-cpu" "andes-a25"
709+
710+
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=andes-ax25 | FileCheck -check-prefix=MCPU-ANDES-AX25 %s
711+
// MCPU-ANDES-AX25: "-target-cpu" "andes-ax25"
712+
// COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-andes-ax25.c`
713+
// MCPU-ANDES-AX25-SAME: "-target-abi" "lp64d"
714+
715+
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=andes-ax25 | FileCheck -check-prefix=MTUNE-ANDES-AX25 %s
716+
// MTUNE-ANDES-AX25: "-tune-cpu" "andes-ax25"
717+
702718
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=andes-n45 | FileCheck -check-prefix=MCPU-ANDES-N45 %s
703719
// MCPU-ANDES-N45: "-target-cpu" "andes-n45"
704720
// MCPU-ANDES-N45-SAME: "-target-feature" "+m"

‎clang/test/Misc/target-invalid-cpu-note/riscv.c

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,8 @@
55
// RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32
66
// RISCV32: error: unknown target CPU 'not-a-cpu'
77
// RISCV32-NEXT: note: valid target CPU values are:
8-
// RISCV32-SAME: {{^}} andes-a45
8+
// RISCV32-SAME: {{^}} andes-a25
9+
// RISCV32-SAME: {{^}}, andes-a45
910
// RISCV32-SAME: {{^}}, andes-n45
1011
// RISCV32-SAME: {{^}}, generic-rv32
1112
// RISCV32-SAME: {{^}}, rocket-rv32
@@ -26,7 +27,8 @@
2627
// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
2728
// RISCV64: error: unknown target CPU 'not-a-cpu'
2829
// RISCV64-NEXT: note: valid target CPU values are:
29-
// RISCV64-SAME: {{^}} andes-ax45
30+
// RISCV64-SAME: {{^}} andes-ax25
31+
// RISCV64-SAME: {{^}}, andes-ax45
3032
// RISCV64-SAME: {{^}}, andes-nx45
3133
// RISCV64-SAME: {{^}}, generic-rv64
3234
// RISCV64-SAME: {{^}}, mips-p8700
@@ -57,7 +59,8 @@
5759
// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
5860
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
5961
// TUNE-RISCV32-NEXT: note: valid target CPU values are:
60-
// TUNE-RISCV32-SAME: {{^}} andes-a45
62+
// TUNE-RISCV32-SAME: {{^}} andes-a25
63+
// TUNE-RISCV32-SAME: {{^}}, andes-a45
6164
// TUNE-RISCV32-SAME: {{^}}, andes-n45
6265
// TUNE-RISCV32-SAME: {{^}}, generic-rv32
6366
// TUNE-RISCV32-SAME: {{^}}, rocket-rv32
@@ -82,7 +85,8 @@
8285
// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
8386
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
8487
// TUNE-RISCV64-NEXT: note: valid target CPU values are:
85-
// TUNE-RISCV64-SAME: {{^}} andes-ax45
88+
// TUNE-RISCV64-SAME: {{^}} andes-ax25
89+
// TUNE-RISCV64-SAME: {{^}}, andes-ax45
8690
// TUNE-RISCV64-SAME: {{^}}, andes-nx45
8791
// TUNE-RISCV64-SAME: {{^}}, generic-rv64
8892
// TUNE-RISCV64-SAME: {{^}}, mips-p8700

‎clang/unittests/Parse/ParseHLSLRootSignatureTest.cpp

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -344,6 +344,43 @@ TEST_F(ParseHLSLRootSignatureTest, ValidParseRootFlagsTest) {
344344
ASSERT_TRUE(Consumer->isSatisfied());
345345
}
346346

347+
TEST_F(ParseHLSLRootSignatureTest, ValidParseRootDescriptorsTest) {
348+
const llvm::StringLiteral Source = R"cc(
349+
CBV(),
350+
SRV(),
351+
UAV()
352+
)cc";
353+
354+
TrivialModuleLoader ModLoader;
355+
auto PP = createPP(Source, ModLoader);
356+
auto TokLoc = SourceLocation();
357+
358+
hlsl::RootSignatureLexer Lexer(Source, TokLoc);
359+
SmallVector<RootElement> Elements;
360+
hlsl::RootSignatureParser Parser(Elements, Lexer, *PP);
361+
362+
// Test no diagnostics produced
363+
Consumer->setNoDiag();
364+
365+
ASSERT_FALSE(Parser.parse());
366+
367+
ASSERT_EQ(Elements.size(), 3u);
368+
369+
RootElement Elem = Elements[0];
370+
ASSERT_TRUE(std::holds_alternative<RootDescriptor>(Elem));
371+
ASSERT_EQ(std::get<RootDescriptor>(Elem).Type, DescriptorType::CBuffer);
372+
373+
Elem = Elements[1];
374+
ASSERT_TRUE(std::holds_alternative<RootDescriptor>(Elem));
375+
ASSERT_EQ(std::get<RootDescriptor>(Elem).Type, DescriptorType::SRV);
376+
377+
Elem = Elements[2];
378+
ASSERT_TRUE(std::holds_alternative<RootDescriptor>(Elem));
379+
ASSERT_EQ(std::get<RootDescriptor>(Elem).Type, DescriptorType::UAV);
380+
381+
ASSERT_TRUE(Consumer->isSatisfied());
382+
}
383+
347384
TEST_F(ParseHLSLRootSignatureTest, ValidTrailingCommaTest) {
348385
// This test will checks we can handling trailing commas ','
349386
const llvm::StringLiteral Source = R"cc(

‎flang/lib/Lower/OpenMP/Utils.cpp

Lines changed: 12 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -336,16 +336,18 @@ mlir::Value createParentSymAndGenIntermediateMaps(
336336
clauseLocation, firOpBuilder.getRefType(memberTy), curValue,
337337
llvm::SmallVector<fir::IntOrValue, 1>{idxConst});
338338

339-
// Skip mapping and the subsequent load if we're the final member or not
340-
// a type with a descriptor such as a pointer/allocatable. If we're a
341-
// final member, the map will be generated by the processMap call that
342-
// invoked this function, and if we're not a type with a descriptor then
343-
// we have no need of generating an intermediate map for it, as we only
344-
// need to generate a map if a member is a descriptor type (and thus
345-
// obscures the members it contains via a pointer in which it's data needs
346-
// mapped)
347-
if ((currentIndicesIdx == indices.size() - 1) ||
348-
!fir::isTypeWithDescriptor(memberTy)) {
339+
// If we're a final member, the map will be generated by the processMap
340+
// call that invoked this function.
341+
if (currentIndicesIdx == indices.size() - 1)
342+
break;
343+
344+
// Skip mapping and the subsequent load if we're not
345+
// a type with a descriptor such as a pointer/allocatable. If we're not a
346+
// type with a descriptor then we have no need of generating an
347+
// intermediate map for it, as we only need to generate a map if a member
348+
// is a descriptor type (and thus obscures the members it contains via a
349+
// pointer in which it's data needs mapped).
350+
if (!fir::isTypeWithDescriptor(memberTy)) {
349351
currentIndicesIdx++;
350352
continue;
351353
}

‎lld/test/COFF/lto-cache-errors.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7,8 +7,8 @@
77
; RUN: rm -Rf %t.cache && mkdir %t.cache
88
; RUN: chmod 444 %t.cache
99

10-
;; Check emit warnings when we can't create the cache dir
11-
; RUN: not --crash lld-link /lldltocache:%t.cache/nonexistant/ /out:%t3 /entry:main %t2.o %t.o 2>&1 | FileCheck %s
10+
;; Check fatal usage error emitted when the cache dir can't be created.
11+
; RUN: not lld-link /lldltocache:%t.cache/nonexistant/ /out:%t3 /entry:main %t2.o %t.o 2>&1 | FileCheck %s
1212
; CHECK: LLVM ERROR: can't create cache directory {{.*}}/nonexistant/: Permission denied
1313

1414
target datalayout = "e-m:w-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"

‎lld/test/ELF/lto/ltopasses-custom.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -24,13 +24,13 @@ define void @barrier() {
2424
; ATOMIC-NEXT: ret void
2525

2626
; Check that invalid passes are rejected gracefully.
27-
; RUN: env LLD_IN_TEST=1 not --crash ld.lld -m elf_x86_64 %t.o -o /dev/null \
27+
; RUN: env LLD_IN_TEST=1 not ld.lld -m elf_x86_64 %t.o -o /dev/null \
2828
; RUN: --lto-newpm-passes=iamnotapass -shared 2>&1 | \
2929
; RUN: FileCheck %s --check-prefix=INVALID
3030
; INVALID: unable to parse pass pipeline description 'iamnotapass': unknown pass name 'iamnotapass'
3131

3232
; Check that invalid AA pipelines are rejected gracefully.
33-
; RUN: env LLD_IN_TEST=1 not --crash ld.lld -m elf_x86_64 %t.o -o /dev/null \
33+
; RUN: env LLD_IN_TEST=1 not ld.lld -m elf_x86_64 %t.o -o /dev/null \
3434
; RUN: --lto-newpm-passes=globaldce --lto-aa-pipeline=patatino \
3535
; RUN: -shared 2>&1 | \
3636
; RUN: FileCheck %s --check-prefix=INVALIDAA

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