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merge main into amd-staging (#676)
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‎.github/workflows/gha-codeql.yml‎

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sparse-checkout: |
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.github/
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- name: Initialize CodeQL
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uses: github/codeql-action/init@014f16e7ab1402f30e7c3329d33797e7948572db # v4.31.3
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uses: github/codeql-action/init@e12f0178983d466f2f6028f5cc7a6d786fd97f4b # v4.31.4
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with:
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languages: actions
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queries: security-extended
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- name: Perform CodeQL Analysis
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uses: github/codeql-action/analyze@014f16e7ab1402f30e7c3329d33797e7948572db # v4.31.3
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uses: github/codeql-action/analyze@e12f0178983d466f2f6028f5cc7a6d786fd97f4b # v4.31.4

‎.github/workflows/libclang-abi-tests.yml‎

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needs: abi-dump-setup
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runs-on: ubuntu-24.04
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container:
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image: "ghcr.io/llvm/ci-ubuntu-24.04-abi-tests@sha256:f80125c0f767e29b8616210c0fd5cea2cd1f4fb6f2ca86d89f6016b6329b8d7f" #ghcr.io/llvm/ci-ubuntu-24.04-abi-tests:9524b37c503f
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image: "ghcr.io/llvm/ci-ubuntu-24.04-abi-tests@sha256:9138b6aea737d935e92ad2afdf5d49325880f9b187b5b979b135ac80cd456135" #ghcr.io/llvm/ci-ubuntu-24.04-abi-tests:9524b37c503f
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strategy:
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matrix:
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name:
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if: github.repository_owner == 'llvm'
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runs-on: ubuntu-24.04
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container:
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image: "ghcr.io/llvm/ci-ubuntu-24.04-abi-tests@sha256:f80125c0f767e29b8616210c0fd5cea2cd1f4fb6f2ca86d89f6016b6329b8d7f" #ghcr.io/llvm/ci-ubuntu-24.04-abi-tests:9524b37c503f
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image: "ghcr.io/llvm/ci-ubuntu-24.04-abi-tests@sha256:9138b6aea737d935e92ad2afdf5d49325880f9b187b5b979b135ac80cd456135" #ghcr.io/llvm/ci-ubuntu-24.04-abi-tests:9524b37c503f
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needs:
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- abi-dump-setup
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- abi-dump

‎.github/workflows/llvm-abi-tests.yml‎

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needs: abi-dump-setup
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runs-on: ubuntu-24.04
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container:
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image: "ghcr.io/llvm/ci-ubuntu-24.04-abi-tests@sha256:f80125c0f767e29b8616210c0fd5cea2cd1f4fb6f2ca86d89f6016b6329b8d7f" #ghcr.io/llvm/ci-ubuntu-24.04-abi-tests:bb0bd382ab2b"
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image: "ghcr.io/llvm/ci-ubuntu-24.04-abi-tests@sha256:9138b6aea737d935e92ad2afdf5d49325880f9b187b5b979b135ac80cd456135" #ghcr.io/llvm/ci-ubuntu-24.04-abi-tests:bb0bd382ab2b"
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strategy:
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matrix:
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name:
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if: github.repository_owner == 'llvm'
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runs-on: ubuntu-24.04
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container:
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image: "ghcr.io/llvm/ci-ubuntu-24.04-abi-tests@sha256:f80125c0f767e29b8616210c0fd5cea2cd1f4fb6f2ca86d89f6016b6329b8d7f" #ghcr.io/llvm/ci-ubuntu-24.04-abi-tests:bb0bd382ab2b
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image: "ghcr.io/llvm/ci-ubuntu-24.04-abi-tests@sha256:9138b6aea737d935e92ad2afdf5d49325880f9b187b5b979b135ac80cd456135" #ghcr.io/llvm/ci-ubuntu-24.04-abi-tests:bb0bd382ab2b
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needs:
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- abi-dump-setup
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- abi-dump

‎.github/workflows/scorecard.yml‎

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# Upload the results to GitHub's code scanning dashboard.
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- name: "Upload to code-scanning"
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uses: github/codeql-action/upload-sarif@014f16e7ab1402f30e7c3329d33797e7948572db # v4.31.3
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uses: github/codeql-action/upload-sarif@e12f0178983d466f2f6028f5cc7a6d786fd97f4b # v4.31.4
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with:
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sarif_file: results.sarif

‎.gitignore‎

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.claude/
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/GEMINI.md
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.gemini/
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AGENTS.md
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.codex/
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#==============================================================================#
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# Directories to ignore (do not add trailing '/'s, they skip symlinks).

‎bolt/include/bolt/Core/MCPlusBuilder.h‎

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@@ -1869,6 +1869,11 @@ class MCPlusBuilder {
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llvm_unreachable("not implemented");
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}
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/// Create a BTI landing pad instruction.
1873+
virtual void createBTI(MCInst &Inst, bool CallTarget, bool JumpTarget) const {
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llvm_unreachable("not implemented");
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}
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/// Store \p Target absolute address to \p RegName
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virtual InstructionListType materializeAddress(const MCSymbol *Target,
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MCContext *Ctx,

‎bolt/lib/Rewrite/RewriteInstance.cpp‎

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@@ -2078,7 +2078,7 @@ Error RewriteInstance::readSpecialSections() {
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if (BC->IsStripped && !opts::AllowStripped) {
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BC->errs()
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<< "BOLT-ERROR: stripped binaries are not supported. If you know "
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"what you're doing, use --allow-stripped to proceed";
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"what you're doing, use --allow-stripped to proceed\n";
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exit(1);
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}
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‎bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp‎

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@@ -2775,6 +2775,13 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
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return Insts;
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}
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void createBTI(MCInst &Inst, bool CallTarget,
2779+
bool JumpTarget) const override {
2780+
Inst.setOpcode(AArch64::HINT);
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unsigned HintNum = getBTIHintNum(CallTarget, JumpTarget);
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Inst.addOperand(MCOperand::createImm(HintNum));
2783+
}
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InstructionListType materializeAddress(const MCSymbol *Target, MCContext *Ctx,
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MCPhysReg RegName,
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int64_t Addend = 0) const override {

‎bolt/unittests/Core/MCPlusBuilder.cpp‎

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@@ -143,6 +143,36 @@ TEST_P(MCPlusBuilderTester, AArch64_CmpJE) {
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ASSERT_EQ(Label, BB->getLabel());
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}
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146+
TEST_P(MCPlusBuilderTester, AArch64_BTI) {
147+
if (GetParam() != Triple::aarch64)
148+
GTEST_SKIP();
149+
BinaryFunction *BF = BC->createInjectedBinaryFunction("BF", true);
150+
std::unique_ptr<BinaryBasicBlock> BB = BF->createBasicBlock();
151+
152+
MCInst BTIjc;
153+
BC->MIB->createBTI(BTIjc, true, true);
154+
BB->addInstruction(BTIjc);
155+
auto II = BB->begin();
156+
ASSERT_EQ(II->getOpcode(), AArch64::HINT);
157+
ASSERT_EQ(II->getOperand(0).getImm(), 38);
158+
159+
MCInst BTIj;
160+
BC->MIB->createBTI(BTIj, false, true);
161+
II = BB->addInstruction(BTIj);
162+
ASSERT_EQ(II->getOpcode(), AArch64::HINT);
163+
ASSERT_EQ(II->getOperand(0).getImm(), 36);
164+
165+
MCInst BTIc;
166+
BC->MIB->createBTI(BTIc, true, false);
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II = BB->addInstruction(BTIc);
168+
ASSERT_EQ(II->getOpcode(), AArch64::HINT);
169+
ASSERT_EQ(II->getOperand(0).getImm(), 34);
170+
171+
MCInst BTIinvalid;
172+
ASSERT_DEATH(BC->MIB->createBTI(BTIinvalid, false, false),
173+
"No target kinds!");
174+
}
175+
146176
TEST_P(MCPlusBuilderTester, AArch64_CmpJNE) {
147177
if (GetParam() != Triple::aarch64)
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GTEST_SKIP();

‎clang/include/clang/Basic/arm_mve_defs.td‎

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Original file line numberDiff line numberDiff line change
@@ -74,9 +74,9 @@ def immshr: CGHelperFn<"MVEImmediateShr"> {
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let special_params = [IRBuilderIntParam<1, "unsigned">,
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IRBuilderIntParam<2, "bool">];
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}
77-
def fadd: IRBuilder<"CreateFAdd">;
78-
def fmul: IRBuilder<"CreateFMul">;
79-
def fsub: IRBuilder<"CreateFSub">;
77+
def fadd_node: IRBuilder<"CreateFAdd">;
78+
def fmul_node: IRBuilder<"CreateFMul">;
79+
def fsub_node: IRBuilder<"CreateFSub">;
8080
def load: IRBuilder<"CreateLoad"> {
8181
let special_params = [IRBuilderAddrParam<0>];
8282
}
@@ -212,6 +212,13 @@ def unsignedflag;
212212
// constant giving its size in bits.
213213
def bitsize;
214214

215+
// strictFPAlt allows a node to have different code generation under strict-fp.
216+
// TODO: The standard node can be IRBuilderBase or IRIntBase.
217+
class strictFPAlt<IRBuilderBase standard_, IRIntBase strictfp_> {
218+
IRBuilderBase standard = standard_;
219+
IRIntBase strictfp = strictfp_;
220+
}
221+
215222
// If you put CustomCodegen<"foo"> in an intrinsic's codegen field, it
216223
// indicates that the IR generation for that intrinsic is done by handwritten
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// C++ and not autogenerated at all. The effect in the MVE builtin codegen
@@ -573,6 +580,14 @@ multiclass IntrinsicMXNameOverride<Type rettype, dag arguments, dag cg,
573580
}
574581
}
575582

583+
// StrictFP nodes that choose between standard fadd and llvm.arm.mve.fadd nodes
584+
// depending on whether we are using strict-fp.
585+
def fadd: strictFPAlt<fadd_node,
586+
IRInt<"vadd", [Vector]>>;
587+
def fsub: strictFPAlt<fsub_node,
588+
IRInt<"vsub", [Vector]>>;
589+
def fmul: strictFPAlt<fmul_node,
590+
IRInt<"vmul", [Vector]>>;
576591

577592
// -----------------------------------------------------------------------------
578593
// Convenience lists of parameter types. 'T' is just a container record, so you

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