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[MLIR][Linalg][Python] Improve bindings for linalg.elementwise (llvm#139462)
Adds wrappers for ElementWiseOp, in particular to ensure appropriate default indexing maps are derived.
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‎mlir/python/mlir/dialects/linalg/__init__.py‎

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Original file line numberDiff line numberDiff line change
@@ -216,6 +216,67 @@ def contract(
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)
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# Extend and shadow the TableGen-derived version to make sure correct default
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# indexing_maps are derived (as there is no mechanism for doing so given the
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# Python API bypasses the C++-builders).
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class ElementwiseOp_(ElementwiseOp):
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def __init__(
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self,
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result_tensors,
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inputs,
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outputs,
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kind,
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*,
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indexing_maps=None,
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loc=None,
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ip=None,
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):
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if indexing_maps is None:
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inputs = [_get_op_result_or_value(in_) for in_ in inputs]
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for in0, in1 in zip(inputs[:-1], inputs[1:]):
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assert in0.type == in1.type
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output = _get_op_result_or_value(outputs[0])
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assert inputs[0].type == output.type
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num_args = len(inputs) + 1
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indexing_maps = [AffineMap.get_identity(output.type.rank)] * num_args
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super().__init__(
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result_tensors=result_tensors,
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inputs=inputs,
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outputs=outputs,
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kind=kind,
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indexing_maps=indexing_maps,
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loc=loc,
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ip=ip,
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)
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ElementwiseOp = ElementwiseOp_
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def elementwise(
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*ins: Union[Operation, OpView, Value],
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outs: Sequence[Union[Operation, OpView, Value]],
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kind: Union[ElementwiseKind, Attribute],
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indexing_maps: Optional[Sequence[AffineMapAttr]] = None,
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):
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ins = [_get_op_result_or_value(input) for input in ins]
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if len(outs) != 1:
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raise ValueError(f"{outs=} must have length 1.")
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init = _get_op_result_or_value(outs[0])
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result_types = [init.type] if isinstance(init.type, RankedTensorType) else []
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op = ElementwiseOp(
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result_tensors=result_types,
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inputs=ins,
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outputs=[init],
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kind=kind,
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indexing_maps=indexing_maps,
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)
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fill_builtin_region(op.operation)
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return _get_op_result_or_op_results(op)
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def pack(
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source,
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dest,

‎mlir/test/python/dialects/linalg/ops.py‎

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Original file line numberDiff line numberDiff line change
@@ -606,3 +606,189 @@ def tensor_pack(src, dst):
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# CHECK: return %[[VAL_4]] : tensor<128x128xf32>
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# CHECK: }
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print(module)
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# CHECK-LABEL: TEST: testElementwiseOp
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@run
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def testElementwiseOp():
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with Context(), Location.unknown():
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module = Module.create()
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f32 = F32Type.get()
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with InsertionPoint(module.body):
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rect_shape = (8, 16)
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vert_line_shape = (8,)
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hor_line_shape = (16,)
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transposed_rect_shape = (16, 8)
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# CHECK-DAG: #[[$IdentMap2D:.*]] = affine_map<(d0, d1) -> (d0, d1)>
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# CHECK-DAG: #[[$TransMap2D:.*]] = affine_map<(d0, d1) -> (d1, d0)>
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# CHECK-DAG: #[[$VertLineBCastMap:.*]] = affine_map<(d0, d1) -> (d0)>
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# CHECK-DAG: #[[$HorLineBCastMap:.*]] = affine_map<(d0, d1) -> (d1)>
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ident_map_2d = AffineMap.get_identity(2)
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transposed_map_2d = AffineMap.get_permutation((1, 0))
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vert_line_bcast_map = AffineMap.get(2, 0, [AffineDimExpr.get(0)])
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hor_line_bcast_map = AffineMap.get(2, 0, [AffineDimExpr.get(1)])
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# CHECK: func.func @elementwise_op(
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@func.FuncOp.from_py_func(
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# CHECK-SAME: %[[Rect:.*]]: tensor<8x16xf32>,
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RankedTensorType.get(rect_shape, f32),
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# CHECK-SAME: %[[RectMem:.*]]: memref<8x16xf32>,
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MemRefType.get(rect_shape, f32),
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# CHECK-SAME: %[[VertLine:.*]]: tensor<8xf32>,
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RankedTensorType.get(vert_line_shape, f32),
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# CHECK-SAME: %[[VertLineMem:.*]]: memref<8xf32>,
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MemRefType.get(vert_line_shape, f32),
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# CHECK-SAME: %[[HorLine:.*]]: tensor<16xf32>,
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RankedTensorType.get(hor_line_shape, f32),
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# CHECK-SAME: %[[HorLineMem:.*]]: memref<16xf32>,
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MemRefType.get(hor_line_shape, f32),
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# CHECK-SAME: %[[TransRect:.*]]: tensor<16x8xf32>,
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RankedTensorType.get(transposed_rect_shape, f32),
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# CHECK-SAME: %[[TransRectMem:.*]]: memref<16x8xf32>)
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MemRefType.get(transposed_rect_shape, f32),
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)
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def elementwise_op(
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rect,
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rect_mem,
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vert_line,
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vert_line_mem,
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hor_line,
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hor_line_mem,
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trans_rect,
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trans_rect_mem,
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):
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# CHECK: %[[OutRect:.*]] = tensor.empty() : tensor<8x16xf32>
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out_rect = tensor.EmptyOp(rect_shape, f32)
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# CHECK: %[[OutRectMem:.*]] = memref.alloca() : memref<8x16xf32>
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out_rect_mem = memref.alloca(MemRefType.get(rect_shape, f32), [], [])
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if _inferred_affine_maps := True:
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# CHECK: linalg.elementwise
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# CHECK-SAME: kind=#linalg.elementwise_kind<exp>
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# CHECK-SAME: ins(%[[Rect]] : tensor<8x16xf32>)
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# CHECK-SAME: outs(%[[OutRect]] : tensor<8x16xf32>) -> tensor<8x16xf32>
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op1 = linalg.ElementwiseOp(
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result_tensors=(out_rect.result.type,),
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inputs=(rect,),
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outputs=(out_rect,),
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kind=linalg.ElementwiseKind.exp,
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)
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linalg.fill_builtin_region(op1.operation)
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# CHECK: linalg.elementwise
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# CHECK-SAME: kind=#linalg.elementwise_kind<exp>
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# CHECK-SAME: ins(%[[Rect]] : tensor<8x16xf32>)
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# CHECK-SAME: outs(%[[OutRect]] : tensor<8x16xf32>) -> tensor<8x16xf32>
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linalg.elementwise(
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rect,
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outs=(out_rect,),
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kind=linalg.ElementwiseKind.exp,
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)
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# CHECK: linalg.elementwise
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# CHECK-SAME: kind=#linalg.elementwise_kind<exp>
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# CHECK-SAME: ins(%[[RectMem]] : memref<8x16xf32>)
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# CHECK-SAME: outs(%[[OutRectMem]] : memref<8x16xf32>)
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linalg.elementwise(
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rect_mem,
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outs=(out_rect_mem,),
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kind=linalg.ElementwiseKind.exp,
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)
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if _explicit_ident_affine_maps := True:
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# Same as above but with default identity indexing_maps explicitly provided.
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# CHECK: linalg.elementwise
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# CHECK-SAME: kind=#linalg.elementwise_kind<exp>
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# CHECK-SAME: ins(%[[Rect]] : tensor<8x16xf32>)
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# CHECK-SAME: outs(%[[OutRect]] : tensor<8x16xf32>) -> tensor<8x16xf32>
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op3 = linalg.ElementwiseOp(
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result_tensors=(out_rect.result.type,),
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inputs=(rect,),
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outputs=(out_rect,),
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kind=linalg.ElementwiseKind.exp,
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indexing_maps=[ident_map_2d, ident_map_2d],
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)
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linalg.fill_builtin_region(op3.operation)
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# CHECK: linalg.elementwise
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# CHECK-SAME: kind=#linalg.elementwise_kind<exp>
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# CHECK-SAME: ins(%[[RectMem]] : memref<8x16xf32>)
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# CHECK-SAME: outs(%[[OutRectMem]] : memref<8x16xf32>)
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linalg.elementwise(
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rect_mem,
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outs=(out_rect_mem,),
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kind=linalg.ElementwiseKind.exp,
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indexing_maps=[ident_map_2d, ident_map_2d],
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)
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if _ops_with_non_ident_input_maps := True:
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# CHECK: linalg.elementwise kind=#linalg.elementwise_kind<exp>
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# CHECK-SAME: indexing_maps = [#[[$VertLineBCastMap]], #[[$IdentMap2D]]]
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# CHECK-SAME: ins(%[[VertLine]] : tensor<8xf32>)
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# CHECK-SAME: outs(%[[OutRect]] : tensor<8x16xf32>) -> tensor<8x16xf32>
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op4 = linalg.ElementwiseOp(
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result_tensors=(out_rect.result.type,),
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inputs=(vert_line,),
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outputs=(out_rect,),
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kind=linalg.ElementwiseKind.exp,
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indexing_maps=[vert_line_bcast_map, ident_map_2d],
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)
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linalg.fill_builtin_region(op4.operation)
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# CHECK: linalg.elementwise kind=#linalg.elementwise_kind<add>
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# CHECK-SAME: indexing_maps = [#[[$IdentMap2D]], #[[$VertLineBCastMap]], #[[$IdentMap2D]]]
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# CHECK-SAME: ins(%[[Rect]], %[[VertLine]] : tensor<8x16xf32>, tensor<8xf32>)
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# CHECK-SAME: outs(%[[OutRect]] : tensor<8x16xf32>) -> tensor<8x16xf32>
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op4 = linalg.ElementwiseOp(
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result_tensors=(out_rect.result.type,),
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inputs=(rect, vert_line),
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outputs=(out_rect,),
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kind=linalg.ElementwiseKind.add,
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indexing_maps=[ident_map_2d, vert_line_bcast_map, ident_map_2d],
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)
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linalg.fill_builtin_region(op4.operation)
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# CHECK: linalg.elementwise kind=#linalg.elementwise_kind<div>
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# CHECK-SAME: indexing_maps = [#[[$VertLineBCastMap]], #[[$HorLineBCastMap]], #[[$IdentMap2D]]]
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# CHECK-SAME: ins(%[[VertLine]], %[[HorLine]] : tensor<8xf32>, tensor<16xf32>)
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# CHECK-SAME: outs(%[[OutRect]] : tensor<8x16xf32>) -> tensor<8x16xf32>
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linalg.elementwise(
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vert_line,
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hor_line,
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outs=(out_rect,),
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kind=linalg.ElementwiseKind.div,
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indexing_maps=[
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vert_line_bcast_map,
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hor_line_bcast_map,
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ident_map_2d,
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],
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)
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if _ops_with_non_ident_and_transposed_input_maps := True:
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# CHECK: %[[VertLineBoolsMem:.*]] = memref.alloca() : memref<8xi1>
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vert_line_bools_mem = memref.alloca(
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MemRefType.get(vert_line_shape, IntegerType.get_signless(1)),
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[],
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[],
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)
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# CHECK: linalg.elementwise kind=#linalg.elementwise_kind<select>
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# CHECK-SAME: indexing_maps = [#[[$VertLineBCastMap]], #[[$HorLineBCastMap]], #[[$TransMap2D]], #[[$IdentMap2D]]]
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# CHECK-SAME: ins(%[[VertLineBoolsMem]], %[[HorLineMem]], %[[TransRectMem]] : memref<8xi1>, memref<16xf32>, memref<16x8xf32>)
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# CHECK-SAME: outs(%[[OutRectMem]] : memref<8x16xf32>)
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linalg.elementwise(
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vert_line_bools_mem,
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hor_line_mem,
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trans_rect_mem,
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outs=(out_rect_mem,),
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kind=linalg.ElementwiseKind.select,
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indexing_maps=[
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vert_line_bcast_map,
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hor_line_bcast_map,
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transposed_map_2d,
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ident_map_2d,
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],
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)
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print(module)

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