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z1-cciautoz1-cciauto
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merge main into amd-staging
2 parents 4e544f4 + 28c14d4 commit c323b82

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94 files changed

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‎bolt/lib/Profile/DataAggregator.cpp‎

Lines changed: 17 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -61,6 +61,12 @@ FilterMemProfile("filter-mem-profile",
6161
cl::init(true),
6262
cl::cat(AggregatorCategory));
6363

64+
static cl::opt<bool> ParseMemProfile(
65+
"parse-mem-profile",
66+
cl::desc("enable memory profile parsing if it's present in the input data, "
67+
"on by default unless `--itrace` is set."),
68+
cl::init(true), cl::cat(AggregatorCategory));
69+
6470
static cl::opt<unsigned long long>
6571
FilterPID("pid",
6672
cl::desc("only use samples from process with specified PID"),
@@ -181,6 +187,10 @@ void DataAggregator::start() {
181187
"script -F pid,event,ip",
182188
/*Wait = */false);
183189
} else if (!opts::ITraceAggregation.empty()) {
190+
// Disable parsing memory profile from trace data, unless requested by user.
191+
if (!opts::ParseMemProfile.getNumOccurrences())
192+
opts::ParseMemProfile = false;
193+
184194
std::string ItracePerfScriptArgs = llvm::formatv(
185195
"script -F pid,brstack --itrace={0}", opts::ITraceAggregation);
186196
launchPerfProcess("branch events with itrace", MainEventsPPI,
@@ -191,12 +201,9 @@ void DataAggregator::start() {
191201
/*Wait = */ false);
192202
}
193203

194-
// Note: we launch script for mem events regardless of the option, as the
195-
// command fails fairly fast if mem events were not collected.
196-
launchPerfProcess("mem events",
197-
MemEventsPPI,
198-
"script -F pid,event,addr,ip",
199-
/*Wait = */false);
204+
if (opts::ParseMemProfile)
205+
launchPerfProcess("mem events", MemEventsPPI, "script -F pid,event,addr,ip",
206+
/*Wait = */ false);
200207

201208
launchPerfProcess("process events", MMapEventsPPI,
202209
"script --show-mmap-events --no-itrace",
@@ -217,7 +224,8 @@ void DataAggregator::abort() {
217224
sys::Wait(TaskEventsPPI.PI, 1, &Error);
218225
sys::Wait(MMapEventsPPI.PI, 1, &Error);
219226
sys::Wait(MainEventsPPI.PI, 1, &Error);
220-
sys::Wait(MemEventsPPI.PI, 1, &Error);
227+
if (opts::ParseMemProfile)
228+
sys::Wait(MemEventsPPI.PI, 1, &Error);
221229

222230
deleteTempFiles();
223231

@@ -506,7 +514,8 @@ Error DataAggregator::preprocessProfile(BinaryContext &BC) {
506514
errs() << "PERF2BOLT: failed to parse samples\n";
507515

508516
// Special handling for memory events
509-
if (!prepareToParse("mem events", MemEventsPPI, MemEventsErrorCallback))
517+
if (opts::ParseMemProfile &&
518+
!prepareToParse("mem events", MemEventsPPI, MemEventsErrorCallback))
510519
if (const std::error_code EC = parseMemEvents())
511520
errs() << "PERF2BOLT: failed to parse memory events: " << EC.message()
512521
<< '\n';

‎clang/include/clang/CIR/MissingFeatures.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -172,6 +172,7 @@ struct MissingFeatures {
172172
static bool astVarDeclInterface() { return false; }
173173
static bool stackSaveOp() { return false; }
174174
static bool aggValueSlot() { return false; }
175+
static bool aggValueSlotMayOverlap() { return false; }
175176
static bool generateDebugInfo() { return false; }
176177
static bool pointerOverflowSanitizer() { return false; }
177178
static bool fpConstraints() { return false; }
@@ -227,7 +228,6 @@ struct MissingFeatures {
227228
static bool implicitConstructorArgs() { return false; }
228229
static bool intrinsics() { return false; }
229230
static bool attributeNoBuiltin() { return false; }
230-
static bool emitCtorPrologue() { return false; }
231231
static bool thunks() { return false; }
232232
static bool runCleanupsScope() { return false; }
233233

‎clang/lib/Basic/Targets/PPC.cpp‎

Lines changed: 141 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,6 @@
1515
#include "clang/Basic/MacroBuilder.h"
1616
#include "clang/Basic/TargetBuiltins.h"
1717
#include "llvm/TargetParser/PPCTargetParser.h"
18-
#include <optional>
1918

2019
using namespace clang;
2120
using namespace clang::targets;
@@ -517,14 +516,129 @@ static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
517516
bool PPCTargetInfo::initFeatureMap(
518517
llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
519518
const std::vector<std::string> &FeaturesVec) const {
519+
Features["altivec"] = llvm::StringSwitch<bool>(CPU)
520+
.Case("7400", true)
521+
.Case("g4", true)
522+
.Case("7450", true)
523+
.Case("g4+", true)
524+
.Case("970", true)
525+
.Case("g5", true)
526+
.Case("pwr6", true)
527+
.Case("pwr7", true)
528+
.Case("pwr8", true)
529+
.Case("pwr9", true)
530+
.Case("ppc64", true)
531+
.Case("ppc64le", true)
532+
.Default(false);
533+
534+
Features["power9-vector"] = (CPU == "pwr9");
535+
Features["crypto"] = llvm::StringSwitch<bool>(CPU)
536+
.Case("ppc64le", true)
537+
.Case("pwr9", true)
538+
.Case("pwr8", true)
539+
.Default(false);
540+
Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
541+
.Case("ppc64le", true)
542+
.Case("pwr9", true)
543+
.Case("pwr8", true)
544+
.Default(false);
545+
Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
546+
.Case("ppc64le", true)
547+
.Case("pwr9", true)
548+
.Case("pwr8", true)
549+
.Case("pwr7", true)
550+
.Default(false);
551+
Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
552+
.Case("ppc64le", true)
553+
.Case("pwr9", true)
554+
.Case("pwr8", true)
555+
.Case("pwr7", true)
556+
.Default(false);
557+
Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
558+
.Case("ppc64le", true)
559+
.Case("pwr9", true)
560+
.Case("pwr8", true)
561+
.Default(false);
562+
Features["crbits"] = llvm::StringSwitch<bool>(CPU)
563+
.Case("ppc64le", true)
564+
.Case("pwr9", true)
565+
.Case("pwr8", true)
566+
.Default(false);
567+
Features["vsx"] = llvm::StringSwitch<bool>(CPU)
568+
.Case("ppc64le", true)
569+
.Case("pwr9", true)
570+
.Case("pwr8", true)
571+
.Case("pwr7", true)
572+
.Default(false);
573+
Features["htm"] = llvm::StringSwitch<bool>(CPU)
574+
.Case("ppc64le", true)
575+
.Case("pwr9", true)
576+
.Case("pwr8", true)
577+
.Default(false);
578+
579+
// ROP Protect is off by default.
580+
Features["rop-protect"] = false;
581+
// Privileged instructions are off by default.
582+
Features["privileged"] = false;
520583

521-
const llvm::Triple &TheTriple = getTriple();
584+
if (getTriple().isOSAIX()) {
585+
// The code generated by the -maix-small-local-[exec|dynamic]-tls option is
586+
// turned off by default.
587+
Features["aix-small-local-exec-tls"] = false;
588+
Features["aix-small-local-dynamic-tls"] = false;
589+
590+
// Turn off TLS model opt by default.
591+
Features["aix-shared-lib-tls-model-opt"] = false;
592+
}
593+
594+
Features["spe"] = llvm::StringSwitch<bool>(CPU)
595+
.Case("8548", true)
596+
.Case("e500", true)
597+
.Default(false);
598+
599+
Features["isa-v206-instructions"] = llvm::StringSwitch<bool>(CPU)
600+
.Case("ppc64le", true)
601+
.Case("pwr9", true)
602+
.Case("pwr8", true)
603+
.Case("pwr7", true)
604+
.Case("a2", true)
605+
.Default(false);
606+
607+
Features["isa-v207-instructions"] = llvm::StringSwitch<bool>(CPU)
608+
.Case("ppc64le", true)
609+
.Case("pwr9", true)
610+
.Case("pwr8", true)
611+
.Default(false);
612+
613+
Features["isa-v30-instructions"] =
614+
llvm::StringSwitch<bool>(CPU).Case("pwr9", true).Default(false);
615+
616+
Features["quadword-atomics"] =
617+
getTriple().isArch64Bit() && llvm::StringSwitch<bool>(CPU)
618+
.Case("pwr9", true)
619+
.Case("pwr8", true)
620+
.Default(false);
621+
622+
// Power10 includes all the same features as Power9 plus any features specific
623+
// to the Power10 core.
624+
if (CPU == "pwr10" || CPU == "power10") {
625+
initFeatureMap(Features, Diags, "pwr9", FeaturesVec);
626+
addP10SpecificFeatures(Features);
627+
}
628+
629+
// Power11 includes all the same features as Power10 plus any features
630+
// specific to the Power11 core.
631+
if (CPU == "pwr11" || CPU == "power11") {
632+
initFeatureMap(Features, Diags, "pwr10", FeaturesVec);
633+
addP11SpecificFeatures(Features);
634+
}
522635

523-
std::optional<llvm::StringMap<bool>> FeaturesOpt =
524-
llvm::PPC::getPPCDefaultTargetFeatures(TheTriple,
525-
llvm::PPC::normalizeCPUName(CPU));
526-
if (FeaturesOpt)
527-
Features = FeaturesOpt.value();
636+
// Future CPU should include all of the features of Power 11 as well as any
637+
// additional features (yet to be determined) specific to it.
638+
if (CPU == "future") {
639+
initFeatureMap(Features, Diags, "pwr11", FeaturesVec);
640+
addFutureSpecificFeatures(Features);
641+
}
528642

529643
if (!ppcUserFeaturesCheck(Diags, FeaturesVec))
530644
return false;
@@ -586,6 +700,26 @@ bool PPCTargetInfo::initFeatureMap(
586700
return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
587701
}
588702

703+
// Add any Power10 specific features.
704+
void PPCTargetInfo::addP10SpecificFeatures(
705+
llvm::StringMap<bool> &Features) const {
706+
Features["htm"] = false; // HTM was removed for P10.
707+
Features["paired-vector-memops"] = true;
708+
Features["mma"] = true;
709+
Features["power10-vector"] = true;
710+
Features["pcrelative-memops"] = true;
711+
Features["prefix-instrs"] = true;
712+
Features["isa-v31-instructions"] = true;
713+
}
714+
715+
// Add any Power11 specific features.
716+
void PPCTargetInfo::addP11SpecificFeatures(
717+
llvm::StringMap<bool> &Features) const {}
718+
719+
// Add features specific to the "Future" CPU.
720+
void PPCTargetInfo::addFutureSpecificFeatures(
721+
llvm::StringMap<bool> &Features) const {}
722+
589723
bool PPCTargetInfo::hasFeature(StringRef Feature) const {
590724
return llvm::StringSwitch<bool>(Feature)
591725
.Case("powerpc", true)

‎clang/lib/CIR/CodeGen/CIRGenCall.cpp‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -189,8 +189,7 @@ void CIRGenFunction::emitDelegateCallArg(CallArgList &args,
189189
// For the most part, we just need to load the alloca, except that aggregate
190190
// r-values are actually pointers to temporaries.
191191
} else {
192-
cgm.errorNYI(param->getSourceRange(),
193-
"emitDelegateCallArg: convertTempToRValue");
192+
args.add(convertTempToRValue(local, type, loc), type);
194193
}
195194

196195
// Deactivate the cleanup for the callee-destructed param that was pushed.

‎clang/lib/CIR/CodeGen/CIRGenClass.cpp‎

Lines changed: 38 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -53,6 +53,21 @@ bool CIRGenFunction::isConstructorDelegationValid(
5353
return true;
5454
}
5555

56+
/// This routine generates necessary code to initialize base classes and
57+
/// non-static data members belonging to this constructor.
58+
void CIRGenFunction::emitCtorPrologue(const CXXConstructorDecl *cd,
59+
CXXCtorType ctorType,
60+
FunctionArgList &args) {
61+
if (cd->isDelegatingConstructor())
62+
return emitDelegatingCXXConstructorCall(cd, args);
63+
64+
if (cd->getNumCtorInitializers() != 0) {
65+
// There's much more to do here.
66+
cgm.errorNYI(cd->getSourceRange(), "emitCtorPrologue: any initializer");
67+
return;
68+
}
69+
}
70+
5671
Address CIRGenFunction::loadCXXThisAddress() {
5772
assert(curFuncDecl && "loading 'this' without a func declaration?");
5873
assert(isa<CXXMethodDecl>(curFuncDecl));
@@ -102,6 +117,29 @@ void CIRGenFunction::emitDelegateCXXConstructorCall(
102117
/*Delegating=*/true, thisAddr, delegateArgs, loc);
103118
}
104119

120+
void CIRGenFunction::emitDelegatingCXXConstructorCall(
121+
const CXXConstructorDecl *ctor, const FunctionArgList &args) {
122+
assert(ctor->isDelegatingConstructor());
123+
124+
Address thisPtr = loadCXXThisAddress();
125+
126+
assert(!cir::MissingFeatures::objCGC());
127+
assert(!cir::MissingFeatures::sanitizers());
128+
AggValueSlot aggSlot = AggValueSlot::forAddr(
129+
thisPtr, Qualifiers(), AggValueSlot::IsDestructed,
130+
AggValueSlot::IsNotAliased, AggValueSlot::MayOverlap,
131+
AggValueSlot::IsNotZeroed);
132+
133+
emitAggExpr(ctor->init_begin()[0]->getInit(), aggSlot);
134+
135+
const CXXRecordDecl *classDecl = ctor->getParent();
136+
if (cgm.getLangOpts().Exceptions && !classDecl->hasTrivialDestructor()) {
137+
cgm.errorNYI(ctor->getSourceRange(),
138+
"emitDelegatingCXXConstructorCall: exception");
139+
return;
140+
}
141+
}
142+
105143
Address CIRGenFunction::getAddressOfBaseClass(
106144
Address value, const CXXRecordDecl *derived,
107145
llvm::iterator_range<CastExpr::path_const_iterator> path,

‎clang/lib/CIR/CodeGen/CIRGenDecl.cpp‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -259,7 +259,12 @@ void CIRGenFunction::emitExprAsInit(const Expr *init, const ValueDecl *d,
259259
return;
260260
}
261261
case cir::TEK_Aggregate:
262-
emitAggExpr(init, AggValueSlot::forLValue(lvalue));
262+
// The overlap flag here should be calculated.
263+
assert(!cir::MissingFeatures::aggValueSlotMayOverlap());
264+
emitAggExpr(init,
265+
AggValueSlot::forLValue(lvalue, AggValueSlot::IsDestructed,
266+
AggValueSlot::IsNotAliased,
267+
AggValueSlot::MayOverlap));
263268
return;
264269
}
265270
llvm_unreachable("bad evaluation kind");

‎clang/lib/CIR/CodeGen/CIRGenExpr.cpp‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1261,6 +1261,23 @@ Address CIRGenFunction::emitArrayToPointerDecay(const Expr *e) {
12611261
return Address(ptr, addr.getAlignment());
12621262
}
12631263

1264+
/// Given the address of a temporary variable, produce an r-value of its type.
1265+
RValue CIRGenFunction::convertTempToRValue(Address addr, clang::QualType type,
1266+
clang::SourceLocation loc) {
1267+
LValue lvalue = makeAddrLValue(addr, type, AlignmentSource::Decl);
1268+
switch (getEvaluationKind(type)) {
1269+
case cir::TEK_Complex:
1270+
cgm.errorNYI(loc, "convertTempToRValue: complex type");
1271+
return RValue::get(nullptr);
1272+
case cir::TEK_Aggregate:
1273+
cgm.errorNYI(loc, "convertTempToRValue: aggregate type");
1274+
return RValue::get(nullptr);
1275+
case cir::TEK_Scalar:
1276+
return RValue::get(emitLoadOfScalar(lvalue, loc));
1277+
}
1278+
llvm_unreachable("bad evaluation kind");
1279+
}
1280+
12641281
/// Emit an `if` on a boolean condition, filling `then` and `else` into
12651282
/// appropriated regions.
12661283
mlir::LogicalResult CIRGenFunction::emitIfOnBoolExpr(const Expr *cond,
@@ -1473,6 +1490,10 @@ void CIRGenFunction::emitCXXConstructExpr(const CXXConstructExpr *e,
14731490
type = Ctor_Complete;
14741491
break;
14751492
case CXXConstructionKind::Delegating:
1493+
// We should be emitting a constructor; GlobalDecl will assert this
1494+
type = curGD.getCtorType();
1495+
delegating = true;
1496+
break;
14761497
case CXXConstructionKind::VirtualBase:
14771498
case CXXConstructionKind::NonVirtualBase:
14781499
cgm.errorNYI(e->getSourceRange(),

‎clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp‎

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -203,7 +203,11 @@ void AggExprEmitter::emitInitializationToLValue(Expr *e, LValue lv) {
203203
cgf.cgm.errorNYI("emitInitializationToLValue TEK_Complex");
204204
break;
205205
case cir::TEK_Aggregate:
206-
cgf.emitAggExpr(e, AggValueSlot::forLValue(lv));
206+
cgf.emitAggExpr(e, AggValueSlot::forLValue(lv, AggValueSlot::IsDestructed,
207+
AggValueSlot::IsNotAliased,
208+
AggValueSlot::MayOverlap,
209+
dest.isZeroed()));
210+
207211
return;
208212
case cir::TEK_Scalar:
209213
if (lv.isSimple())
@@ -284,6 +288,8 @@ LValue CIRGenFunction::emitAggExprToLValue(const Expr *e) {
284288
assert(hasAggregateEvaluationKind(e->getType()) && "Invalid argument!");
285289
Address temp = createMemTemp(e->getType(), getLoc(e->getSourceRange()));
286290
LValue lv = makeAddrLValue(temp, e->getType());
287-
emitAggExpr(e, AggValueSlot::forLValue(lv));
291+
emitAggExpr(e, AggValueSlot::forLValue(lv, AggValueSlot::IsNotDestructed,
292+
AggValueSlot::IsNotAliased,
293+
AggValueSlot::DoesNotOverlap));
288294
return lv;
289295
}

‎clang/lib/CIR/CodeGen/CIRGenFunction.cpp‎

Lines changed: 2 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -526,14 +526,8 @@ void CIRGenFunction::emitConstructorBody(FunctionArgList &args) {
526526
// TODO: in restricted cases, we can emit the vbase initializers of a
527527
// complete ctor and then delegate to the base ctor.
528528

529-
assert(!cir::MissingFeatures::emitCtorPrologue());
530-
if (ctor->isDelegatingConstructor()) {
531-
// This will be handled in emitCtorPrologue, but we should emit a diagnostic
532-
// rather than silently fail to delegate.
533-
cgm.errorNYI(ctor->getSourceRange(),
534-
"emitConstructorBody: delegating ctor");
535-
return;
536-
}
529+
// Emit the constructor prologue, i.e. the base and member initializers.
530+
emitCtorPrologue(ctor, ctorType, args);
537531

538532
// TODO(cir): propagate this result via mlir::logical result. Just unreachable
539533
// now just to have it handled.

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