merge main into amd-staging

Author: z1.cciauto

clang/lib/AST/Decl.cpp

@@ -400,9 +400,9 @@ void LinkageComputer::mergeTemplateLV(
   FunctionTemplateDecl *temp = specInfo->getTemplate();
   // Merge information from the template declaration.
   LinkageInfo tempLV = getLVForDecl(temp, computation);
-  // The linkage and visibility of the specialization should be
-  // consistent with the template declaration.
-  LV.mergeMaybeWithVisibility(tempLV, considerVisibility);
+  // The linkage of the specialization should be consistent with the
+  // template declaration.
+  LV.setLinkage(tempLV.getLinkage());
 
   // Merge information from the template parameters.
   LinkageInfo paramsLV =
@@ -1051,13 +1051,6 @@ LinkageComputer::getLVForClassMember(const NamedDecl *D,
     if (const auto *redeclTemp = dyn_cast<RedeclarableTemplateDecl>(temp)) {
       if (isExplicitMemberSpecialization(redeclTemp)) {
         explicitSpecSuppressor = temp->getTemplatedDecl();
-      } else if (const RedeclarableTemplateDecl *from =
-                     redeclTemp->getInstantiatedFromMemberTemplate()) {
-        // If no explicit visibility is specified yet, and this is an
-        // instantiated member of a template, look up visibility there
-        // as well.
-        LinkageInfo fromLV = from->getLinkageAndVisibility();
-        LV.mergeMaybeWithVisibility(fromLV, considerVisibility);
       }
     }
   }

clang/lib/Sema/SemaDeclAttr.cpp

@@ -5495,12 +5495,12 @@ bool Sema::CheckCallingConvAttr(const ParsedAttr &Attrs, CallingConv &CC,
 
   TargetInfo::CallingConvCheckResult A = TargetInfo::CCCR_OK;
   const TargetInfo &TI = Context.getTargetInfo();
+  auto *Aux = Context.getAuxTargetInfo();
   // CUDA functions may have host and/or device attributes which indicate
   // their targeted execution environment, therefore the calling convention
   // of functions in CUDA should be checked against the target deduced based
   // on their host/device attributes.
   if (LangOpts.CUDA) {
-    auto *Aux = Context.getAuxTargetInfo();
     assert(FD || CFT != CUDAFunctionTarget::InvalidTarget);
     auto CudaTarget = FD ? CUDA().IdentifyTarget(FD) : CFT;
     bool CheckHost = false, CheckDevice = false;
@@ -5525,6 +5525,15 @@ bool Sema::CheckCallingConvAttr(const ParsedAttr &Attrs, CallingConv &CC,
       A = HostTI->checkCallingConvention(CC);
     if (A == TargetInfo::CCCR_OK && CheckDevice && DeviceTI)
       A = DeviceTI->checkCallingConvention(CC);
+  } else if (LangOpts.SYCLIsDevice && TI.getTriple().isAMDGPU() &&
+             CC == CC_X86VectorCall) {
+    // Assuming SYCL Device AMDGPU CC_X86VectorCall functions are always to be
+    // emitted on the host. The MSVC STL has CC-based specializations so we
+    // cannot change the CC to be the default as that will cause a clash with
+    // another specialization.
+    A = TI.checkCallingConvention(CC);
+    if (Aux && A != TargetInfo::CCCR_OK)
+      A = Aux->checkCallingConvention(CC);
   } else {
     A = TI.checkCallingConvention(CC);
   }

clang/test/CodeGenCXX/visibility.cpp

@@ -1457,45 +1457,9 @@ namespace test71 {
   // CHECK-LABEL: declare hidden noundef i32 @_ZN6test713fooIiE3zedEv(
   // CHECK-LABEL: define linkonce_odr noundef i32 @_ZN6test713fooIiE3barIiEET_v(
   // CHECK-LABEL: define linkonce_odr hidden noundef i64 @_ZN6test713fooIlE3zedEv(
-  // CHECK-LABEL: define linkonce_odr hidden noundef i32 @_ZN6test713fooIlE3barIiEET_v(
+  // CHECK-LABEL: define linkonce_odr noundef i32 @_ZN6test713fooIlE3barIiEET_v(
   // CHECK-HIDDEN-LABEL: declare hidden noundef i32 @_ZN6test713fooIiE3zedEv(
   // CHECK-HIDDEN-LABEL: define linkonce_odr noundef i32 @_ZN6test713fooIiE3barIiEET_v(
   // CHECK-HIDDEN-LABEL: define linkonce_odr hidden noundef i64 @_ZN6test713fooIlE3zedEv(
   // CHECK-HIDDEN-LABEL: define linkonce_odr hidden noundef i32 @_ZN6test713fooIlE3barIiEET_v(
 }
-
-// https://github.com/llvm/llvm-project/issues/103477
-namespace test72 {
-  template <class a>
-  struct t {
-    template <int>
-    static HIDDEN void bar() {}
-  };
-
-  void test() {
-      t<char>::bar<1>();
-  }
-  // CHECK-LABEL: define linkonce_odr hidden void @_ZN6test721tIcE3barILi1EEEvv(
-  // CHECK-HIDDEN-LABEL: define linkonce_odr hidden void @_ZN6test721tIcE3barILi1EEEvv(
-}
-
-// https://github.com/llvm/llvm-project/issues/31462
-namespace test73 {
-  template <class T> struct s {
-    template <class U>
-    __attribute__((__visibility__("hidden"))) U should_not_be_exported();
-  };
-
-  template <class T> template <class U> U s<T>::should_not_be_exported() {
-    return U();
-  }
-
-  extern template struct __attribute__((__visibility__("default"))) s<int>;
-
-  int f() {
-    s<int> o;
-    return o.should_not_be_exported<int>();
-  }
-  // CHECK-LABEL: define linkonce_odr noundef i32 @_ZN6test731sIiE22should_not_be_exportedIiEET_v(
-  // CHECK-HIDDEN-LABEL: define linkonce_odr noundef i32 @_ZN6test731sIiE22should_not_be_exportedIiEET_v(
-}

clang/test/Format/lit.local.cfg

@@ -1,3 +1,4 @@
+import os
 import platform
 import lit.formats
 
@@ -27,3 +28,8 @@ config.suffixes = [
 # python implementation does, so use that for cross platform compatibility
 if platform.system() == "AIX":
     config.test_format = lit.formats.ShTest()
+
+# Create an empty .clang-format-ignore file so that tests don't get messed
+# up if one exists higher in the tree
+with open(".clang-format-ignore", 'w'):
+    pass

clang/test/SemaSYCL/Inputs/vectorcall.hpp

@@ -0,0 +1,18 @@
+
+template <typename F> struct A{};
+
+template <typename Ret, typename C, typename... Args> struct A<Ret (             C::*)(Args...) noexcept> { static constexpr int value = 0; };
+template <typename Ret, typename C, typename... Args> struct A<Ret (__vectorcall C::*)(Args...) noexcept> { static constexpr int value = 1; };
+
+template <typename F> constexpr int A_v = A<F>::value;
+
+struct B
+{
+    void f() noexcept {}
+    void __vectorcall g() noexcept {}
+};
+
+int main()
+{
+    return A_v<decltype(&B::f)> + A_v<decltype(&B::g)>;
+}

clang/test/SemaSYCL/sycl-cconv-win.cpp

@@ -0,0 +1,5 @@
+// RUN: %clang_cc1 -isystem %S/Inputs/ -fsycl-is-device -triple amdgcn-amd-hsa -aux-triple x86_64-pc-windows-msvc -fsyntax-only -verify %s
+
+// expected-no-diagnostics
+
+#include <vectorcall.hpp>

flang-rt/include/flang-rt/runtime/io-stmt.h

@@ -20,6 +20,7 @@
 #include "flang/Common/optional.h"
 #include "flang/Common/reference-wrapper.h"
 #include "flang/Common/visit.h"
+#include "flang/Runtime/freestanding-tools.h"
 #include "flang/Runtime/io-api.h"
 #include <flang/Common/variant.h>
 #include <functional>
@@ -180,8 +181,8 @@ class IoStatementState {
 
   private:
     RT_API_ATTRS void CheckForAsterisk() {
-      hasAsterisk_ =
-          at_ && at_ < limit_ && std::memchr(at_, '*', limit_ - at_) != nullptr;
+      hasAsterisk_ = at_ && at_ < limit_ &&
+          runtime::memchr(at_, '*', limit_ - at_) != nullptr;
     }
 
     ConnectionState &connection_;

flang/lib/Optimizer/CodeGen/LowerRepackArrays.cpp

@@ -357,8 +357,8 @@ class LowerRepackArraysPass
     patterns.insert<PackArrayConversion>(context);
     patterns.insert<UnpackArrayConversion>(context);
     mlir::GreedyRewriteConfig config;
-    config.setRegionSimplificationLevel(
-        mlir::GreedySimplifyRegionLevel::Disabled);
+    config.enableRegionSimplification =
+        mlir::GreedySimplifyRegionLevel::Disabled;
     (void)applyPatternsGreedily(module, std::move(patterns), config);
   }
 

flang/lib/Optimizer/HLFIR/Transforms/InlineElementals.cpp

@@ -119,8 +119,8 @@ class InlineElementalsPass
 
     mlir::GreedyRewriteConfig config;
     // Prevent the pattern driver from merging blocks.
-    config.setRegionSimplificationLevel(
-        mlir::GreedySimplifyRegionLevel::Disabled);
+    config.enableRegionSimplification =
+        mlir::GreedySimplifyRegionLevel::Disabled;
 
     mlir::RewritePatternSet patterns(context);
     patterns.insert<InlineElementalConversion>(context);

flang/lib/Optimizer/HLFIR/Transforms/InlineHLFIRAssign.cpp

@@ -135,8 +135,8 @@ class InlineHLFIRAssignPass
 
     mlir::GreedyRewriteConfig config;
     // Prevent the pattern driver from merging blocks.
-    config.setRegionSimplificationLevel(
-        mlir::GreedySimplifyRegionLevel::Disabled);
+    config.enableRegionSimplification =
+        mlir::GreedySimplifyRegionLevel::Disabled;
 
     mlir::RewritePatternSet patterns(context);
     patterns.insert<InlineHLFIRAssignConversion>(context);