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merge main into amd-staging (llvm#4256)
2 parents 94bdf57 + 95dac03 commit cdfd34a

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42 files changed

+983
-162
lines changed

‎llvm/include/llvm/CodeGen/RDFGraph.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -447,7 +447,7 @@ struct NodeAllocator {
447447
AllocatorTy MemPool;
448448
};
449449

450-
using RegisterSet = std::set<RegisterRef>;
450+
using RegisterSet = std::set<RegisterRef, RegisterRefLess>;
451451

452452
struct TargetOperandInfo {
453453
TargetOperandInfo(const TargetInstrInfo &tii) : TII(tii) {}

‎llvm/include/llvm/CodeGen/RDFRegisters.h‎

Lines changed: 28 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -199,6 +199,33 @@ struct PhysicalRegisterInfo {
199199
std::vector<AliasInfo> AliasInfos;
200200
};
201201

202+
struct RegisterRefEqualTo {
203+
constexpr RegisterRefEqualTo(const llvm::rdf::PhysicalRegisterInfo &pri)
204+
: PRI(&pri) {}
205+
206+
bool operator()(llvm::rdf::RegisterRef A, llvm::rdf::RegisterRef B) const {
207+
return PRI->equal_to(A, B);
208+
}
209+
210+
private:
211+
// Make it a pointer just in case. See comment in `RegisterRefLess` below.
212+
const llvm::rdf::PhysicalRegisterInfo *PRI;
213+
};
214+
215+
struct RegisterRefLess {
216+
constexpr RegisterRefLess(const llvm::rdf::PhysicalRegisterInfo &pri)
217+
: PRI(&pri) {}
218+
219+
bool operator()(llvm::rdf::RegisterRef A, llvm::rdf::RegisterRef B) const {
220+
return PRI->less(A, B);
221+
}
222+
223+
private:
224+
// Make it a pointer because apparently some versions of MSVC use std::swap
225+
// on the comparator object.
226+
const llvm::rdf::PhysicalRegisterInfo *PRI;
227+
};
228+
202229
struct RegisterAggr {
203230
RegisterAggr(const PhysicalRegisterInfo &pri)
204231
: Units(pri.getTRI().getNumRegUnits()), PRI(pri) {}
@@ -334,42 +361,17 @@ template <> struct hash<llvm::rdf::RegisterAggr> {
334361
}
335362
};
336363

337-
template <> struct equal_to<llvm::rdf::RegisterRef> {
338-
constexpr equal_to(const llvm::rdf::PhysicalRegisterInfo &pri) : PRI(&pri) {}
339-
340-
bool operator()(llvm::rdf::RegisterRef A, llvm::rdf::RegisterRef B) const {
341-
return PRI->equal_to(A, B);
342-
}
343-
344-
private:
345-
// Make it a pointer just in case. See comment in `less` below.
346-
const llvm::rdf::PhysicalRegisterInfo *PRI;
347-
};
348-
349364
template <> struct equal_to<llvm::rdf::RegisterAggr> {
350365
bool operator()(const llvm::rdf::RegisterAggr &A,
351366
const llvm::rdf::RegisterAggr &B) const {
352367
return A == B;
353368
}
354369
};
355370

356-
template <> struct less<llvm::rdf::RegisterRef> {
357-
constexpr less(const llvm::rdf::PhysicalRegisterInfo &pri) : PRI(&pri) {}
358-
359-
bool operator()(llvm::rdf::RegisterRef A, llvm::rdf::RegisterRef B) const {
360-
return PRI->less(A, B);
361-
}
362-
363-
private:
364-
// Make it a pointer because apparently some versions of MSVC use std::swap
365-
// on the std::less specialization.
366-
const llvm::rdf::PhysicalRegisterInfo *PRI;
367-
};
368-
369371
} // namespace std
370372

371373
namespace llvm::rdf {
372-
using RegisterSet = std::set<RegisterRef, std::less<RegisterRef>>;
374+
using RegisterSet = std::set<RegisterRef, RegisterRefLess>;
373375
} // namespace llvm::rdf
374376

375377
#endif // LLVM_CODEGEN_RDFREGISTERS_H

‎llvm/lib/CodeGen/RDFLiveness.cpp‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -652,8 +652,9 @@ void Liveness::computePhiInfo() {
652652
// defs, cache the result of subtracting these defs from a given register
653653
// ref.
654654
using RefHash = std::hash<RegisterRef>;
655-
using RefEqual = std::equal_to<RegisterRef>;
656-
using SubMap = std::unordered_map<RegisterRef, RegisterRef>;
655+
using RefEqual = RegisterRefEqualTo;
656+
using SubMap =
657+
std::unordered_map<RegisterRef, RegisterRef, RefHash, RefEqual>;
657658
std::unordered_map<RegisterAggr, SubMap> Subs;
658659
auto ClearIn = [](RegisterRef RR, const RegisterAggr &Mid, SubMap &SM) {
659660
if (Mid.empty())
@@ -868,7 +869,7 @@ void Liveness::computeLiveIns() {
868869
std::vector<RegisterRef> LV;
869870
for (const MachineBasicBlock::RegisterMaskPair &LI : B.liveins())
870871
LV.push_back(RegisterRef(LI.PhysReg, LI.LaneMask));
871-
llvm::sort(LV, std::less<RegisterRef>(PRI));
872+
llvm::sort(LV, RegisterRefLess(PRI));
872873
dbgs() << printMBBReference(B) << "\t rec = {";
873874
for (auto I : LV)
874875
dbgs() << ' ' << Print(I, DFG);
@@ -878,7 +879,7 @@ void Liveness::computeLiveIns() {
878879
LV.clear();
879880
for (RegisterRef RR : LiveMap[&B].refs())
880881
LV.push_back(RR);
881-
llvm::sort(LV, std::less<RegisterRef>(PRI));
882+
llvm::sort(LV, RegisterRefLess(PRI));
882883
dbgs() << "\tcomp = {";
883884
for (auto I : LV)
884885
dbgs() << ' ' << Print(I, DFG);

‎llvm/lib/Target/Hexagon/RDFCopy.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -108,7 +108,7 @@ bool CopyPropagation::scanBlock(MachineBasicBlock *B) {
108108
for (NodeAddr<InstrNode*> IA : BA.Addr->members(DFG)) {
109109
if (DFG.IsCode<NodeAttrs::Stmt>(IA)) {
110110
NodeAddr<StmtNode*> SA = IA;
111-
EqualityMap EM(std::less<RegisterRef>(DFG.getPRI()));
111+
EqualityMap EM(RegisterRefLess(DFG.getPRI()));
112112
if (interpretAsCopy(SA.Addr->getCode(), EM))
113113
recordCopy(SA, EM);
114114
}

‎llvm/lib/Target/Hexagon/RDFCopy.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -25,8 +25,8 @@ class MachineInstr;
2525
namespace rdf {
2626

2727
struct CopyPropagation {
28-
CopyPropagation(DataFlowGraph &dfg) : MDT(dfg.getDT()), DFG(dfg),
29-
RDefMap(std::less<RegisterRef>(DFG.getPRI())) {}
28+
CopyPropagation(DataFlowGraph &dfg)
29+
: MDT(dfg.getDT()), DFG(dfg), RDefMap(RegisterRefLess(DFG.getPRI())) {}
3030

3131
virtual ~CopyPropagation() = default;
3232

@@ -35,7 +35,7 @@ namespace rdf {
3535
bool trace() const { return Trace; }
3636
DataFlowGraph &getDFG() { return DFG; }
3737

38-
using EqualityMap = std::map<RegisterRef, RegisterRef>;
38+
using EqualityMap = std::map<RegisterRef, RegisterRef, RegisterRefLess>;
3939
virtual bool interpretAsCopy(const MachineInstr *MI, EqualityMap &EM);
4040

4141
private:
@@ -45,7 +45,7 @@ namespace rdf {
4545
bool Trace = false;
4646

4747
// map: register -> (map: stmt -> reaching def)
48-
std::map<RegisterRef,std::map<NodeId,NodeId>> RDefMap;
48+
std::map<RegisterRef, std::map<NodeId, NodeId>, RegisterRefLess> RDefMap;
4949
// map: statement -> (map: dst reg -> src reg)
5050
std::map<NodeId, EqualityMap> CopyMap;
5151
std::vector<NodeId> Copies;

‎llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp‎

Lines changed: 51 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1096,6 +1096,41 @@ static bool build2DBlockIOINTELInst(const SPIRV::IncomingCall *Call,
10961096
return true;
10971097
}
10981098

1099+
static bool buildPipeInst(const SPIRV::IncomingCall *Call, unsigned Opcode,
1100+
unsigned Scope, MachineIRBuilder &MIRBuilder,
1101+
SPIRVGlobalRegistry *GR) {
1102+
switch (Opcode) {
1103+
case SPIRV::OpCommitReadPipe:
1104+
case SPIRV::OpCommitWritePipe:
1105+
return buildOpFromWrapper(MIRBuilder, Opcode, Call, Register(0));
1106+
case SPIRV::OpGroupCommitReadPipe:
1107+
case SPIRV::OpGroupCommitWritePipe:
1108+
case SPIRV::OpGroupReserveReadPipePackets:
1109+
case SPIRV::OpGroupReserveWritePipePackets: {
1110+
Register ScopeConstReg =
1111+
MIRBuilder.buildConstant(LLT::scalar(32), Scope).getReg(0);
1112+
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
1113+
MRI->setRegClass(ScopeConstReg, &SPIRV::iIDRegClass);
1114+
MachineInstrBuilder MIB;
1115+
MIB = MIRBuilder.buildInstr(Opcode);
1116+
// Add Return register and type.
1117+
if (Opcode == SPIRV::OpGroupReserveReadPipePackets ||
1118+
Opcode == SPIRV::OpGroupReserveWritePipePackets)
1119+
MIB.addDef(Call->ReturnRegister)
1120+
.addUse(GR->getSPIRVTypeID(Call->ReturnType));
1121+
1122+
MIB.addUse(ScopeConstReg);
1123+
for (unsigned int i = 0; i < Call->Arguments.size(); ++i)
1124+
MIB.addUse(Call->Arguments[i]);
1125+
1126+
return true;
1127+
}
1128+
default:
1129+
return buildOpFromWrapper(MIRBuilder, Opcode, Call,
1130+
GR->getSPIRVTypeID(Call->ReturnType));
1131+
}
1132+
}
1133+
10991134
static unsigned getNumComponentsForDim(SPIRV::Dim::Dim dim) {
11001135
switch (dim) {
11011136
case SPIRV::Dim::DIM_1D:
@@ -2350,6 +2385,20 @@ static bool generate2DBlockIOINTELInst(const SPIRV::IncomingCall *Call,
23502385
return build2DBlockIOINTELInst(Call, Opcode, MIRBuilder, GR);
23512386
}
23522387

2388+
static bool generatePipeInst(const SPIRV::IncomingCall *Call,
2389+
MachineIRBuilder &MIRBuilder,
2390+
SPIRVGlobalRegistry *GR) {
2391+
const SPIRV::DemangledBuiltin *Builtin = Call->Builtin;
2392+
unsigned Opcode =
2393+
SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode;
2394+
2395+
unsigned Scope = SPIRV::Scope::Workgroup;
2396+
if (Builtin->Name.contains("sub_group"))
2397+
Scope = SPIRV::Scope::Subgroup;
2398+
2399+
return buildPipeInst(Call, Opcode, Scope, MIRBuilder, GR);
2400+
}
2401+
23532402
static bool buildNDRange(const SPIRV::IncomingCall *Call,
23542403
MachineIRBuilder &MIRBuilder,
23552404
SPIRVGlobalRegistry *GR) {
@@ -2948,6 +2997,8 @@ std::optional<bool> lowerBuiltin(const StringRef DemangledCall,
29482997
return generateTernaryBitwiseFunctionINTELInst(Call.get(), MIRBuilder, GR);
29492998
case SPIRV::Block2DLoadStore:
29502999
return generate2DBlockIOINTELInst(Call.get(), MIRBuilder, GR);
3000+
case SPIRV::Pipe:
3001+
return generatePipeInst(Call.get(), MIRBuilder, GR);
29513002
}
29523003
return false;
29533004
}

‎llvm/lib/Target/SPIRV/SPIRVBuiltins.td‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -69,6 +69,7 @@ def ExtendedBitOps : BuiltinGroup;
6969
def BindlessINTEL : BuiltinGroup;
7070
def TernaryBitwiseINTEL : BuiltinGroup;
7171
def Block2DLoadStore : BuiltinGroup;
72+
def Pipe : BuiltinGroup;
7273

7374
//===----------------------------------------------------------------------===//
7475
// Class defining a demangled builtin record. The information in the record
@@ -633,6 +634,29 @@ defm : DemangledNativeBuiltin<"__spirv_AtomicSMax", OpenCL_std, Atomic, 4, 4, Op
633634
defm : DemangledNativeBuiltin<"__spirv_AtomicUMin", OpenCL_std, Atomic, 4, 4, OpAtomicUMin>;
634635
defm : DemangledNativeBuiltin<"__spirv_AtomicUMax", OpenCL_std, Atomic, 4, 4, OpAtomicUMax>;
635636

637+
// Pipe Instruction
638+
defm : DemangledNativeBuiltin<"__read_pipe_2", OpenCL_std, Pipe,2, 2, OpReadPipe>;
639+
defm : DemangledNativeBuiltin<"__write_pipe_2", OpenCL_std, Pipe, 2, 2, OpWritePipe>;
640+
defm : DemangledNativeBuiltin<"__read_pipe_4", OpenCL_std, Pipe,4, 4, OpReservedReadPipe>;
641+
defm : DemangledNativeBuiltin<"__write_pipe_4", OpenCL_std, Pipe, 4, 4, OpReservedWritePipe>;
642+
defm : DemangledNativeBuiltin<"__reserve_read_pipe", OpenCL_std, Pipe, 2, 2, OpReserveReadPipePackets>;
643+
defm : DemangledNativeBuiltin<"__reserve_write_pipe", OpenCL_std, Pipe, 2, 2, OpReserveWritePipePackets>;
644+
defm : DemangledNativeBuiltin<"__commit_read_pipe", OpenCL_std, Pipe, 2, 2, OpCommitReadPipe>;
645+
defm : DemangledNativeBuiltin<"__commit_write_pipe", OpenCL_std, Pipe, 2, 2, OpCommitWritePipe>;
646+
defm : DemangledNativeBuiltin<"is_valid_reserve_id", OpenCL_std, Pipe, 1, 1, OpIsValidReserveId>;
647+
defm : DemangledNativeBuiltin<"__get_pipe_num_packets_ro", OpenCL_std, Pipe, 1, 1, OpGetNumPipePackets>;
648+
defm : DemangledNativeBuiltin<"__get_pipe_max_packets_ro", OpenCL_std, Pipe, 1, 1, OpGetMaxPipePackets>;
649+
defm : DemangledNativeBuiltin<"__get_pipe_num_packets_wo", OpenCL_std, Pipe, 1, 1, OpGetNumPipePackets>;
650+
defm : DemangledNativeBuiltin<"__get_pipe_max_packets_wo", OpenCL_std, Pipe, 1, 1, OpGetMaxPipePackets>;
651+
defm : DemangledNativeBuiltin<"__work_group_reserve_read_pipe", OpenCL_std, Pipe, 2, 2, OpGroupReserveReadPipePackets>;
652+
defm : DemangledNativeBuiltin<"__work_group_reserve_write_pipe", OpenCL_std, Pipe, 2, 2, OpGroupReserveWritePipePackets>;
653+
defm : DemangledNativeBuiltin<"__work_group_commit_read_pipe", OpenCL_std, Pipe, 2, 2, OpGroupCommitReadPipe>;
654+
defm : DemangledNativeBuiltin<"__work_group_commit_write_pipe", OpenCL_std, Pipe, 2, 2, OpGroupCommitWritePipe>;
655+
defm : DemangledNativeBuiltin<"__sub_group_reserve_read_pipe", OpenCL_std, Pipe, 2, 2, OpGroupReserveReadPipePackets>;
656+
defm : DemangledNativeBuiltin<"__sub_group_reserve_write_pipe", OpenCL_std, Pipe, 2, 2, OpGroupReserveWritePipePackets>;
657+
defm : DemangledNativeBuiltin<"__sub_group_commit_read_pipe", OpenCL_std, Pipe, 2, 2, OpGroupCommitReadPipe>;
658+
defm : DemangledNativeBuiltin<"__sub_group_commit_write_pipe", OpenCL_std, Pipe, 2, 2, OpGroupCommitWritePipe>;
659+
636660
// Barrier builtin records:
637661
defm : DemangledNativeBuiltin<"barrier", OpenCL_std, Barrier, 1, 3, OpControlBarrier>;
638662
defm : DemangledNativeBuiltin<"work_group_barrier", OpenCL_std, Barrier, 1, 3, OpControlBarrier>;

‎llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -148,7 +148,10 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
148148
SPIRV::Extension::Extension::SPV_KHR_float_controls2},
149149
{"SPV_INTEL_tensor_float32_conversion",
150150
SPIRV::Extension::Extension::SPV_INTEL_tensor_float32_conversion},
151-
{"SPV_KHR_bfloat16", SPIRV::Extension::Extension::SPV_KHR_bfloat16}};
151+
{"SPV_KHR_bfloat16", SPIRV::Extension::Extension::SPV_KHR_bfloat16},
152+
{"SPV_EXT_relaxed_printf_string_address_space",
153+
SPIRV::Extension::Extension::
154+
SPV_EXT_relaxed_printf_string_address_space}};
152155

153156
bool SPIRVExtensionsParser::parse(cl::Option &O, StringRef ArgName,
154157
StringRef ArgValue,

‎llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp‎

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1909,11 +1909,12 @@ Instruction *SPIRVEmitIntrinsics::visitInsertValueInst(InsertValueInst &I) {
19091909
B.SetInsertPoint(&I);
19101910
SmallVector<Type *, 1> Types = {I.getInsertedValueOperand()->getType()};
19111911
SmallVector<Value *> Args;
1912-
for (auto &Op : I.operands())
1913-
if (isa<UndefValue>(Op))
1914-
Args.push_back(UndefValue::get(B.getInt32Ty()));
1915-
else
1916-
Args.push_back(Op);
1912+
Value *AggregateOp = I.getAggregateOperand();
1913+
if (isa<UndefValue>(AggregateOp))
1914+
Args.push_back(UndefValue::get(B.getInt32Ty()));
1915+
else
1916+
Args.push_back(AggregateOp);
1917+
Args.push_back(I.getInsertedValueOperand());
19171918
for (auto &Op : I.indices())
19181919
Args.push_back(B.getInt32(Op));
19191920
Instruction *NewI =

‎llvm/lib/Target/SPIRV/SPIRVInstrInfo.td‎

Lines changed: 32 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -763,7 +763,38 @@ def OpGetDefaultQueue: Op<303, (outs ID:$res), (ins TYPE:$type),
763763
def OpBuildNDRange: Op<304, (outs ID:$res), (ins TYPE:$type, ID:$GWS, ID:$LWS, ID:$GWO),
764764
"$res = OpBuildNDRange $type $GWS $LWS $GWO">;
765765

766-
// TODO: 3.42.23. Pipe Instructions
766+
// 3.42.23. Pipe Instructions
767+
768+
def OpReadPipe: Op<274, (outs ID:$res), (ins TYPE:$type, ID:$Pipe, ID:$Pointer, ID:$PcktSize, ID:$PcktAlign),
769+
"$res = OpReadPipe $type $Pipe $Pointer $PcktSize $PcktAlign">;
770+
def OpWritePipe: Op<275, (outs ID:$res), (ins TYPE:$type, ID:$Pipe, ID:$Pointer, ID:$PcktSize, ID:$PcktAlign),
771+
"$res = OpWritePipe $type $Pipe $Pointer $PcktSize $PcktAlign">;
772+
def OpReservedReadPipe : Op<276, (outs ID:$res), (ins TYPE:$type, ID:$Pipe, ID:$ReserveId, ID:$Index, ID:$Pointer, ID:$PcktSize, ID:$PcktAlign),
773+
"$res = OpReservedReadPipe $type $Pipe $ReserveId $Index $Pointer $PcktSize $PcktAlign">;
774+
def OpReservedWritePipe : Op<277, (outs ID:$res), (ins TYPE:$type, ID:$Pipe, ID:$ReserveId, ID:$Index, ID:$Pointer, ID:$PcktSize, ID:$PcktAlign),
775+
"$res = OpReservedWritePipe $type $Pipe $ReserveId $Index $Pointer $PcktSize $PcktAlign">;
776+
def OpReserveReadPipePackets : Op<278, (outs ID:$res), (ins TYPE:$type, ID:$Pipe, ID:$NumPckts, ID:$PcktSize, ID:$PcktAlign),
777+
"$res = OpReserveReadPipePackets $type $Pipe $NumPckts $PcktSize $PcktAlign">;
778+
def OpReserveWritePipePackets : Op<279, (outs ID:$res), (ins TYPE:$type, ID:$Pipe, ID:$NumPckts, ID:$PcktSize, ID:$PcktAlign),
779+
"$res = OpReserveWritePipePackets $type $Pipe $NumPckts $PcktSize $PcktAlign">;
780+
def OpCommitReadPipe : Op<280, (outs), (ins ID:$Pipe, ID:$ReserveId, ID:$PcktSize, ID:$PcktAlign),
781+
"OpCommitReadPipe $Pipe $ReserveId $PcktSize $PcktAlign">;
782+
def OpCommitWritePipe : Op<281, (outs), (ins ID:$Pipe, ID:$ReserveId, ID:$PcktSize, ID:$PcktAlign),
783+
"OpCommitWritePipe $Pipe $ReserveId $PcktSize $PcktAlign">;
784+
def OpIsValidReserveId : Op<282, (outs ID:$res), (ins TYPE:$type, ID:$ReserveId),
785+
"$res = OpIsValidReserveId $type $ReserveId">;
786+
def OpGetNumPipePackets : Op<283, (outs ID:$res), (ins TYPE:$type, ID:$Pipe, ID:$PacketSize, ID:$PacketAlign),
787+
"$res = OpGetNumPipePackets $type $Pipe $PacketSize $PacketAlign">;
788+
def OpGetMaxPipePackets : Op<284, (outs ID:$res), (ins TYPE:$type, ID:$Pipe, ID:$PacketSize, ID:$PacketAlign),
789+
"$res = OpGetMaxPipePackets $type $Pipe $PacketSize $PacketAlign">;
790+
def OpGroupReserveReadPipePackets : Op<285, (outs ID:$res), (ins TYPE:$type, ID:$Scope, ID:$Pipe, ID:$NumPckts, ID:$PacketSize, ID:$PacketAlign),
791+
"$res = OpGroupReserveReadPipePackets $type $Scope $Pipe $NumPckts $PacketSize $PacketAlign">;
792+
def OpGroupReserveWritePipePackets : Op<286, (outs ID:$res), (ins TYPE:$type, ID:$Scope, ID:$Pipe, ID:$NumPckts, ID:$PacketSize, ID:$PacketAlign),
793+
"$res = OpGroupReserveWritePipePackets $type $Scope $Pipe $NumPckts $PacketSize $PacketAlign">;
794+
def OpGroupCommitReadPipe : Op<287, (outs), (ins ID:$Scope, ID:$Pipe, ID:$ReserveId, ID:$PacketSize, ID:$PacketAlign),
795+
"OpGroupCommitReadPipe $Scope $Pipe $ReserveId $PacketSize $PacketAlign">;
796+
def OpGroupCommitWritePipe : Op<288, (outs), (ins ID:$Scope, ID:$Pipe, ID:$ReserveId, ID:$PacketSize, ID:$PacketAlign),
797+
"OpGroupCommitWritePipe $Scope $Pipe $ReserveId $PacketSize $PacketAlign">;
767798

768799
// 3.42.24. Non-Uniform Instructions
769800

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