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generate instructions `dbar 0x700`, `div.w`, `div.wu`, `mod.w` and `mod.wu`
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when related target features are enabled. `llacq.w`, `screl.w`, `llacq.d` and
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`screl.d` cannot be generated yet.
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* An llc option called `-loongarch-annotate-tablejump` is added to annotate
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table jump instruction in the `.discard.tablejump_annotate` section. A typical
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user of these annotations is the `objtool` in Linux kernel.
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* The default cpu in `MCSubtargetInfo` is changed from `la464` to `generic-la64`.
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In addition, the `lsx` feature is added to `generic-la64`.
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* CFI instructions now allow register names and aliases, previously only numbers
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were allowed.
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*`RuntimeDyld` now supports LoongArch, which means that programs relying on
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`MCJIT` can now work.
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*`.balign N, 0`, `.p2align N, 0`, `.align N, 0` in code sections will now fill
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the required alignment space with a sequence of `0x0` bytes (the requested
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fill value) rather than NOPs.
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*`%ld_pcrel_20`, `%gd_pcrel_20` and `%desc_pcrel_20` operand modifiers are
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supported by assembler.
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* A machine function pass called `LoongArch Merge Base Offset` is added to merge
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the offset of address calculation into the offset field of instructions in a
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global address lowering sequence.
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* The `LoopDataPrefetch` pass can now work on LoongArch, but it is disabled by
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default due to the bad effect on Fortran benchmarks.
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* Enable alias analysis by default.
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* Avoid indirect branch jumps using the `$ra` register.
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* Other optimizations.
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Changes to the MIPS Backend
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---------------------------
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@@ -489,11 +540,19 @@ Changes to LLDB
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to be opened in the firewall (one for the `lldb-server` platform, one for gdbserver connections).
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In addition, due to this work, `lldb-server` now works on Windows in the server mode.
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-
* LLDB now supports execution of user expressions for non-trivial cases for RISC-V targets, like function calls, when some code needs to be executed on the target.
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* LLDB now supports execution of user expressions for non-trivial cases for LoongArch and RISC-V targets, like function calls, when some code needs to be executed on the target.
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* LLDB now supports optionally enabled/disabled register sets (particularly floating point registers) for RISC-V 64. This happens for targets like `RV64IMAC` or `RV64IMACV`,
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that have no floating point registers. The change is applied to native debugging and core-file usage.
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* LLDB now supports [core-file for LoongArch](https://github.com/llvm/llvm-project/pull/112296).
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* LLDB now supports [hardware breakpoint and watchpoint for LoongArch](https://github.com/llvm/llvm-project/pull/118770).
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* LLDB now supports [vector registers for LoongArch](https://github.com/llvm/llvm-project/pull/120664) when debugging a live process.
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* Incorrect floating-point register dwarf number for LoongArch is [fixed](https://github.com/llvm/llvm-project/pull/120391).
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