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[RISCV] Add tests for widening FP VP reductions. NFC
We're missing patterns for matching vfwred{u,o}sum.vs, both with VP and non-VP fpexts.
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‎llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll‎

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@@ -465,3 +465,131 @@ define float @vreduce_fmaximum_v4f32(float %start, <4 x float> %val, <4 x i1> %m
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%s = call float @llvm.vp.reduce.fmaximum.v4f32(float %start, <4 x float> %val, <4 x i1> %m, i32 %evl)
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ret float %s
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}
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define float @vpreduce_fadd_fpext_vp_nxv1f16_nxv1f32(float %s, <vscale x 1 x half> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpreduce_fadd_fpext_vp_nxv1f16_nxv1f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
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; CHECK-NEXT: vfwcvt.f.f.v v9, v8, v0.t
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; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
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; CHECK-NEXT: vfmv.s.f v8, fa0
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; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
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; CHECK-NEXT: vfredusum.vs v8, v9, v8, v0.t
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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%w = call <vscale x 1 x float> @llvm.vp.fpext(<vscale x 1 x half> %v, <vscale x 1 x i1> %m, i32 %evl)
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%r = call reassoc float @llvm.vp.reduce.fadd(float %s, <vscale x 1 x float> %w, <vscale x 1 x i1> %m, i32 %evl)
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ret float %r
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}
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define float @vpreduce_ord_fadd_fpext_vp_fpext_nxv1f16_nxv1f32(float %s, <vscale x 1 x half> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpreduce_ord_fadd_fpext_vp_fpext_nxv1f16_nxv1f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
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; CHECK-NEXT: vfwcvt.f.f.v v9, v8, v0.t
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; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
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; CHECK-NEXT: vfmv.s.f v8, fa0
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; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
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; CHECK-NEXT: vfredosum.vs v8, v9, v8, v0.t
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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%w = call <vscale x 1 x float> @llvm.vp.fpext(<vscale x 1 x half> %v, <vscale x 1 x i1> %m, i32 %evl)
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%r = call float @llvm.vp.reduce.fadd(float %s, <vscale x 1 x float> %w, <vscale x 1 x i1> %m, i32 %evl)
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ret float %r
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}
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define double @vpreduce_fadd_fpext_vp_nxv1f32_nxv1f64(double %s, <vscale x 1 x float> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpreduce_fadd_fpext_vp_nxv1f32_nxv1f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
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; CHECK-NEXT: vfwcvt.f.f.v v9, v8, v0.t
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; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
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; CHECK-NEXT: vfmv.s.f v8, fa0
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; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
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; CHECK-NEXT: vfredusum.vs v8, v9, v8, v0.t
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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%w = call <vscale x 1 x double> @llvm.vp.fpext(<vscale x 1 x float> %v, <vscale x 1 x i1> %m, i32 %evl)
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%r = call reassoc double @llvm.vp.reduce.fadd(double %s, <vscale x 1 x double> %w, <vscale x 1 x i1> %m, i32 %evl)
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ret double %r
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}
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define double @vpreduce_ord_fadd_fpext_vp_fpext_nxv1f32_nxv1f64(double %s, <vscale x 1 x float> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpreduce_ord_fadd_fpext_vp_fpext_nxv1f32_nxv1f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
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; CHECK-NEXT: vfwcvt.f.f.v v9, v8, v0.t
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; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
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; CHECK-NEXT: vfmv.s.f v8, fa0
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; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
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; CHECK-NEXT: vfredosum.vs v8, v9, v8, v0.t
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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%w = call <vscale x 1 x double> @llvm.vp.fpext(<vscale x 1 x float> %v, <vscale x 1 x i1> %m, i32 %evl)
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%r = call double @llvm.vp.reduce.fadd(double %s, <vscale x 1 x double> %w, <vscale x 1 x i1> %m, i32 %evl)
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ret double %r
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}
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define float @vpreduce_fadd_fpext_nxv1f16_nxv1f32(float %s, <vscale x 1 x half> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpreduce_fadd_fpext_nxv1f16_nxv1f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
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; CHECK-NEXT: vfwcvt.f.f.v v9, v8
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; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
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; CHECK-NEXT: vfmv.s.f v8, fa0
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; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
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; CHECK-NEXT: vfredusum.vs v8, v9, v8, v0.t
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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%w = fpext <vscale x 1 x half> %v to <vscale x 1 x float>
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%r = call reassoc float @llvm.vp.reduce.fadd(float %s, <vscale x 1 x float> %w, <vscale x 1 x i1> %m, i32 %evl)
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ret float %r
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}
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define float @vpreduce_ord_fadd_fpext_nxv1f16_nxv1f32(float %s, <vscale x 1 x half> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpreduce_ord_fadd_fpext_nxv1f16_nxv1f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
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; CHECK-NEXT: vfwcvt.f.f.v v9, v8
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; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
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; CHECK-NEXT: vfmv.s.f v8, fa0
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; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
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; CHECK-NEXT: vfredosum.vs v8, v9, v8, v0.t
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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%w = fpext <vscale x 1 x half> %v to <vscale x 1 x float>
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%r = call float @llvm.vp.reduce.fadd(float %s, <vscale x 1 x float> %w, <vscale x 1 x i1> %m, i32 %evl)
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ret float %r
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}
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define double @vpreduce_fadd_fpext_nxv1f32_nxv1f64(double %s, <vscale x 1 x float> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpreduce_fadd_fpext_nxv1f32_nxv1f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
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; CHECK-NEXT: vfwcvt.f.f.v v9, v8
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; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
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; CHECK-NEXT: vfmv.s.f v8, fa0
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; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
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; CHECK-NEXT: vfredusum.vs v8, v9, v8, v0.t
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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%w = fpext <vscale x 1 x float> %v to <vscale x 1 x double>
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%r = call reassoc double @llvm.vp.reduce.fadd(double %s, <vscale x 1 x double> %w, <vscale x 1 x i1> %m, i32 %evl)
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ret double %r
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}
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define double @vpreduce_ord_fadd_fpext_nxv1f32_nxv1f64(double %s, <vscale x 1 x float> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpreduce_ord_fadd_fpext_nxv1f32_nxv1f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
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; CHECK-NEXT: vfwcvt.f.f.v v9, v8
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; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
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; CHECK-NEXT: vfmv.s.f v8, fa0
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; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
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; CHECK-NEXT: vfredosum.vs v8, v9, v8, v0.t
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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%w = fpext <vscale x 1 x float> %v to <vscale x 1 x double>
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%r = call double @llvm.vp.reduce.fadd(double %s, <vscale x 1 x double> %w, <vscale x 1 x i1> %m, i32 %evl)
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ret double %r
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}

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