regen two lit tests

ronlieb · ronlieb · commit ef7dbb47257a · 2025-04-10T22:24:13.000-05:00
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ll
@@ -1114,19 +1114,23 @@ define amdgpu_kernel void @f64_to_v4i16(ptr addrspace(1) %out, ptr addrspace(1)
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-NEXT:    s_load_dwordx2 s[4:5], s[2:3], 0x0
 ; GCN-NEXT:    s_mov_b32 s3, 0xf000
-; GCN-NEXT:    s_mov_b32 s2, -1
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-NEXT:    v_add_f64 v[0:1], s[4:5], 1.0
-; GCN-NEXT:    v_and_b32_e32 v2, 0xffff0000, v1
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, 2, v1
-; GCN-NEXT:    v_and_b32_e32 v3, 0xffff0000, v0
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, 2, v0
-; GCN-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GCN-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GCN-NEXT:    v_or_b32_e32 v1, v2, v1
-; GCN-NEXT:    v_or_b32_e32 v0, v3, v0
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, 0x20000, v1
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, 0x20000, v0
+; GCN-NEXT:    v_readfirstlane_b32 s2, v0
+; GCN-NEXT:    v_readfirstlane_b32 s4, v1
+; GCN-NEXT:    s_and_b32 s5, s4, 0xffff0000
+; GCN-NEXT:    s_add_i32 s4, s4, 2
+; GCN-NEXT:    s_and_b32 s6, s2, 0xffff0000
+; GCN-NEXT:    s_add_i32 s2, s2, 2
+; GCN-NEXT:    s_and_b32 s4, s4, 0xffff
+; GCN-NEXT:    s_and_b32 s2, s2, 0xffff
+; GCN-NEXT:    s_or_b32 s4, s5, s4
+; GCN-NEXT:    s_or_b32 s2, s6, s2
+; GCN-NEXT:    s_add_i32 s4, s4, 0x20000
+; GCN-NEXT:    s_add_i32 s5, s2, 0x20000
+; GCN-NEXT:    s_mov_b32 s2, -1
+; GCN-NEXT:    v_mov_b32_e32 v0, s5
+; GCN-NEXT:    v_mov_b32_e32 v1, s4
 ; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GCN-NEXT:    s_endpgm
 ;
@@ -1139,14 +1143,20 @@ define amdgpu_kernel void @f64_to_v4i16(ptr addrspace(1) %out, ptr addrspace(1)
 ; VI-NEXT:    v_mov_b32_e32 v3, s1
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    v_add_f64 v[0:1], s[2:3], 1.0
-; VI-NEXT:    v_and_b32_e32 v4, 0xffff0000, v0
-; VI-NEXT:    v_add_u32_e32 v0, vcc, 2, v0
-; VI-NEXT:    v_and_b32_e32 v5, 0xffff0000, v1
-; VI-NEXT:    v_add_u32_e32 v1, vcc, 2, v1
-; VI-NEXT:    v_or_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-; VI-NEXT:    v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-; VI-NEXT:    v_add_u32_e32 v1, vcc, 0x20000, v1
-; VI-NEXT:    v_add_u32_e32 v0, vcc, 0x20000, v0
+; VI-NEXT:    v_readfirstlane_b32 s0, v1
+; VI-NEXT:    v_readfirstlane_b32 s1, v0
+; VI-NEXT:    s_and_b32 s2, s1, 0xffff0000
+; VI-NEXT:    s_add_i32 s1, s1, 2
+; VI-NEXT:    s_and_b32 s3, s0, 0xffff0000
+; VI-NEXT:    s_add_i32 s0, s0, 2
+; VI-NEXT:    s_and_b32 s0, s0, 0xffff
+; VI-NEXT:    s_and_b32 s1, s1, 0xffff
+; VI-NEXT:    s_or_b32 s0, s3, s0
+; VI-NEXT:    s_or_b32 s1, s2, s1
+; VI-NEXT:    s_add_i32 s0, s0, 0x20000
+; VI-NEXT:    s_add_i32 s1, s1, 0x20000
+; VI-NEXT:    v_mov_b32_e32 v0, s1
+; VI-NEXT:    v_mov_b32_e32 v1, s0
 ; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
 ; VI-NEXT:    s_endpgm
 ;
diff --git a/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-debug-info-multi-entry.ll b/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs-debug-info-multi-entry.ll
@@ -45,151 +45,151 @@ define amdgpu_kernel void @preload_block_count_x(ptr addrspace(1) inreg noundef
 ; GFX942-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX942-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX942-NEXT:    v_fmamk_f32 v0, v1, 0xcf800000, v0
-; GFX942-NEXT:    v_cvt_u32_f32_e32 v4, v1
-; GFX942-NEXT:    v_cvt_u32_f32_e32 v5, v0
-; GFX942-NEXT:    v_mul_lo_u32 v0, s1, v4
-; GFX942-NEXT:    v_mul_hi_u32 v2, s1, v5
-; GFX942-NEXT:    v_mul_lo_u32 v1, s3, v5
-; GFX942-NEXT:    v_add_u32_e32 v0, v2, v0
-; GFX942-NEXT:    v_mul_lo_u32 v6, s1, v5
-; GFX942-NEXT:    v_add_u32_e32 v7, v0, v1
-; GFX942-NEXT:    v_mul_hi_u32 v3, v5, v7
-; GFX942-NEXT:    v_mul_lo_u32 v2, v5, v7
-; GFX942-NEXT:    v_mul_hi_u32 v0, v5, v6
-; GFX942-NEXT:    v_mov_b32_e32 v1, 0
-; GFX942-NEXT:    v_lshl_add_u64 v[2:3], v[0:1], 0, v[2:3]
-; GFX942-NEXT:    v_mul_hi_u32 v0, v4, v6
-; GFX942-NEXT:    v_mul_lo_u32 v6, v4, v6
-; GFX942-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v6
-; GFX942-NEXT:    v_mul_hi_u32 v8, v4, v7
-; GFX942-NEXT:    s_nop 0
-; GFX942-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
-; GFX942-NEXT:    v_mul_lo_u32 v2, v4, v7
-; GFX942-NEXT:    s_nop 0
-; GFX942-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v8, vcc
-; GFX942-NEXT:    v_lshl_add_u64 v[2:3], v[0:1], 0, v[2:3]
-; GFX942-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v2
-; GFX942-NEXT:    v_mul_hi_u32 v2, s1, v5
-; GFX942-NEXT:    s_nop 0
-; GFX942-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v3, vcc
-; GFX942-NEXT:    v_mul_lo_u32 v0, s1, v4
-; GFX942-NEXT:    v_add_u32_e32 v0, v2, v0
-; GFX942-NEXT:    v_mul_lo_u32 v2, s3, v5
-; GFX942-NEXT:    v_add_u32_e32 v6, v0, v2
-; GFX942-NEXT:    v_mul_lo_u32 v0, s1, v5
-; GFX942-NEXT:    v_mul_hi_u32 v8, v4, v0
-; GFX942-NEXT:    v_mul_lo_u32 v9, v4, v0
-; GFX942-NEXT:    v_mul_hi_u32 v3, v5, v6
-; GFX942-NEXT:    v_mul_lo_u32 v2, v5, v6
-; GFX942-NEXT:    v_mul_hi_u32 v0, v5, v0
-; GFX942-NEXT:    v_lshl_add_u64 v[2:3], v[0:1], 0, v[2:3]
-; GFX942-NEXT:    v_add_co_u32_e32 v0, vcc, v2, v9
-; GFX942-NEXT:    v_mul_hi_u32 v7, v4, v6
-; GFX942-NEXT:    s_nop 0
-; GFX942-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v8, vcc
-; GFX942-NEXT:    v_mul_lo_u32 v2, v4, v6
-; GFX942-NEXT:    s_nop 0
-; GFX942-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v7, vcc
-; GFX942-NEXT:    v_lshl_add_u64 v[2:3], v[0:1], 0, v[2:3]
-; GFX942-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v2
-; GFX942-NEXT:    v_mul_hi_u32 v0, s6, v5
-; GFX942-NEXT:    s_nop 0
-; GFX942-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v3, vcc
-; GFX942-NEXT:    v_mul_hi_u32 v3, s6, v4
-; GFX942-NEXT:    v_mul_lo_u32 v2, s6, v4
-; GFX942-NEXT:    v_lshl_add_u64 v[2:3], v[0:1], 0, v[2:3]
-; GFX942-NEXT:    v_mul_hi_u32 v0, s7, v5
-; GFX942-NEXT:    v_mul_lo_u32 v5, s7, v5
-; GFX942-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v5
-; GFX942-NEXT:    v_mul_hi_u32 v6, s7, v4
-; GFX942-NEXT:    s_nop 0
-; GFX942-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
-; GFX942-NEXT:    v_mul_lo_u32 v2, s7, v4
-; GFX942-NEXT:    s_nop 0
-; GFX942-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v6, vcc
-; GFX942-NEXT:    v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3]
-; GFX942-NEXT:    v_mul_lo_u32 v2, s12, v1
-; GFX942-NEXT:    v_mul_hi_u32 v3, s12, v0
-; GFX942-NEXT:    v_add_u32_e32 v2, v3, v2
-; GFX942-NEXT:    v_mul_lo_u32 v3, s13, v0
-; GFX942-NEXT:    v_add_u32_e32 v6, v2, v3
-; GFX942-NEXT:    v_mul_lo_u32 v3, s12, v0
-; GFX942-NEXT:    v_sub_u32_e32 v2, s7, v6
-; GFX942-NEXT:    v_mov_b32_e32 v4, s13
-; GFX942-NEXT:    v_sub_co_u32_e32 v7, vcc, s6, v3
-; GFX942-NEXT:    s_nop 1
-; GFX942-NEXT:    v_subb_co_u32_e64 v2, s[8:9], v2, v4, vcc
-; GFX942-NEXT:    v_subrev_co_u32_e64 v3, s[8:9], s12, v7
-; GFX942-NEXT:    s_nop 1
-; GFX942-NEXT:    v_subbrev_co_u32_e64 v2, s[8:9], 0, v2, s[8:9]
-; GFX942-NEXT:    v_cmp_le_u32_e64 s[8:9], s13, v2
-; GFX942-NEXT:    s_nop 1
-; GFX942-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[8:9]
-; GFX942-NEXT:    v_cmp_le_u32_e64 s[8:9], s12, v3
-; GFX942-NEXT:    s_nop 1
-; GFX942-NEXT:    v_cndmask_b32_e64 v3, 0, -1, s[8:9]
-; GFX942-NEXT:    v_cmp_eq_u32_e64 s[8:9], s13, v2
-; GFX942-NEXT:    s_nop 1
-; GFX942-NEXT:    v_cndmask_b32_e64 v8, v4, v3, s[8:9]
-; GFX942-NEXT:    v_lshl_add_u64 v[2:3], v[0:1], 0, 1
-; GFX942-NEXT:    v_lshl_add_u64 v[4:5], v[0:1], 0, 2
-; GFX942-NEXT:    v_cmp_ne_u32_e64 s[8:9], 0, v8
-; GFX942-NEXT:    s_nop 1
-; GFX942-NEXT:    v_cndmask_b32_e64 v2, v2, v4, s[8:9]
-; GFX942-NEXT:    v_mov_b32_e32 v4, s7
-; GFX942-NEXT:    v_subb_co_u32_e32 v4, vcc, v4, v6, vcc
-; GFX942-NEXT:    v_cmp_le_u32_e32 vcc, s13, v4
-; GFX942-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s[8:9]
-; GFX942-NEXT:    s_nop 0
-; GFX942-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
-; GFX942-NEXT:    v_cmp_le_u32_e32 vcc, s12, v7
-; GFX942-NEXT:    s_nop 1
-; GFX942-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
-; GFX942-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v4
-; GFX942-NEXT:    s_nop 1
-; GFX942-NEXT:    v_cndmask_b32_e32 v4, v5, v6, vcc
-; GFX942-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
-; GFX942-NEXT:    s_nop 1
-; GFX942-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX942-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX942-NEXT:    v_cvt_u32_f32_e32 v1, v1
+; GFX942-NEXT:    v_cvt_u32_f32_e32 v0, v0
+; GFX942-NEXT:    v_readfirstlane_b32 s5, v1
+; GFX942-NEXT:    v_readfirstlane_b32 s8, v0
+; GFX942-NEXT:    s_mul_i32 s9, s1, s5
+; GFX942-NEXT:    s_mul_hi_u32 s15, s1, s8
+; GFX942-NEXT:    s_mul_i32 s14, s3, s8
+; GFX942-NEXT:    s_add_i32 s9, s15, s9
+; GFX942-NEXT:    s_add_i32 s9, s9, s14
+; GFX942-NEXT:    s_mul_i32 s16, s1, s8
+; GFX942-NEXT:    s_mul_hi_u32 s14, s8, s9
+; GFX942-NEXT:    s_mul_i32 s15, s8, s9
+; GFX942-NEXT:    s_mul_hi_u32 s8, s8, s16
+; GFX942-NEXT:    s_add_u32 s8, s8, s15
+; GFX942-NEXT:    s_addc_u32 s14, 0, s14
+; GFX942-NEXT:    s_mul_hi_u32 s17, s5, s16
+; GFX942-NEXT:    s_mul_i32 s16, s5, s16
+; GFX942-NEXT:    s_add_u32 s8, s8, s16
+; GFX942-NEXT:    s_mul_hi_u32 s15, s5, s9
+; GFX942-NEXT:    s_addc_u32 s8, s14, s17
+; GFX942-NEXT:    s_addc_u32 s14, s15, 0
+; GFX942-NEXT:    s_mul_i32 s9, s5, s9
+; GFX942-NEXT:    s_add_u32 s8, s8, s9
+; GFX942-NEXT:    s_addc_u32 s9, 0, s14
+; GFX942-NEXT:    v_add_co_u32_e32 v0, vcc, s8, v0
+; GFX942-NEXT:    s_cmp_lg_u64 vcc, 0
+; GFX942-NEXT:    s_addc_u32 s5, s5, s9
+; GFX942-NEXT:    v_readfirstlane_b32 s9, v0
+; GFX942-NEXT:    s_mul_i32 s8, s1, s5
+; GFX942-NEXT:    s_mul_hi_u32 s14, s1, s9
+; GFX942-NEXT:    s_add_i32 s8, s14, s8
+; GFX942-NEXT:    s_mul_i32 s3, s3, s9
+; GFX942-NEXT:    s_add_i32 s8, s8, s3
+; GFX942-NEXT:    s_mul_i32 s1, s1, s9
+; GFX942-NEXT:    s_mul_hi_u32 s14, s5, s1
+; GFX942-NEXT:    s_mul_i32 s15, s5, s1
+; GFX942-NEXT:    s_mul_i32 s17, s9, s8
+; GFX942-NEXT:    s_mul_hi_u32 s1, s9, s1
+; GFX942-NEXT:    s_mul_hi_u32 s16, s9, s8
+; GFX942-NEXT:    s_add_u32 s1, s1, s17
+; GFX942-NEXT:    s_addc_u32 s9, 0, s16
+; GFX942-NEXT:    s_add_u32 s1, s1, s15
+; GFX942-NEXT:    s_mul_hi_u32 s3, s5, s8
+; GFX942-NEXT:    s_addc_u32 s1, s9, s14
+; GFX942-NEXT:    s_addc_u32 s3, s3, 0
+; GFX942-NEXT:    s_mul_i32 s8, s5, s8
+; GFX942-NEXT:    s_add_u32 s1, s1, s8
+; GFX942-NEXT:    s_addc_u32 s3, 0, s3
+; GFX942-NEXT:    v_add_co_u32_e32 v0, vcc, s1, v0
+; GFX942-NEXT:    s_cmp_lg_u64 vcc, 0
+; GFX942-NEXT:    s_addc_u32 s1, s5, s3
+; GFX942-NEXT:    v_readfirstlane_b32 s8, v0
+; GFX942-NEXT:    s_mul_i32 s5, s6, s1
+; GFX942-NEXT:    s_mul_hi_u32 s9, s6, s8
+; GFX942-NEXT:    s_mul_hi_u32 s3, s6, s1
+; GFX942-NEXT:    s_add_u32 s5, s9, s5
+; GFX942-NEXT:    s_addc_u32 s3, 0, s3
+; GFX942-NEXT:    s_mul_hi_u32 s14, s7, s8
+; GFX942-NEXT:    s_mul_i32 s8, s7, s8
+; GFX942-NEXT:    s_add_u32 s5, s5, s8
+; GFX942-NEXT:    s_mul_hi_u32 s9, s7, s1
+; GFX942-NEXT:    s_addc_u32 s3, s3, s14
+; GFX942-NEXT:    s_addc_u32 s5, s9, 0
+; GFX942-NEXT:    s_mul_i32 s1, s7, s1
+; GFX942-NEXT:    s_add_u32 s1, s3, s1
+; GFX942-NEXT:    s_addc_u32 s3, 0, s5
+; GFX942-NEXT:    s_mul_i32 s5, s12, s3
+; GFX942-NEXT:    s_mul_hi_u32 s8, s12, s1
+; GFX942-NEXT:    s_add_i32 s5, s8, s5
+; GFX942-NEXT:    s_mul_i32 s8, s13, s1
+; GFX942-NEXT:    s_mul_i32 s9, s12, s1
+; GFX942-NEXT:    s_add_i32 s5, s5, s8
+; GFX942-NEXT:    v_mov_b32_e32 v0, s9
+; GFX942-NEXT:    s_sub_i32 s8, s7, s5
+; GFX942-NEXT:    v_sub_co_u32_e32 v0, vcc, s6, v0
+; GFX942-NEXT:    s_cmp_lg_u64 vcc, 0
+; GFX942-NEXT:    s_subb_u32 s14, s8, s13
+; GFX942-NEXT:    v_subrev_co_u32_e64 v1, s[8:9], s12, v0
+; GFX942-NEXT:    s_cmp_lg_u64 s[8:9], 0
+; GFX942-NEXT:    s_subb_u32 s8, s14, 0
+; GFX942-NEXT:    s_cmp_ge_u32 s8, s13
+; GFX942-NEXT:    v_readfirstlane_b32 s14, v1
+; GFX942-NEXT:    s_cselect_b32 s9, -1, 0
+; GFX942-NEXT:    s_cmp_ge_u32 s14, s12
+; GFX942-NEXT:    s_cselect_b32 s14, -1, 0
+; GFX942-NEXT:    s_cmp_eq_u32 s8, s13
+; GFX942-NEXT:    s_cselect_b32 s8, s14, s9
+; GFX942-NEXT:    s_add_u32 s9, s1, 1
+; GFX942-NEXT:    s_addc_u32 s14, s3, 0
+; GFX942-NEXT:    s_add_u32 s15, s1, 2
+; GFX942-NEXT:    s_addc_u32 s16, s3, 0
+; GFX942-NEXT:    s_cmp_lg_u32 s8, 0
+; GFX942-NEXT:    s_cselect_b32 s8, s15, s9
+; GFX942-NEXT:    s_cselect_b32 s9, s16, s14
+; GFX942-NEXT:    s_cmp_lg_u64 vcc, 0
+; GFX942-NEXT:    s_subb_u32 s5, s7, s5
+; GFX942-NEXT:    s_cmp_ge_u32 s5, s13
+; GFX942-NEXT:    v_readfirstlane_b32 s15, v0
+; GFX942-NEXT:    s_cselect_b32 s14, -1, 0
+; GFX942-NEXT:    s_cmp_ge_u32 s15, s12
+; GFX942-NEXT:    s_cselect_b32 s15, -1, 0
+; GFX942-NEXT:    s_cmp_eq_u32 s5, s13
+; GFX942-NEXT:    s_cselect_b32 s5, s15, s14
+; GFX942-NEXT:    s_cmp_lg_u32 s5, 0
+; GFX942-NEXT:    s_cselect_b32 s9, s9, s3
+; GFX942-NEXT:    s_cselect_b32 s8, s8, s1
 ; GFX942-NEXT:    s_cbranch_execnz .LBB0_3
 ; GFX942-NEXT:  .LBB0_2:
 ; GFX942-NEXT:    v_cvt_f32_u32_e32 v0, s12
 ; GFX942-NEXT:    s_sub_i32 s1, 0, s12
+; GFX942-NEXT:    s_mov_b32 s9, 0
 ; GFX942-NEXT:    v_rcp_iflag_f32_e32 v0, v0
 ; GFX942-NEXT:    s_nop 0
 ; GFX942-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
 ; GFX942-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GFX942-NEXT:    v_mul_lo_u32 v1, s1, v0
-; GFX942-NEXT:    v_mul_hi_u32 v1, v0, v1
-; GFX942-NEXT:    v_add_u32_e32 v0, v0, v1
-; GFX942-NEXT:    v_mul_hi_u32 v0, s6, v0
-; GFX942-NEXT:    v_mul_lo_u32 v2, v0, s12
-; GFX942-NEXT:    v_sub_u32_e32 v2, s6, v2
-; GFX942-NEXT:    v_add_u32_e32 v1, 1, v0
-; GFX942-NEXT:    v_subrev_u32_e32 v3, s12, v2
-; GFX942-NEXT:    v_cmp_le_u32_e32 vcc, s12, v2
-; GFX942-NEXT:    s_nop 1
-; GFX942-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
-; GFX942-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX942-NEXT:    v_add_u32_e32 v1, 1, v0
-; GFX942-NEXT:    v_cmp_le_u32_e32 vcc, s12, v2
-; GFX942-NEXT:    s_nop 1
-; GFX942-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX942-NEXT:    v_mov_b32_e32 v1, 0
+; GFX942-NEXT:    s_nop 0
+; GFX942-NEXT:    v_readfirstlane_b32 s3, v0
+; GFX942-NEXT:    s_mul_i32 s1, s1, s3
+; GFX942-NEXT:    s_mul_hi_u32 s1, s3, s1
+; GFX942-NEXT:    s_add_i32 s3, s3, s1
+; GFX942-NEXT:    s_mul_hi_u32 s1, s6, s3
+; GFX942-NEXT:    s_mul_i32 s5, s1, s12
+; GFX942-NEXT:    s_sub_i32 s5, s6, s5
+; GFX942-NEXT:    s_add_i32 s3, s1, 1
+; GFX942-NEXT:    s_sub_i32 s8, s5, s12
+; GFX942-NEXT:    s_cmp_ge_u32 s5, s12
+; GFX942-NEXT:    s_cselect_b32 s1, s3, s1
+; GFX942-NEXT:    s_cselect_b32 s5, s8, s5
+; GFX942-NEXT:    s_add_i32 s3, s1, 1
+; GFX942-NEXT:    s_cmp_ge_u32 s5, s12
+; GFX942-NEXT:    s_cselect_b32 s8, s3, s1
 ; GFX942-NEXT:  .LBB0_3:
-; GFX942-NEXT:    v_lshl_add_u64 v[0:1], v[0:1], 0, 15
 ; GFX942-NEXT:    s_ashr_i32 s1, s0, 31
-; GFX942-NEXT:    v_and_b32_e32 v0, -16, v0
-; GFX942-NEXT:    v_mul_lo_u32 v2, v0, s1
-; GFX942-NEXT:    v_mul_hi_u32 v3, v0, s0
-; GFX942-NEXT:    v_add_u32_e32 v2, v3, v2
-; GFX942-NEXT:    v_mul_lo_u32 v1, v1, s0
-; GFX942-NEXT:    v_add_u32_e32 v1, v2, v1
-; GFX942-NEXT:    v_mul_lo_u32 v2, v0, s0
-; GFX942-NEXT:    v_cvt_f64_i32_e32 v[0:1], v1
+; GFX942-NEXT:    s_add_u32 s3, s8, 15
+; GFX942-NEXT:    s_addc_u32 s5, s9, 0
+; GFX942-NEXT:    s_and_b32 s3, s3, -16
+; GFX942-NEXT:    s_mul_i32 s1, s3, s1
+; GFX942-NEXT:    s_mul_hi_u32 s8, s3, s0
+; GFX942-NEXT:    s_add_i32 s1, s8, s1
+; GFX942-NEXT:    s_mul_i32 s5, s5, s0
+; GFX942-NEXT:    s_add_i32 s1, s1, s5
+; GFX942-NEXT:    s_mul_i32 s3, s3, s0
+; GFX942-NEXT:    v_cvt_f64_i32_e32 v[0:1], s1
 ; GFX942-NEXT:    v_ldexp_f64 v[0:1], v[0:1], 32
-; GFX942-NEXT:    v_cvt_f64_u32_e32 v[2:3], v2
+; GFX942-NEXT:    v_cvt_f64_u32_e32 v[2:3], s3
 ; GFX942-NEXT:    v_add_f64 v[0:1], v[0:1], v[2:3]
 ; GFX942-NEXT:    v_cvt_f64_u32_e32 v[2:3], s7
 ; GFX942-NEXT:    v_ldexp_f64 v[2:3], v[2:3], 32
@@ -215,7 +215,7 @@ define amdgpu_kernel void @preload_block_count_x(ptr addrspace(1) inreg noundef
 ; GFX942-NEXT:  .LBB0_4:
 ; GFX942-NEXT:  .Ltmp4:
 ; GFX942-NEXT:    ;DEBUG_VALUE: test:var <- [DW_OP_LLVM_poisoned] $sgpr2_sgpr3
-; GFX942-NEXT:    ; implicit-def: $vgpr0_vgpr1
+; GFX942-NEXT:    ; implicit-def: $sgpr8_sgpr9
 ; GFX942-NEXT:    s_branch .LBB0_2
 ; GFX942-NEXT:  .Ltmp5:
 entry:
