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davemgreendavemgreen
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[AArch64][GlobalISel] Update and regenerate some vecreduce and other tests. NFC
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-1142
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-1142
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‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-add.mir

Lines changed: 57 additions & 55 deletions
Original file line numberDiff line numberDiff line change
@@ -6,15 +6,15 @@ tracksRegLiveness: true
66
body: |
77
bb.1:
88
liveins: $x0
9-
109
; CHECK-LABEL: name: add_v16s8
1110
; CHECK: liveins: $x0
12-
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
13-
; CHECK: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>))
14-
; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s8) = G_VECREDUCE_ADD [[LOAD]](<16 x s8>)
15-
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[VECREDUCE_ADD]](s8)
16-
; CHECK: $w0 = COPY [[ANYEXT]](s32)
17-
; CHECK: RET_ReallyLR implicit $w0
11+
; CHECK-NEXT: {{ $}}
12+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
13+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>))
14+
; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s8) = G_VECREDUCE_ADD [[LOAD]](<16 x s8>)
15+
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[VECREDUCE_ADD]](s8)
16+
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
17+
; CHECK-NEXT: RET_ReallyLR implicit $w0
1818
%0:_(p0) = COPY $x0
1919
%1:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>))
2020
%2:_(s8) = G_VECREDUCE_ADD %1(<16 x s8>)
@@ -29,15 +29,15 @@ tracksRegLiveness: true
2929
body: |
3030
bb.1:
3131
liveins: $x0
32-
3332
; CHECK-LABEL: name: add_v8s16
3433
; CHECK: liveins: $x0
35-
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
36-
; CHECK: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>))
37-
; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s16) = G_VECREDUCE_ADD [[LOAD]](<8 x s16>)
38-
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[VECREDUCE_ADD]](s16)
39-
; CHECK: $w0 = COPY [[ANYEXT]](s32)
40-
; CHECK: RET_ReallyLR implicit $w0
34+
; CHECK-NEXT: {{ $}}
35+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
36+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>))
37+
; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s16) = G_VECREDUCE_ADD [[LOAD]](<8 x s16>)
38+
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[VECREDUCE_ADD]](s16)
39+
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
40+
; CHECK-NEXT: RET_ReallyLR implicit $w0
4141
%0:_(p0) = COPY $x0
4242
%1:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>))
4343
%2:_(s16) = G_VECREDUCE_ADD %1(<8 x s16>)
@@ -52,14 +52,14 @@ tracksRegLiveness: true
5252
body: |
5353
bb.1:
5454
liveins: $x0
55-
5655
; CHECK-LABEL: name: add_v4s32
5756
; CHECK: liveins: $x0
58-
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
59-
; CHECK: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>))
60-
; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s32) = G_VECREDUCE_ADD [[LOAD]](<4 x s32>)
61-
; CHECK: $w0 = COPY [[VECREDUCE_ADD]](s32)
62-
; CHECK: RET_ReallyLR implicit $w0
57+
; CHECK-NEXT: {{ $}}
58+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
59+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>))
60+
; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s32) = G_VECREDUCE_ADD [[LOAD]](<4 x s32>)
61+
; CHECK-NEXT: $w0 = COPY [[VECREDUCE_ADD]](s32)
62+
; CHECK-NEXT: RET_ReallyLR implicit $w0
6363
%0:_(p0) = COPY $x0
6464
%1:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>))
6565
%2:_(s32) = G_VECREDUCE_ADD %1(<4 x s32>)
@@ -73,14 +73,14 @@ tracksRegLiveness: true
7373
body: |
7474
bb.1:
7575
liveins: $x0
76-
7776
; CHECK-LABEL: name: add_v2s64
7877
; CHECK: liveins: $x0
79-
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
80-
; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>))
81-
; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[LOAD]](<2 x s64>)
82-
; CHECK: $x0 = COPY [[VECREDUCE_ADD]](s64)
83-
; CHECK: RET_ReallyLR implicit $x0
78+
; CHECK-NEXT: {{ $}}
79+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
80+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>))
81+
; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[LOAD]](<2 x s64>)
82+
; CHECK-NEXT: $x0 = COPY [[VECREDUCE_ADD]](s64)
83+
; CHECK-NEXT: RET_ReallyLR implicit $x0
8484
%0:_(p0) = COPY $x0
8585
%1:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>))
8686
%2:_(s64) = G_VECREDUCE_ADD %1(<2 x s64>)
@@ -94,14 +94,14 @@ tracksRegLiveness: true
9494
body: |
9595
bb.1:
9696
liveins: $x0
97-
9897
; CHECK-LABEL: name: add_v2s32
9998
; CHECK: liveins: $x0
100-
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
101-
; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<2 x s32>))
102-
; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s32) = G_VECREDUCE_ADD [[LOAD]](<2 x s32>)
103-
; CHECK: $w0 = COPY [[VECREDUCE_ADD]](s32)
104-
; CHECK: RET_ReallyLR implicit $w0
99+
; CHECK-NEXT: {{ $}}
100+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
101+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<2 x s32>))
102+
; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s32) = G_VECREDUCE_ADD [[LOAD]](<2 x s32>)
103+
; CHECK-NEXT: $w0 = COPY [[VECREDUCE_ADD]](s32)
104+
; CHECK-NEXT: RET_ReallyLR implicit $w0
105105
%0:_(p0) = COPY $x0
106106
%1:_(<2 x s32>) = G_LOAD %0(p0) :: (load (<2 x s32>))
107107
%2:_(s32) = G_VECREDUCE_ADD %1(<2 x s32>)
@@ -111,24 +111,25 @@ body: |
111111
...
112112
---
113113
name: test_v8i64
114+
# This is a power-of-2 legalization, so use a tree reduction.
114115
alignment: 4
115116
tracksRegLiveness: true
116117
body: |
117118
bb.1:
118119
liveins: $q0, $q1, $q2, $q3
119-
; This is a power-of-2 legalization, so use a tree reduction.
120120
; CHECK-LABEL: name: test_v8i64
121121
; CHECK: liveins: $q0, $q1, $q2, $q3
122-
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
123-
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
124-
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
125-
; CHECK: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $q3
126-
; CHECK: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY]], [[COPY1]]
127-
; CHECK: [[ADD1:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY2]], [[COPY3]]
128-
; CHECK: [[ADD2:%[0-9]+]]:_(<2 x s64>) = G_ADD [[ADD]], [[ADD1]]
129-
; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[ADD2]](<2 x s64>)
130-
; CHECK: $x0 = COPY [[VECREDUCE_ADD]](s64)
131-
; CHECK: RET_ReallyLR implicit $x0
122+
; CHECK-NEXT: {{ $}}
123+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
124+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
125+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
126+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $q3
127+
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY]], [[COPY1]]
128+
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY2]], [[COPY3]]
129+
; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(<2 x s64>) = G_ADD [[ADD]], [[ADD1]]
130+
; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[ADD2]](<2 x s64>)
131+
; CHECK-NEXT: $x0 = COPY [[VECREDUCE_ADD]](s64)
132+
; CHECK-NEXT: RET_ReallyLR implicit $x0
132133
%0:_(<2 x s64>) = COPY $q0
133134
%1:_(<2 x s64>) = COPY $q1
134135
%2:_(<2 x s64>) = COPY $q2
@@ -143,25 +144,26 @@ body: |
143144
...
144145
---
145146
name: test_v6i64
147+
# This is a non-power-of-2 legalization, generate multiple vector reductions
148+
# and combine them with scalar ops.
146149
alignment: 4
147150
tracksRegLiveness: true
148151
body: |
149152
bb.1:
150153
liveins: $q0, $q1, $q2, $q3
151-
; This is a non-power-of-2 legalization, generate multiple vector reductions
152-
; and combine them with scalar ops.
153154
; CHECK-LABEL: name: test_v6i64
154155
; CHECK: liveins: $q0, $q1, $q2, $q3
155-
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
156-
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
157-
; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
158-
; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[COPY]](<2 x s64>)
159-
; CHECK: [[VECREDUCE_ADD1:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[COPY1]](<2 x s64>)
160-
; CHECK: [[VECREDUCE_ADD2:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[COPY2]](<2 x s64>)
161-
; CHECK: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[VECREDUCE_ADD]], [[VECREDUCE_ADD1]]
162-
; CHECK: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ADD]], [[VECREDUCE_ADD2]]
163-
; CHECK: $x0 = COPY [[ADD1]](s64)
164-
; CHECK: RET_ReallyLR implicit $x0
156+
; CHECK-NEXT: {{ $}}
157+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
158+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
159+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
160+
; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[COPY]](<2 x s64>)
161+
; CHECK-NEXT: [[VECREDUCE_ADD1:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[COPY1]](<2 x s64>)
162+
; CHECK-NEXT: [[VECREDUCE_ADD2:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[COPY2]](<2 x s64>)
163+
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[VECREDUCE_ADD]], [[VECREDUCE_ADD1]]
164+
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ADD]], [[VECREDUCE_ADD2]]
165+
; CHECK-NEXT: $x0 = COPY [[ADD1]](s64)
166+
; CHECK-NEXT: RET_ReallyLR implicit $x0
165167
%0:_(<2 x s64>) = COPY $q0
166168
%1:_(<2 x s64>) = COPY $q1
167169
%2:_(<2 x s64>) = COPY $q2

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