CP upstream llvm#157927 (llvm#4406)

kzhuravl · Shoreshen · web-flow · commit f8730b5a37a0 · 2025-10-10T14:37:40.000-04:00
Co-authored-by: shore &lt;372660931@qq.com&gt;
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -3193,7 +3193,7 @@ bool SITargetLowering::CanLowerReturn(
 
   // We must use the stack if return would require unavailable registers.
   unsigned MaxNumVGPRs = Subtarget->getMaxNumVGPRs(MF);
-  unsigned TotalNumVGPRs = AMDGPU::VGPR_32RegClass.getNumRegs();
+  unsigned TotalNumVGPRs = Subtarget->getAddressableNumArchVGPRs();
   for (unsigned i = MaxNumVGPRs; i < TotalNumVGPRs; ++i)
     if (CCInfo.isAllocated(AMDGPU::VGPR_32RegClass.getRegister(i)))
       return false;
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
@@ -102,7 +102,7 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const Function &F,
                                MaxKernArgAlign);
 
     if (ST.hasGFX90AInsts() &&
-        ST.getMaxNumVGPRs(F) <= AMDGPU::VGPR_32RegClass.getNumRegs() &&
+        ST.getMaxNumVGPRs(F) <= ST.getAddressableNumArchVGPRs() &&
         !mayUseAGPRs(F))
       MayNeedAGPRs = false; // We will select all MAI with VGPR operands.
   }

Original file line number	Diff line number	Diff line change
`@@ -102,7 +102,7 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const Function &F,`
`102`	`102`	`MaxKernArgAlign);`
`103`	`103`
`104`	`104`	`if (ST.hasGFX90AInsts() &&`
`105`		`- ST.getMaxNumVGPRs(F) <= AMDGPU::VGPR_32RegClass.getNumRegs() &&`
	`105`	`+ ST.getMaxNumVGPRs(F) <= ST.getAddressableNumArchVGPRs() &&`
`106`	`106`	`!mayUseAGPRs(F))`
`107`	`107`	`MayNeedAGPRs = false; // We will select all MAI with VGPR operands.`
`108`	`108`	`}`