Revert "[llvm-exegesis] [AArch64] Resolving "not all operands are initialized by snippet generator" (llvm#142529)"

This reverts commit 2e8ecf7.

It is causing clang-aarch64-quick buildbot to fail.

(see:https://lab.llvm.org/buildbot/#/builders/65/builds/22035)

Author: omjavaid

llvm/lib/Target/AArch64/AArch64InstrFormats.td

@@ -1327,8 +1327,6 @@ def move_vec_shift : Operand<i32> {
   let PrintMethod = "printShifter";
   let EncoderMethod = "getMoveVecShifterOpValue";
   let ParserMatchClass = MoveVecShifterOperand;
-  let OperandType = "OPERAND_SHIFT_MSL";
-  let OperandNamespace = "AArch64";
 }
 
 let DiagnosticType = "AddSubSecondSource" in {

llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h

@@ -65,16 +65,15 @@ void initLLVMToCVRegMapping(MCRegisterInfo *MRI);
 bool isHForm(const MCInst &MI, const MCInstrInfo *MCII);
 bool isQForm(const MCInst &MI, const MCInstrInfo *MCII);
 bool isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII);
-} // namespace AArch64_MC
+}
 
 namespace AArch64 {
 enum OperandType {
   OPERAND_IMPLICIT_IMM_0 = MCOI::OPERAND_FIRST_TARGET,
-  OPERAND_SHIFT_MSL,
 };
 } // namespace AArch64
 
-} // namespace llvm
+} // End llvm namespace
 
 // Defines symbolic names for AArch64 registers.  This defines a mapping from
 // register name to register number.

llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s

@@ -119,10 +119,6 @@ class ExegesisAArch64Target : public ExegesisTarget {
   ExegesisAArch64Target()
       : ExegesisTarget(AArch64CpuPfmCounters, AArch64_MC::isOpcodeAvailable) {}
 
-  Error randomizeTargetMCOperand(const Instruction &Instr, const Variable &Var,
-                                 MCOperand &AssignedValue,
-                                 const BitVector &ForbiddenRegs) const override;
-
 private:
   std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, MCRegister Reg,
                                const APInt &Value) const override {
@@ -186,56 +182,6 @@ class ExegesisAArch64Target : public ExegesisTarget {
   }
 };
 
-Error ExegesisAArch64Target::randomizeTargetMCOperand(
-    const Instruction &Instr, const Variable &Var, MCOperand &AssignedValue,
-    const BitVector &ForbiddenRegs) const {
-  const Operand &Op = Instr.getPrimaryOperand(Var);
-  const auto OperandType = Op.getExplicitOperandInfo().OperandType;
-  // NOTE: To resolve "Not all operands were initialized by snippet generator"
-  // Requires OperandType to be defined for such opcode's operands in AArch64
-  // tablegen files. And omit introduced OperandType(s).
-
-  // Hacky temporary fix works by defaulting all OPERAND_UNKNOWN to
-  // immediate value 0, but this introduce illegal instruction error for below
-  // system instructions will need to be omitted with OperandType or opcode
-  // specific values to avoid generating invalid encodings or unreliable
-  // benchmark results for these system-level instructions.
-  //  Implement opcode-specific immediate value handling for system instrs:
-  //   - MRS/MSR: Use valid system register encodings (e.g., NZCV, FPCR, FPSR)
-  //   - MSRpstatesvcrImm1: Use valid PSTATE field encodings (e.g., SPSel,
-  //   DAIFSet)
-  //   - SYSLxt/SYSxt: Use valid system instruction encodings with proper
-  //   CRn/CRm/op values
-  //   - UDF: Use valid undefined instruction immediate ranges (0-65535)
-
-  switch (OperandType) {
-  // MSL (Masking Shift Left) imm operand for 32-bit splatted SIMD constants
-  // Correspond to AArch64InstructionSelector::tryAdvSIMDModImm321s()
-  case llvm::AArch64::OPERAND_SHIFT_MSL: {
-    // There are two valid encodings:
-    //   - Type 7: imm at [15:8], [47:40], shift = 264 (0x108) → msl #8
-    //   - Type 8: imm at [23:16], [55:48], shift = 272 (0x110) → msl #16
-    //     Corresponds AArch64_AM::encodeAdvSIMDModImmType7()
-    // But, v2s_msl and v4s_msl instructions accept either form,
-    // Thus, Arbitrarily chosing 264 (msl #8) for simplicity.
-    AssignedValue = MCOperand::createImm(264);
-    return Error::success();
-  }
-  case llvm::AArch64::OPERAND_IMPLICIT_IMM_0:
-    AssignedValue = MCOperand::createImm(0);
-    return Error::success();
-  case MCOI::OperandType::OPERAND_PCREL:
-    AssignedValue = MCOperand::createImm(8);
-    return Error::success();
-  default:
-    break;
-  }
-
-  return make_error<Failure>(
-      Twine("Unimplemented operand type: MCOI::OperandType:")
-          .concat(Twine(static_cast<int>(OperandType))));
-}
-
 } // namespace
 
 static ExegesisTarget *getTheExegesisAArch64Target() {

llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp

@@ -276,10 +276,6 @@ static Error randomizeMCOperand(const LLVMState &State,
     AssignedValue = MCOperand::createReg(randomBit(AllowedRegs));
     break;
   }
-  /// Omit pc-relative operands to imm value based on the instruction
-  case MCOI::OperandType::OPERAND_PCREL:
-    return State.getExegesisTarget().randomizeTargetMCOperand(
-        Instr, Var, AssignedValue, ForbiddenRegs);
   default:
     break;
   }