Fix arch in Fusion test (#1888)

umangyadav · web-flow · commit 5abd971b4c67 · 2025-06-17T07:14:14.000-04:00
diff --git a/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_13.torch-tosa.mlir b/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_13.torch-tosa.mlir
@@ -1,5 +1,4 @@
 // RUN: rocmlir-gen -fut bert_part_13 -arch %arch --clone-harness %s | rocmlir-driver -host-pipeline highlevel -targets %arch | rocmlir-gen -ph -print-results -rand 1 -rand_type float -fut bert_part_13_wrapper --verifier clone - | rocmlir-driver -host-pipeline mhal -kernel-pipeline full | xmir-runner --shared-libs=%linalg_test_lib_dir/libmlir_rocm_runtime%shlibext,%conv_validation_wrapper_library_dir/libconv-validation-wrappers%shlibext,%linalg_test_lib_dir/libmlir_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_float16_utils%shlibext,%linalg_test_lib_dir/libmlir_c_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_async_runtime%shlibext --entry-point-result=void | FileCheck %s
-// CHECK-DISABLED: RMS = {{.*}}e-08
 // CHECK: [1 1 1]
 module {
   func.func @bert_part_13(%arg0: tensor<1x12x12x32xf32> {mhal.read_access}, %arg1: tensor<384x384xf32> {mhal.read_access}, %arg2: tensor<1x1x384xf32> {mhal.read_access}, %arg3: tensor<1x12x384xf32> {mhal.read_access}) -> (tensor<1x12x384xf32> {mhal.write_access}) {
diff --git a/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_14.torch-tosa.mlir b/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_14.torch-tosa.mlir
@@ -1,5 +1,4 @@
 // RUN: rocmlir-gen -fut bert_part_14 -arch %arch --clone-harness %s | rocmlir-driver -host-pipeline highlevel -targets %arch | rocmlir-gen -ph -print-results -rand 1 -rand_type float -fut bert_part_14_wrapper --verifier clone - | rocmlir-driver -host-pipeline mhal -kernel-pipeline full | xmir-runner --shared-libs=%linalg_test_lib_dir/libmlir_rocm_runtime%shlibext,%conv_validation_wrapper_library_dir/libconv-validation-wrappers%shlibext,%linalg_test_lib_dir/libmlir_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_float16_utils%shlibext,%linalg_test_lib_dir/libmlir_c_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_async_runtime%shlibext --entry-point-result=void | FileCheck %s
-// CHECK-DISABLED: RMS = {{.*}}e-08
 // CHECK: [1 1 1]
 module {
   func.func @bert_part_14(%arg0: tensor<1x12x384xf32> {mhal.read_access}, %arg1: tensor<384x1536xf32> {mhal.read_access}, %arg2: tensor<1x1x1536xf32> {mhal.read_access}) -> (tensor<1x12x1536xf32> {mhal.write_access}) {
diff --git a/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_15.torch-tosa.mlir b/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_15.torch-tosa.mlir
@@ -1,5 +1,4 @@
 // RUN: rocmlir-gen -fut bert_part_15 -arch %arch --clone-harness %s | rocmlir-driver -host-pipeline highlevel -targets %arch | rocmlir-gen -ph -print-results -rand 1 -rand_type float -fut bert_part_15_wrapper --verifier clone - | rocmlir-driver -host-pipeline mhal -kernel-pipeline full | xmir-runner --shared-libs=%linalg_test_lib_dir/libmlir_rocm_runtime%shlibext,%conv_validation_wrapper_library_dir/libconv-validation-wrappers%shlibext,%linalg_test_lib_dir/libmlir_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_float16_utils%shlibext,%linalg_test_lib_dir/libmlir_c_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_async_runtime%shlibext --entry-point-result=void | FileCheck %s
-// CHECK-DISABLED: RMS = {{.*}}e-08
 // CHECK: [1 1 1]
 module {
   func.func @bert_part_15(%arg0: tensor<1x12x1536xf32> {mhal.read_access}, %arg1: tensor<1536x384xf32> {mhal.read_access}, %arg2: tensor<1x1x384xf32> {mhal.read_access}, %arg3: tensor<1x12x384xf32> {mhal.read_access}) -> (tensor<1x12x384xf32> {mhal.write_access}) {
diff --git a/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_19.torch-tosa.mlir b/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_19.torch-tosa.mlir
@@ -1,5 +1,4 @@
 // RUN: rocmlir-gen -fut bert_part_19 -arch %arch --clone-harness %s | rocmlir-driver -host-pipeline highlevel -targets %arch | rocmlir-gen -ph -print-results -rand 1 -rand_type float -fut bert_part_19_wrapper --verifier clone - | rocmlir-driver -host-pipeline mhal -kernel-pipeline full | xmir-runner --shared-libs=%linalg_test_lib_dir/libmlir_rocm_runtime%shlibext,%conv_validation_wrapper_library_dir/libconv-validation-wrappers%shlibext,%linalg_test_lib_dir/libmlir_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_float16_utils%shlibext,%linalg_test_lib_dir/libmlir_c_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_async_runtime%shlibext --entry-point-result=void | FileCheck %s
-// CHECK-DISABLED: RMS = {{.*}}e-08
 // CHECK: [1 1 1]
 module {
   func.func @bert_part_19(%arg0: tensor<1x12x12x32xf32> {mhal.read_access}, %arg1: tensor<1x12x32x12xf32> {mhal.read_access}, %arg2: tensor<1x1x1x1xf32> {mhal.read_access}, %arg3: tensor<1x1x1x12xf32> {mhal.read_access}) -> (tensor<1x12x12x12xf32> {mhal.write_access}) {
diff --git a/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_21.torch-tosa.mlir b/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_21.torch-tosa.mlir
@@ -1,5 +1,4 @@
 // RUN: rocmlir-gen -fut bert_part_21 -arch %arch --clone-harness %s | rocmlir-driver -host-pipeline highlevel -targets %arch | rocmlir-gen -ph -print-results -rand 1 -rand_type float -fut bert_part_21_wrapper --verifier clone - | rocmlir-driver -host-pipeline mhal -kernel-pipeline full | xmir-runner --shared-libs=%linalg_test_lib_dir/libmlir_rocm_runtime%shlibext,%conv_validation_wrapper_library_dir/libconv-validation-wrappers%shlibext,%linalg_test_lib_dir/libmlir_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_float16_utils%shlibext,%linalg_test_lib_dir/libmlir_c_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_async_runtime%shlibext --entry-point-result=void | FileCheck %s
-// CHECK-DISABLED: RMS = {{.*}}e-08
 // CHECK: [1 1 1]
 module {
   func.func @bert_part_21(%arg0: tensor<1x12x12x32xf32> {mhal.read_access}, %arg1: tensor<384x384xf32> {mhal.read_access}, %arg2: tensor<1x1x384xf32> {mhal.read_access}, %arg3: tensor<1x12x384xf32> {mhal.read_access}) -> (tensor<1x12x384xf32> {mhal.write_access}) {
diff --git a/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_22.torch-tosa.mlir b/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_22.torch-tosa.mlir
@@ -1,5 +1,4 @@
 // RUN: rocmlir-gen -fut bert_part_22 -arch %arch --clone-harness %s | rocmlir-driver -host-pipeline highlevel -targets %arch | rocmlir-gen -ph -print-results -rand 1 -rand_type float -fut bert_part_22_wrapper --verifier clone - | rocmlir-driver -host-pipeline mhal -kernel-pipeline full | xmir-runner --shared-libs=%linalg_test_lib_dir/libmlir_rocm_runtime%shlibext,%conv_validation_wrapper_library_dir/libconv-validation-wrappers%shlibext,%linalg_test_lib_dir/libmlir_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_float16_utils%shlibext,%linalg_test_lib_dir/libmlir_c_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_async_runtime%shlibext --entry-point-result=void | FileCheck %s
-// CHECK-DISABLED: RMS = {{.*}}e-08
 // CHECK: [1 1 1]
 module {
   func.func @bert_part_22(%arg0: tensor<1x12x384xf32> {mhal.read_access}, %arg1: tensor<384x1536xf32> {mhal.read_access}, %arg2: tensor<1x1x1536xf32> {mhal.read_access}) -> (tensor<1x12x1536xf32> {mhal.write_access}) {
diff --git a/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_29.torch-tosa.mlir b/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_29.torch-tosa.mlir
@@ -1,5 +1,4 @@
 // RUN: rocmlir-gen -fut bert_part_29 -arch %arch --clone-harness %s | rocmlir-driver -host-pipeline highlevel -targets %arch | rocmlir-gen -ph -print-results -rand 1 -rand_type float -fut bert_part_29_wrapper --verifier clone - | rocmlir-driver -host-pipeline mhal -kernel-pipeline full | xmir-runner --shared-libs=%linalg_test_lib_dir/libmlir_rocm_runtime%shlibext,%conv_validation_wrapper_library_dir/libconv-validation-wrappers%shlibext,%linalg_test_lib_dir/libmlir_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_float16_utils%shlibext,%linalg_test_lib_dir/libmlir_c_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_async_runtime%shlibext --entry-point-result=void | FileCheck %s
-// CHECK-DISABLED: RMS = {{.*}}e-08
 // CHECK: [1 1 1]
 module {
   func.func @bert_part_29(%arg0: tensor<1x12x12x32xf32> {mhal.read_access}, %arg1: tensor<384x384xf32> {mhal.read_access}, %arg2: tensor<1x1x384xf32> {mhal.read_access}, %arg3: tensor<1x12x384xf32> {mhal.read_access}) -> (tensor<1x12x384xf32> {mhal.write_access}) {
diff --git a/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_3.torch-tosa.mlir b/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_3.torch-tosa.mlir
@@ -1,5 +1,4 @@
 // RUN: rocmlir-gen -fut bert_part_3 -arch %arch --clone-harness %s | rocmlir-driver -host-pipeline highlevel -targets %arch | rocmlir-gen -ph -print-results -rand 1 -rand_type float -fut bert_part_3_wrapper --verifier clone - | rocmlir-driver -host-pipeline mhal -kernel-pipeline full | xmir-runner --shared-libs=%linalg_test_lib_dir/libmlir_rocm_runtime%shlibext,%conv_validation_wrapper_library_dir/libconv-validation-wrappers%shlibext,%linalg_test_lib_dir/libmlir_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_float16_utils%shlibext,%linalg_test_lib_dir/libmlir_c_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_async_runtime%shlibext --entry-point-result=void | FileCheck %s
-// CHECK-DISABLED: RMS = {{.*}}e-08
 // CHECK: [1 1 1]
 module {
   func.func @bert_part_3(%arg0: tensor<1x12x12x32xf32> {mhal.read_access}, %arg1: tensor<1x12x32x12xf32> {mhal.read_access}, %arg2: tensor<1x1x1x1xf32> {mhal.read_access}, %arg3: tensor<1x1x1x12xf32> {mhal.read_access}) -> (tensor<1x12x12x12xf32> {mhal.write_access}) {
diff --git a/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_30.torch-tosa.mlir b/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_30.torch-tosa.mlir
@@ -1,5 +1,4 @@
 // RUN: rocmlir-gen -fut bert_part_30 -arch %arch --clone-harness %s | rocmlir-driver -host-pipeline highlevel -targets %arch | rocmlir-gen -ph -print-results -rand 1 -rand_type float -fut bert_part_30_wrapper --verifier clone - | rocmlir-driver -host-pipeline mhal -kernel-pipeline full | xmir-runner --shared-libs=%linalg_test_lib_dir/libmlir_rocm_runtime%shlibext,%conv_validation_wrapper_library_dir/libconv-validation-wrappers%shlibext,%linalg_test_lib_dir/libmlir_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_float16_utils%shlibext,%linalg_test_lib_dir/libmlir_c_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_async_runtime%shlibext --entry-point-result=void | FileCheck %s
-// CHECK-DISABLED: RMS = {{.*}}e-08
 // CHECK: [1 1 1]
 module {
   func.func @bert_part_30(%arg0: tensor<1x12x384xf32> {mhal.read_access}, %arg1: tensor<384x1536xf32> {mhal.read_access}, %arg2: tensor<1x1x1536xf32> {mhal.read_access}) -> (tensor<1x12x1536xf32> {mhal.write_access}) {
diff --git a/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_37.torch-tosa.mlir b/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_37.torch-tosa.mlir
@@ -1,5 +1,4 @@
 // RUN: rocmlir-gen -fut bert_part_37 -arch %arch --clone-harness %s | rocmlir-driver -host-pipeline highlevel -targets %arch | rocmlir-gen -ph -print-results -rand 1 -rand_type float -fut bert_part_37_wrapper --verifier clone - | rocmlir-driver -host-pipeline mhal -kernel-pipeline full | xmir-runner --shared-libs=%linalg_test_lib_dir/libmlir_rocm_runtime%shlibext,%conv_validation_wrapper_library_dir/libconv-validation-wrappers%shlibext,%linalg_test_lib_dir/libmlir_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_float16_utils%shlibext,%linalg_test_lib_dir/libmlir_c_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_async_runtime%shlibext --entry-point-result=void | FileCheck %s
-// CHECK-DISABLED: RMS = {{.*}}e-08
 // CHECK: [1 1 1]
 module {
   func.func @bert_part_37(%arg0: tensor<1x12x12x32xf32> {mhal.read_access}, %arg1: tensor<384x384xf32> {mhal.read_access}, %arg2: tensor<1x1x384xf32> {mhal.read_access}, %arg3: tensor<1x12x384xf32> {mhal.read_access}) -> (tensor<1x12x384xf32> {mhal.write_access}) {
diff --git a/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_38.torch-tosa.mlir b/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_38.torch-tosa.mlir
@@ -1,5 +1,4 @@
 // RUN: rocmlir-gen -fut bert_part_38 -arch %arch --clone-harness %s | rocmlir-driver -host-pipeline highlevel -targets %arch | rocmlir-gen -ph -print-results -rand 1 -rand_type float -fut bert_part_38_wrapper --verifier clone - | rocmlir-driver -host-pipeline mhal -kernel-pipeline full | xmir-runner --shared-libs=%linalg_test_lib_dir/libmlir_rocm_runtime%shlibext,%conv_validation_wrapper_library_dir/libconv-validation-wrappers%shlibext,%linalg_test_lib_dir/libmlir_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_float16_utils%shlibext,%linalg_test_lib_dir/libmlir_c_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_async_runtime%shlibext --entry-point-result=void | FileCheck %s
-// CHECK-DISABLED: RMS = {{.*}}e-08
 // CHECK: [1 1 1]
 module {
   func.func @bert_part_38(%arg0: tensor<1x12x384xf32> {mhal.read_access}, %arg1: tensor<384x1536xf32> {mhal.read_access}, %arg2: tensor<1x1x1536xf32> {mhal.read_access}) -> (tensor<1x12x1536xf32> {mhal.write_access}) {
diff --git a/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_4.torch-tosa.mlir b/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_4.torch-tosa.mlir
@@ -1,5 +1,4 @@
 // RUN: rocmlir-gen -fut bert_part_4 -arch %arch --clone-harness %s | rocmlir-driver -host-pipeline highlevel -targets %arch | rocmlir-gen -ph -print-results -rand 1 -rand_type float -fut bert_part_4_wrapper --verifier clone - | rocmlir-driver -host-pipeline mhal -kernel-pipeline full | xmir-runner --shared-libs=%linalg_test_lib_dir/libmlir_rocm_runtime%shlibext,%conv_validation_wrapper_library_dir/libconv-validation-wrappers%shlibext,%linalg_test_lib_dir/libmlir_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_float16_utils%shlibext,%linalg_test_lib_dir/libmlir_c_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_async_runtime%shlibext --entry-point-result=void | FileCheck %s
-// CHECK-DISABLED: RMS = {{.*}}e-08
 // CHECK: [1 1 1]
 module {
   func.func @bert_part_4(%arg0: tensor<1x12x12x12xf32> {mhal.read_access}, %arg1: tensor<1x12x12x32xf32> {mhal.read_access}) -> (tensor<1x12x12x32xf32> {mhal.write_access}) {
diff --git a/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_48.torch-tosa.mlir b/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_48.torch-tosa.mlir
@@ -1,5 +1,4 @@
 // RUN: rocmlir-gen -fut bert_part_48 -arch %arch --clone-harness %s | rocmlir-driver -host-pipeline highlevel -targets %arch | rocmlir-gen -ph -print-results -rand 1 -rand_type float -fut bert_part_48_wrapper --verifier clone - | rocmlir-driver -host-pipeline mhal -kernel-pipeline full | xmir-runner --shared-libs=%linalg_test_lib_dir/libmlir_rocm_runtime%shlibext,%conv_validation_wrapper_library_dir/libconv-validation-wrappers%shlibext,%linalg_test_lib_dir/libmlir_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_float16_utils%shlibext,%linalg_test_lib_dir/libmlir_c_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_async_runtime%shlibext --entry-point-result=void | FileCheck %s
-// CHECK-DISABLED: RMS = {{.*}}e-08
 // CHECK: [1 1 1]
 module {
   func.func @bert_part_48(%arg0: tensor<1x1x384xf32> {mhal.read_access}, %arg1: tensor<384x384xf32> {mhal.read_access}, %arg2: tensor<1x384xf32> {mhal.read_access}) -> (tensor<1x1x384xf32> {mhal.write_access}) {
diff --git a/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_49.torch-tosa.mlir b/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_49.torch-tosa.mlir
@@ -1,9 +1,5 @@
-// MLIR#764: rock-to-gpu bug when global constant not cloned
-// RUN: rocmlir-gen -fut bert_part_49 -arch gfx1100 --clone-harness %s | rocmlir-driver -host-pipeline highlevel -targets %arch | FileCheck %s
-// RUN-DISABLE: rocmlir-gen -fut bert_part_49 -arch gfx1100 --clone-harness %s | rocmlir-driver -host-pipeline highlevel -targets %arch | rocmlir-gen -ph -print-results -rand 1 -rand_type float -fut bert_part_49_wrapper --verifier clone - | rocmlir-driver -host-pipeline mhal -kernel-pipeline full | xmir-runner --shared-libs=%linalg_test_lib_dir/libmlir_rocm_runtime%shlibext,%conv_validation_wrapper_library_dir/libconv-validation-wrappers%shlibext,%linalg_test_lib_dir/libmlir_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_float16_utils%shlibext,%linalg_test_lib_dir/libmlir_c_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_async_runtime%shlibext --entry-point-result=void | FileCheck %s
-// CHECK-DISABLED: RMS = {{.*}}e-08
-// COM: CHECK: [1 1 1]
-// CHECK: bert_part_49_wrapper
+// RUN: rocmlir-gen -fut bert_part_49 -arch %arch --clone-harness %s | rocmlir-driver -host-pipeline highlevel -targets %arch | rocmlir-gen -ph -print-results -rand 1 -rand_type float -fut bert_part_49_wrapper --verifier clone - | rocmlir-driver -host-pipeline mhal -kernel-pipeline full | xmir-runner --shared-libs=%linalg_test_lib_dir/libmlir_rocm_runtime%shlibext,%conv_validation_wrapper_library_dir/libconv-validation-wrappers%shlibext,%linalg_test_lib_dir/libmlir_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_float16_utils%shlibext,%linalg_test_lib_dir/libmlir_c_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_async_runtime%shlibext --entry-point-result=void | FileCheck %s
+// CHECK: [1 1 1]
 module {
   func.func @bert_part_49(%arg0: tensor<1x1x384xf32> {mhal.read_access}, %arg1: tensor<384x2xf32> {mhal.read_access}) -> (tensor<1x2xf32> {mhal.write_access}) {
       %const_shape = "tosa.const_shape"() { values = dense<[1, 384, 2]> : tensor<3xindex> } : () -> !tosa.shape<3>
diff --git a/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_5.torch-tosa.mlir b/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_5.torch-tosa.mlir
@@ -1,5 +1,4 @@
 // RUN: rocmlir-gen -fut bert_part_5 -arch %arch --clone-harness %s | rocmlir-driver -host-pipeline highlevel -targets %arch | rocmlir-gen -ph -print-results -rand 1 -rand_type float -fut bert_part_5_wrapper --verifier clone - | rocmlir-driver -host-pipeline mhal -kernel-pipeline full | xmir-runner --shared-libs=%linalg_test_lib_dir/libmlir_rocm_runtime%shlibext,%conv_validation_wrapper_library_dir/libconv-validation-wrappers%shlibext,%linalg_test_lib_dir/libmlir_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_float16_utils%shlibext,%linalg_test_lib_dir/libmlir_c_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_async_runtime%shlibext --entry-point-result=void | FileCheck %s
-// CHECK-DISABLED: RMS = {{.*}}e-08
 // CHECK: [1 1 1]
 module {
   func.func @bert_part_5(%arg0: tensor<1x12x12x32xf32> {mhal.read_access}, %arg1: tensor<384x384xf32> {mhal.read_access}, %arg2: tensor<1x1x384xf32> {mhal.read_access}, %arg3: tensor<1x12x384xf32> {mhal.read_access}) -> (tensor<1x12x384xf32> {mhal.write_access}) {
diff --git a/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_6.torch-tosa.mlir b/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_6.torch-tosa.mlir
@@ -1,5 +1,4 @@
 // RUN: rocmlir-gen -fut bert_part_6 -arch %arch --clone-harness %s | rocmlir-driver -host-pipeline highlevel -targets %arch | rocmlir-gen -ph -print-results -rand 1 -rand_type float -fut bert_part_6_wrapper --verifier clone - | rocmlir-driver -host-pipeline mhal -kernel-pipeline full | xmir-runner --shared-libs=%linalg_test_lib_dir/libmlir_rocm_runtime%shlibext,%conv_validation_wrapper_library_dir/libconv-validation-wrappers%shlibext,%linalg_test_lib_dir/libmlir_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_float16_utils%shlibext,%linalg_test_lib_dir/libmlir_c_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_async_runtime%shlibext --entry-point-result=void | FileCheck %s
-// CHECK-DISABLED: RMS = {{.*}}e-08
 // CHECK: [1 1 1]
 module {
   func.func @bert_part_6(%arg0: tensor<1x12x384xf32> {mhal.read_access}, %arg1: tensor<384x1536xf32> {mhal.read_access}, %arg2: tensor<1x1x1536xf32> {mhal.read_access}) -> (tensor<1x12x1536xf32> {mhal.write_access}) {
diff --git a/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_7.torch-tosa.mlir b/mlir/test/xmir/bert-torch-tosa-e2e/bert_part_7.torch-tosa.mlir
@@ -1,5 +1,4 @@
 // RUN: rocmlir-gen -fut bert_part_7 -arch %arch --clone-harness %s | rocmlir-driver -host-pipeline highlevel -targets %arch | rocmlir-gen -ph -print-results -rand 1 -rand_type float -fut bert_part_7_wrapper --verifier clone - | rocmlir-driver -host-pipeline mhal -kernel-pipeline full | xmir-runner --shared-libs=%linalg_test_lib_dir/libmlir_rocm_runtime%shlibext,%conv_validation_wrapper_library_dir/libconv-validation-wrappers%shlibext,%linalg_test_lib_dir/libmlir_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_float16_utils%shlibext,%linalg_test_lib_dir/libmlir_c_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_async_runtime%shlibext --entry-point-result=void | FileCheck %s
-// CHECK-DISABLED: RMS = {{.*}}e-08
 // CHECK: [1 1 1]
 module {
   func.func @bert_part_7(%arg0: tensor<1x12x1536xf32> {mhal.read_access}, %arg1: tensor<1536x384xf32> {mhal.read_access}, %arg2: tensor<1x1x384xf32> {mhal.read_access}, %arg3: tensor<1x12x384xf32> {mhal.read_access}) -> (tensor<1x12x384xf32> {mhal.write_access}) {

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`@@ -1,5 +1,4 @@`
`1`	`1`	// RUN: rocmlir-gen -fut bert_part_13 -arch %arch --clone-harness %s \| rocmlir-driver -host-pipeline highlevel -targets %arch \| rocmlir-gen -ph -print-results -rand 1 -rand_type float -fut bert_part_13_wrapper --verifier clone - \| rocmlir-driver -host-pipeline mhal -kernel-pipeline full \| xmir-runner --shared-libs=%linalg_test_lib_dir/libmlir_rocm_runtime%shlibext,%conv_validation_wrapper_library_dir/libconv-validation-wrappers%shlibext,%linalg_test_lib_dir/libmlir_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_float16_utils%shlibext,%linalg_test_lib_dir/libmlir_c_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_async_runtime%shlibext --entry-point-result=void \| FileCheck %s
`2`		`-// CHECK-DISABLED: RMS = {{.*}}e-08`
`3`	`2`	`// CHECK: [1 1 1]`
`4`	`3`	`module {`
`5`	`4`	`func.func @bert_part_13(%arg0: tensor<1x12x12x32xf32> {mhal.read_access}, %arg1: tensor<384x384xf32> {mhal.read_access}, %arg2: tensor<1x1x384xf32> {mhal.read_access}, %arg3: tensor<1x12x384xf32> {mhal.read_access}) -> (tensor<1x12x384xf32> {mhal.write_access}) {`
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`@@ -1,5 +1,4 @@`
`1`	`1`	// RUN: rocmlir-gen -fut bert_part_14 -arch %arch --clone-harness %s \| rocmlir-driver -host-pipeline highlevel -targets %arch \| rocmlir-gen -ph -print-results -rand 1 -rand_type float -fut bert_part_14_wrapper --verifier clone - \| rocmlir-driver -host-pipeline mhal -kernel-pipeline full \| xmir-runner --shared-libs=%linalg_test_lib_dir/libmlir_rocm_runtime%shlibext,%conv_validation_wrapper_library_dir/libconv-validation-wrappers%shlibext,%linalg_test_lib_dir/libmlir_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_float16_utils%shlibext,%linalg_test_lib_dir/libmlir_c_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_async_runtime%shlibext --entry-point-result=void \| FileCheck %s
`2`		`-// CHECK-DISABLED: RMS = {{.*}}e-08`
`3`	`2`	`// CHECK: [1 1 1]`
`4`	`3`	`module {`
`5`	`4`	`func.func @bert_part_14(%arg0: tensor<1x12x384xf32> {mhal.read_access}, %arg1: tensor<384x1536xf32> {mhal.read_access}, %arg2: tensor<1x1x1536xf32> {mhal.read_access}) -> (tensor<1x12x1536xf32> {mhal.write_access}) {`
Original file line number	Diff line number	Diff line change
`@@ -1,5 +1,4 @@`
`1`	`1`	// RUN: rocmlir-gen -fut bert_part_15 -arch %arch --clone-harness %s \| rocmlir-driver -host-pipeline highlevel -targets %arch \| rocmlir-gen -ph -print-results -rand 1 -rand_type float -fut bert_part_15_wrapper --verifier clone - \| rocmlir-driver -host-pipeline mhal -kernel-pipeline full \| xmir-runner --shared-libs=%linalg_test_lib_dir/libmlir_rocm_runtime%shlibext,%conv_validation_wrapper_library_dir/libconv-validation-wrappers%shlibext,%linalg_test_lib_dir/libmlir_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_float16_utils%shlibext,%linalg_test_lib_dir/libmlir_c_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_async_runtime%shlibext --entry-point-result=void \| FileCheck %s
`2`		`-// CHECK-DISABLED: RMS = {{.*}}e-08`
`3`	`2`	`// CHECK: [1 1 1]`
`4`	`3`	`module {`
`5`	`4`	`func.func @bert_part_15(%arg0: tensor<1x12x1536xf32> {mhal.read_access}, %arg1: tensor<1536x384xf32> {mhal.read_access}, %arg2: tensor<1x1x384xf32> {mhal.read_access}, %arg3: tensor<1x12x384xf32> {mhal.read_access}) -> (tensor<1x12x384xf32> {mhal.write_access}) {`
Original file line number	Diff line number	Diff line change
`@@ -1,5 +1,4 @@`
`1`	`1`	// RUN: rocmlir-gen -fut bert_part_19 -arch %arch --clone-harness %s \| rocmlir-driver -host-pipeline highlevel -targets %arch \| rocmlir-gen -ph -print-results -rand 1 -rand_type float -fut bert_part_19_wrapper --verifier clone - \| rocmlir-driver -host-pipeline mhal -kernel-pipeline full \| xmir-runner --shared-libs=%linalg_test_lib_dir/libmlir_rocm_runtime%shlibext,%conv_validation_wrapper_library_dir/libconv-validation-wrappers%shlibext,%linalg_test_lib_dir/libmlir_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_float16_utils%shlibext,%linalg_test_lib_dir/libmlir_c_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_async_runtime%shlibext --entry-point-result=void \| FileCheck %s
`2`		`-// CHECK-DISABLED: RMS = {{.*}}e-08`
`3`	`2`	`// CHECK: [1 1 1]`
`4`	`3`	`module {`
`5`	`4`	`func.func @bert_part_19(%arg0: tensor<1x12x12x32xf32> {mhal.read_access}, %arg1: tensor<1x12x32x12xf32> {mhal.read_access}, %arg2: tensor<1x1x1x1xf32> {mhal.read_access}, %arg3: tensor<1x1x1x12xf32> {mhal.read_access}) -> (tensor<1x12x12x12xf32> {mhal.write_access}) {`
Original file line number	Diff line number	Diff line change
`@@ -1,5 +1,4 @@`
`1`	`1`	// RUN: rocmlir-gen -fut bert_part_21 -arch %arch --clone-harness %s \| rocmlir-driver -host-pipeline highlevel -targets %arch \| rocmlir-gen -ph -print-results -rand 1 -rand_type float -fut bert_part_21_wrapper --verifier clone - \| rocmlir-driver -host-pipeline mhal -kernel-pipeline full \| xmir-runner --shared-libs=%linalg_test_lib_dir/libmlir_rocm_runtime%shlibext,%conv_validation_wrapper_library_dir/libconv-validation-wrappers%shlibext,%linalg_test_lib_dir/libmlir_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_float16_utils%shlibext,%linalg_test_lib_dir/libmlir_c_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_async_runtime%shlibext --entry-point-result=void \| FileCheck %s
`2`		`-// CHECK-DISABLED: RMS = {{.*}}e-08`
`3`	`2`	`// CHECK: [1 1 1]`
`4`	`3`	`module {`
`5`	`4`	`func.func @bert_part_21(%arg0: tensor<1x12x12x32xf32> {mhal.read_access}, %arg1: tensor<384x384xf32> {mhal.read_access}, %arg2: tensor<1x1x384xf32> {mhal.read_access}, %arg3: tensor<1x12x384xf32> {mhal.read_access}) -> (tensor<1x12x384xf32> {mhal.write_access}) {`
Original file line number	Diff line number	Diff line change
`@@ -1,5 +1,4 @@`
`1`	`1`	// RUN: rocmlir-gen -fut bert_part_22 -arch %arch --clone-harness %s \| rocmlir-driver -host-pipeline highlevel -targets %arch \| rocmlir-gen -ph -print-results -rand 1 -rand_type float -fut bert_part_22_wrapper --verifier clone - \| rocmlir-driver -host-pipeline mhal -kernel-pipeline full \| xmir-runner --shared-libs=%linalg_test_lib_dir/libmlir_rocm_runtime%shlibext,%conv_validation_wrapper_library_dir/libconv-validation-wrappers%shlibext,%linalg_test_lib_dir/libmlir_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_float16_utils%shlibext,%linalg_test_lib_dir/libmlir_c_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_async_runtime%shlibext --entry-point-result=void \| FileCheck %s
`2`		`-// CHECK-DISABLED: RMS = {{.*}}e-08`
`3`	`2`	`// CHECK: [1 1 1]`
`4`	`3`	`module {`
`5`	`4`	`func.func @bert_part_22(%arg0: tensor<1x12x384xf32> {mhal.read_access}, %arg1: tensor<384x1536xf32> {mhal.read_access}, %arg2: tensor<1x1x1536xf32> {mhal.read_access}) -> (tensor<1x12x1536xf32> {mhal.write_access}) {`
Original file line number	Diff line number	Diff line change
`@@ -1,5 +1,4 @@`
`1`	`1`	// RUN: rocmlir-gen -fut bert_part_29 -arch %arch --clone-harness %s \| rocmlir-driver -host-pipeline highlevel -targets %arch \| rocmlir-gen -ph -print-results -rand 1 -rand_type float -fut bert_part_29_wrapper --verifier clone - \| rocmlir-driver -host-pipeline mhal -kernel-pipeline full \| xmir-runner --shared-libs=%linalg_test_lib_dir/libmlir_rocm_runtime%shlibext,%conv_validation_wrapper_library_dir/libconv-validation-wrappers%shlibext,%linalg_test_lib_dir/libmlir_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_float16_utils%shlibext,%linalg_test_lib_dir/libmlir_c_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_async_runtime%shlibext --entry-point-result=void \| FileCheck %s
`2`		`-// CHECK-DISABLED: RMS = {{.*}}e-08`
`3`	`2`	`// CHECK: [1 1 1]`
`4`	`3`	`module {`
`5`	`4`	`func.func @bert_part_29(%arg0: tensor<1x12x12x32xf32> {mhal.read_access}, %arg1: tensor<384x384xf32> {mhal.read_access}, %arg2: tensor<1x1x384xf32> {mhal.read_access}, %arg3: tensor<1x12x384xf32> {mhal.read_access}) -> (tensor<1x12x384xf32> {mhal.write_access}) {`
Original file line number	Diff line number	Diff line change
`@@ -1,5 +1,4 @@`
`1`	`1`	// RUN: rocmlir-gen -fut bert_part_3 -arch %arch --clone-harness %s \| rocmlir-driver -host-pipeline highlevel -targets %arch \| rocmlir-gen -ph -print-results -rand 1 -rand_type float -fut bert_part_3_wrapper --verifier clone - \| rocmlir-driver -host-pipeline mhal -kernel-pipeline full \| xmir-runner --shared-libs=%linalg_test_lib_dir/libmlir_rocm_runtime%shlibext,%conv_validation_wrapper_library_dir/libconv-validation-wrappers%shlibext,%linalg_test_lib_dir/libmlir_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_float16_utils%shlibext,%linalg_test_lib_dir/libmlir_c_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_async_runtime%shlibext --entry-point-result=void \| FileCheck %s
`2`		`-// CHECK-DISABLED: RMS = {{.*}}e-08`
`3`	`2`	`// CHECK: [1 1 1]`
`4`	`3`	`module {`
`5`	`4`	`func.func @bert_part_3(%arg0: tensor<1x12x12x32xf32> {mhal.read_access}, %arg1: tensor<1x12x32x12xf32> {mhal.read_access}, %arg2: tensor<1x1x1x1xf32> {mhal.read_access}, %arg3: tensor<1x1x1x12xf32> {mhal.read_access}) -> (tensor<1x12x12x12xf32> {mhal.write_access}) {`
Original file line number	Diff line number	Diff line change
`@@ -1,5 +1,4 @@`
`1`	`1`	// RUN: rocmlir-gen -fut bert_part_30 -arch %arch --clone-harness %s \| rocmlir-driver -host-pipeline highlevel -targets %arch \| rocmlir-gen -ph -print-results -rand 1 -rand_type float -fut bert_part_30_wrapper --verifier clone - \| rocmlir-driver -host-pipeline mhal -kernel-pipeline full \| xmir-runner --shared-libs=%linalg_test_lib_dir/libmlir_rocm_runtime%shlibext,%conv_validation_wrapper_library_dir/libconv-validation-wrappers%shlibext,%linalg_test_lib_dir/libmlir_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_float16_utils%shlibext,%linalg_test_lib_dir/libmlir_c_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_async_runtime%shlibext --entry-point-result=void \| FileCheck %s
`2`		`-// CHECK-DISABLED: RMS = {{.*}}e-08`
`3`	`2`	`// CHECK: [1 1 1]`
`4`	`3`	`module {`
`5`	`4`	`func.func @bert_part_30(%arg0: tensor<1x12x384xf32> {mhal.read_access}, %arg1: tensor<384x1536xf32> {mhal.read_access}, %arg2: tensor<1x1x1536xf32> {mhal.read_access}) -> (tensor<1x12x1536xf32> {mhal.write_access}) {`
Original file line number	Diff line number	Diff line change
`@@ -1,5 +1,4 @@`
`1`	`1`	// RUN: rocmlir-gen -fut bert_part_37 -arch %arch --clone-harness %s \| rocmlir-driver -host-pipeline highlevel -targets %arch \| rocmlir-gen -ph -print-results -rand 1 -rand_type float -fut bert_part_37_wrapper --verifier clone - \| rocmlir-driver -host-pipeline mhal -kernel-pipeline full \| xmir-runner --shared-libs=%linalg_test_lib_dir/libmlir_rocm_runtime%shlibext,%conv_validation_wrapper_library_dir/libconv-validation-wrappers%shlibext,%linalg_test_lib_dir/libmlir_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_float16_utils%shlibext,%linalg_test_lib_dir/libmlir_c_runner_utils%shlibext,%linalg_test_lib_dir/libmlir_async_runtime%shlibext --entry-point-result=void \| FileCheck %s
`2`		`-// CHECK-DISABLED: RMS = {{.*}}e-08`
`3`	`2`	`// CHECK: [1 1 1]`
`4`	`3`	`module {`
`5`	`4`	`func.func @bert_part_37(%arg0: tensor<1x12x12x32xf32> {mhal.read_access}, %arg1: tensor<384x384xf32> {mhal.read_access}, %arg2: tensor<1x1x384xf32> {mhal.read_access}, %arg3: tensor<1x12x384xf32> {mhal.read_access}) -> (tensor<1x12x384xf32> {mhal.write_access}) {`