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Update Zen5/5 documentation
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‎doc/archs/zen4.md‎

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</TR>
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</TABLE>
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<H1>Counters available for one hardware thread per L3 segment (aka CCD)</H1>
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<H1>Counters available for one hardware thread per socket</H1>
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\anchor ZEN4_POWER_SOCKET
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<H2>Power counters</H2>
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<P>The AMD&reg; Zen4 microarchitecture provides measurements of the current power consumption through the RAPL interface.</P>

‎doc/archs/zen4c.md‎

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</TR>
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</TABLE>
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<H1>Counters available for one hardware thread per L3 segment (aka CCD)</H1>
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<H1>Counters available for one hardware thread per socket</H1>
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\anchor ZEN4C_POWER_SOCKET
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<H2>Power counters</H2>
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<P>The AMD&reg; Zen4 microarchitecture provides measurements of the current power consumption through the RAPL interface.</P>

‎doc/archs/zen5.md‎

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<H1>Counters available for one hardware thread per L3 segment (aka CCD)</H1>
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<H1>Counters available for one hardware thread per socket</H1>
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\anchor ZEN5_POWER_SOCKET
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<H2>Power counters</H2>
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<P>The AMD&reg; Zen5 microarchitecture provides measurements of the current power consumption through the RAPL interface.</P>

‎doc/archs/zen5c.md‎

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\page zen5 AMD&reg; Zen5c (Ryzen, Epyc)
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<H1>Available performance monitors for the AMD&reg; Zen5c microarchitecture</H1>
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<UL>
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<LI>\ref ZEN5C_FIXED "Fixed-purpose counters"</LI>
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<LI>\ref ZEN5C_PMC "General-purpose counters"</LI>
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<LI>\ref ZEN5C_POWER_CORE "CPU core energy counters"</LI>
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<LI>\ref ZEN5C_CPMC "L3 cache general-purpose counters"</LI>
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<LI>\ref ZEN5C_POWER_SOCKET "Socket energy counters"</LI>
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<LI> \ref ZEN5C_DATA_FABRIC "Data Fabric counters"</LI>
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<LI> \ref ZEN5C_UMC "Unified memory controller counters"</LI>
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</UL>
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\anchor ZEN5C_FIXED
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<H2>Fixed-purpose counters</H2>
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<P>The AMD&reg; Zen5c microarchitecture provides three fixed-purpose counters for
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retired instructions, actual CPU core clock (MPerf: This register increments in
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proportion to the actual number of core clocks cycles while the core is in C0) and
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maximum CPU core clock (APerf: Incremented by hardware at the
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P0 frequency while the core is in C0).</P>
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<H3>Counter and events</H3>
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<TABLE>
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<TR>
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<TH>Counter name</TH>
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<TH>Event name</TH>
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</TR>
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<TR>
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<TD>FIXC0</TD>
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<TD>INST_RETIRED_ANY (removed due to bad counts)</TD>
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</TR>
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<TR>
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<TD>FIXC1</TD>
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<TD>ACTUAL_CPU_CLOCK or APERF</TD>
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</TR>
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<TR>
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<TD>FIXC2</TD>
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<TD>MAX_CPU_CLOCK or MPERF</TD>
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</TR>
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</TABLE>
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\anchor ZEN5C_PMC
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<H2>General-purpose counters</H2>
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<P>The AMD&reg; Zen5c microarchitecture provides 6 general-purpose counters consisting of a config and a counter register.</P>
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<H3>Counter and events</H3>
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<TABLE>
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<TR>
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<TH>Counter name</TH>
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<TH>Event name</TH>
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</TR>
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<TR>
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<TD>PMC0</TD>
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<TD>*</TD>
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</TR>
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<TR>
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<TD>PMC1</TD>
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<TD>*</TD>
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</TR>
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<TR>
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<TD>PMC2</TD>
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<TD>*</TD>
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</TR>
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<TR>
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<TD>PMC3</TD>
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<TD>*</TD>
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</TR>
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<TR>
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<TD>PMC4</TD>
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<TD>*</TD>
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</TR>
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<TR>
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<TD>PMC5</TD>
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<TD>*</TD>
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</TR>
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</TABLE>
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<H3>Available Options</H3>
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<TABLE>
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<TR>
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<TH>Option</TH>
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<TH>Argument</TH>
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<TH>Description</TH>
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<TH>Comment</TH>
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</TR>
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<TR>
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<TD>edgedetect</TD>
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<TD>N</TD>
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<TD>Set bit 18 in config register</TD>
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<TD></TD>
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</TR>
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<TR>
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<TD>kernel</TD>
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<TD>N</TD>
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<TD>Set bit 17 in config register</TD>
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<TD></TD>
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</TR>
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<TR>
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<TD>threshold</TD>
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<TD>7 bit hex value</TD>
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<TD>Set bits 24-31 in config register</TD>
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<TD>The value for threshold can range between 0x0 and 0x7F</TD>
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</TR>
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<TR>
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<TD>invert</TD>
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<TD>N</TD>
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<TD>Set bit 23 in config register</TD>
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<TD></TD>
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</TR>
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</TABLE>
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<H1>Counters available for one hardware thread per CPU core</H1>
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\anchor ZEN5C_POWER_CORE
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<H2>Power counters</H2>
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<P>The AMD&reg; Zen5c microarchitecture provides measurements of the current power consumption through the RAPL interface.</P>
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<H3>Counter and events</H3>
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<TABLE>
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<TR>
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<TH>Counter name</TH>
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<TH>Event name</TH>
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</TR>
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<TR>
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<TD>PWR0</TD>
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<TD>RAPL_CORE_ENERGY</TD>
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</TR>
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</TABLE>
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<P>There are more energy counters but only one for each L3 segment (aka CCD) (\ref ZEN5C_POWER_SOCKET)</P>
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<H1>Counters available for one hardware thread per shared L3 cache</H1>
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\anchor ZEN5C_CPMC
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<H2>L3 general-purpose counters</H2>
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<P>The AMD&reg; Zen5c microarchitecture provides 6 general-purpose counters for measuring L3 cache events. They consist of a config and a counter register.</P>
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<H3>Counter and events</H3>
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<TABLE>
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<TR>
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<TH>Counter name</TH>
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<TH>Event name</TH>
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</TR>
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<TR>
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<TD>CPMC0</TD>
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<TD>*</TD>
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</TR>
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<TR>
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<TD>CPMC1</TD>
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<TD>*</TD>
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</TR>
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<TR>
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<TD>CPMC2</TD>
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<TD>*</TD>
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</TR>
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<TR>
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<TD>CPMC3</TD>
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<TD>*</TD>
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</TR>
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<TR>
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<TD>CPMC4</TD>
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<TD>*</TD>
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</TR>
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<TR>
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<TD>CPMC5</TD>
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<TD>*</TD>
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</TR>
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</TABLE>
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<H3>Available Options</H3>
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<TABLE>
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<TR>
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<TH>Option</TH>
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<TH>Argument</TH>
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<TH>Description</TH>
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<TH>Comment</TH>
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</TR>
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<TR>
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<TD>tid</TD>
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<TD>8 bit hex value</TD>
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<TD>Set bits 56-63 in config register</TD>
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<TD>Define which CPU thread should be counted. Bits: 0 = Core0-Thread0, 1 = Core0-Thread1, 2 = Core1-Thread0, 3 = Core1-Thread1, ... Default are all threads</TD>
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</TR>
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<TR>
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<TD>cid</TD>
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<TD>3 bit hex value</TD>
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<TD>Set bits 42-45 in config register</TD>
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<TD>Selects which core should be counted. If not specified, the all-cores flag (bit 47) is set</TD>
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</TR>
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<TR>
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<TD>slice</TD>
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<TD>4 bit hex value</TD>
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<TD>Set bits 48-51 in config register</TD>
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<TD>Selects which L3 slice should be counted. If not specified, the all-slices flag (bit 46) is set</TD>
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</TR>
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</TABLE>
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<H1>Counters available for one hardware thread per socket</H1>
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\anchor ZEN5C_POWER_SOCKET
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<H2>Power counters</H2>
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<P>The AMD&reg; Zen5c microarchitecture provides measurements of the current power consumption through the RAPL interface.</P>
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<H3>Counter and events</H3>
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<TABLE>
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<TR>
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<TH>Counter name</TH>
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<TH>Event name</TH>
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</TR>
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<TR>
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<TD>PWR1</TD>
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<TD>RAPL_DRAM_ENERGY</TD>
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</TR>
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</TABLE>
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<P>There are more energy counters for each CPU core (\ref ZEN5C_POWER_CORE)</P>
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\anchor ZEN5C_DATA_FABRIC
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<H2>Data Fabric counters</H2>
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<P>The AMD&reg; Zen5c microarchitecture provides additional Uncore counters for the so-called Data Fabric.</P>
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<H3>Counter and events</H3>
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<TABLE>
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<TR>
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<TH>Counter name</TH>
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<TH>Event name</TH>
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</TR>
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<TR>
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<TD>DFC0</TD>
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<TD>*</TD>
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</TR>
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<TR>
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<TD>DFC1</TD>
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<TD>*</TD>
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</TR>
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<TR>
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<TD>DFC2</TD>
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<TD>*</TD>
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</TR>
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<TR>
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<TD>DFC3</TD>
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<TD>*</TD>
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</TR>
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<TR>
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<TD>DFC4</TD>
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<TD>*</TD>
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</TR>
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<TR>
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<TD>DFC5</TD>
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<TD>*</TD>
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</TR>
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<TR>
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<TD>DFC5</TD>
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<TD>*</TD>
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</TR>
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<TR>
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<TD>DFC6</TD>
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<TD>*</TD>
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</TR>
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<TR>
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<TD>DFC7</TD>
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<TD>*</TD>
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</TR>
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<TR>
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<TD>DFC8</TD>
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<TD>*</TD>
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</TR>
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<TR>
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<TD>DFC9</TD>
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<TD>*</TD>
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</TR>
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<TR>
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<TD>DFC10</TD>
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<TD>*</TD>
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</TR>
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<TR>
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<TD>DFC11</TD>
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<TD>*</TD>
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</TR>
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<TR>
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<TD>DFC12</TD>
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<TD>*</TD>
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</TR>
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<TR>
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<TD>DFC13</TD>
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<TD>*</TD>
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</TR>
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<TR>
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<TD>DFC14</TD>
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<TD>*</TD>
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</TR>
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<TR>
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<TD>DFC15</TD>
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<TD>*</TD>
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</TR>
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</TABLE>
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\anchor ZEN5C_UMC
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<H2>Unified memory controller counters</H2>
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<P>The AMD&reg; Zen5c microarchitecture provides additional Uncore counters at the unified memory controllers (UMC). There are up to 12 memory controllers with up to 5 counters each as the system provides 64 registers in total for all. The exact configuration is system dependent and read at runtime.</P>
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<H3>Counter and events</H3>
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<TABLE>
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<TR>
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<TH>Counter name</TH>
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<TH>Event name</TH>
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</TR>
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<TR>
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<TD>UMC&lt;0-11&gt;C0</TD>
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<TD>*</TD>
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</TR>
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<TR>
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<TD>UMC&lt;0-11&gt;C1</TD>
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<TD>*</TD>
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</TR>
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<TR>
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<TD>UMC&lt;0-11&gt;C2</TD>
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<TD>*</TD>
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</TR>
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<TR>
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<TD>UMC&lt;0-11&gt;C3</TD>
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<TD>*</TD>
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</TR>
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<TR>
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<TD>UMC&lt;0-11&gt;C4</TD>
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<TD>*</TD>
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</TR>
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</TABLE>

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