diff --git a/.github/workflows/action.yml b/.github/workflows/action.yml index 437a845d..c818bf9f 100644 --- a/.github/workflows/action.yml +++ b/.github/workflows/action.yml @@ -57,6 +57,8 @@ jobs: - {RTT_BSP: "Edgi_Talk_M33_Blink_LED"} - {RTT_BSP: "Edgi_Talk_CherryUSB/Edgi_Talk_M33_USB_D"} - {RTT_BSP: "Edgi_Talk_CherryUSB/Edgi_Talk_M33_USB_H"} + - {RTT_BSP: "Edgi_Talk_IPC/Edgi_Talk_M33_IPC"} + - {RTT_BSP: "Edgi_Talk_IPC/Edgi_Talk_M55_IPC"} - {RTT_BSP: "Edgi_Talk_M55_Blink_LED"} - {RTT_BSP: "Edgi_Talk_CherryUSB/Edgi_Talk_M55_USB_D"} - {RTT_BSP: "Edgi_Talk_CherryUSB/Edgi_Talk_M55_USB_H"} diff --git a/README.md b/README.md index 0ca1fbea..abadded5 100644 --- a/README.md +++ b/README.md @@ -33,6 +33,9 @@ $ sdk-bsp-psoc_e84-edgi-talk │ │ ├── Edgi_Talk_M33_USB_H │ │ ├── Edgi_Talk_M55_USB_D │ │ └── Edgi_Talk_M55_USB_H +│ ├── Edgi_Talk_IPC +│ │ ├── Edgi_Talk_M33_IPC +│ │ └── Edgi_Talk_M55_IPC │ ├── Edgi-Talk_CoreMark │ ├── Edgi-Talk_CDC_Echo │ ├── Edgi-Talk_HyperRam diff --git a/README_zh.md b/README_zh.md index a012d7f1..1d8fb257 100644 --- a/README_zh.md +++ b/README_zh.md @@ -33,6 +33,9 @@ $ sdk-bsp-psoc_e84-edgi-talk │ │ ├── Edgi_Talk_M33_USB_H │ │ ├── Edgi_Talk_M55_USB_D │ │ └── Edgi_Talk_M55_USB_H +│ ├── Edgi_Talk_IPC +│ │ ├── Edgi_Talk_M33_IPC +│ │ └── Edgi_Talk_M55_IPC │ ├── Edgi_Talk_CoreMark │ ├── Edgi_Talk_CDC_Echo │ ├── Edgi_Talk_HyperRam diff --git a/libraries/HAL_Drivers/SConscript b/libraries/HAL_Drivers/SConscript index 06ea04a7..fb871541 100644 --- a/libraries/HAL_Drivers/SConscript +++ b/libraries/HAL_Drivers/SConscript @@ -66,6 +66,12 @@ if GetDepend(['RT_USING_DAC']): if GetDepend(['BSP_USING_TIM']): src += ['drv_hwtimer.c'] +if GetDepend(['RT_USING_CAN']): + src += ['drv_canfd.c'] + +if GetDepend(['BSP_USING_IPC']): + src += ['drv_ipc.c'] + path = [cwd] path += [cwd + '/config'] diff --git a/libraries/HAL_Drivers/canfd_config.h b/libraries/HAL_Drivers/canfd_config.h new file mode 100644 index 00000000..4a50850a --- /dev/null +++ b/libraries/HAL_Drivers/canfd_config.h @@ -0,0 +1,95 @@ +/****************************************************************************** + * Copyright 2020-2026 The RT-Thread Development Team. All Rights Reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *****************************************************************************/ + +#ifndef __CANFD_CONFIG_H__ +#define __CANFD_CONFIG_H__ + +#include +#include "board.h" +#include "cy_canfd.h" +#include "cy_sysint.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_CANFD0 +extern const cy_stc_canfd_config_t CYBSP_CAN_FD_CH_0_config; + +static cy_stc_sysint_t CANFD0_IRQ_cfg = +{ + .intrSrc = canfd_0_interrupts0_0_IRQn, + .intrPriority = 3u, +}; +#endif + +#ifdef BSP_USING_CANFD1 +extern const cy_stc_canfd_config_t CANFD1_config; + +static cy_stc_sysint_t CANFD1_IRQ_cfg = +{ + .intrSrc = canfd_1_interrupts0_0_IRQn, + .intrPriority = 3u, +}; +#endif + +/* CANFD0 */ +#if defined(BSP_USING_CANFD0) +#ifndef CANFD0_CONFIG +#define CANFD0_CONFIG \ + { \ + .name = "canfd0", \ + .base = CANFD0, \ + .channel = 0u, \ + .channel_mask = (1u << 0), \ + .mram_delay_us = 6u, \ + .irq = canfd_0_interrupts0_0_IRQn, \ + .irq_cfg = &CANFD0_IRQ_cfg, \ + .isr = RT_NULL, \ + .canfd_config = &CYBSP_CAN_FD_CH_0_config, \ + .test_mode = CY_CANFD_TEST_MODE_DISABLE, \ + .enable_brs = true, \ + .tx_buffer_index = 0u, \ + } +#endif +#endif /* BSP_USING_CANFD0 */ + +/* CANFD1 */ +#if defined(BSP_USING_CANFD1) +#ifndef CANFD1_CONFIG +#define CANFD1_CONFIG \ + { \ + .name = "canfd1", \ + .base = CANFD1, \ + .channel = 0u, \ + .channel_mask = (1u << 0), \ + .mram_delay_us = 6u, \ + .irq = canfd_1_interrupts0_0_IRQn, \ + .irq_cfg = &CANFD1_IRQ_cfg, \ + .isr = RT_NULL, \ + .canfd_config = &CANFD1_config, \ + .test_mode = CY_CANFD_TEST_MODE_DISABLE, \ + .enable_brs = true, \ + .tx_buffer_index = 0u, \ + } +#endif +#endif /* BSP_USING_CANFD1 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CANFD_CONFIG_H__ */ diff --git a/libraries/HAL_Drivers/drv_canfd.c b/libraries/HAL_Drivers/drv_canfd.c new file mode 100644 index 00000000..3dfa1c23 --- /dev/null +++ b/libraries/HAL_Drivers/drv_canfd.c @@ -0,0 +1,524 @@ +/****************************************************************************** + * Copyright 2020-2026 The RT-Thread Development Team. All Rights Reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *****************************************************************************/ + +#include "drv_canfd.h" +#include "canfd_config.h" + +#ifdef RT_USING_CAN + +enum +{ +#ifdef BSP_USING_CANFD0 + CANFD0_INDEX, +#endif +#ifdef BSP_USING_CANFD1 + CANFD1_INDEX, +#endif +}; + +static struct ifx_canfd_config can_config[] = +{ +#ifdef BSP_USING_CANFD0 + CANFD0_CONFIG, +#endif +#ifdef BSP_USING_CANFD1 + CANFD1_CONFIG, +#endif +}; + +static struct ifx_canfd can_obj[sizeof(can_config) / sizeof(can_config[0])] = {0}; + +#define IFX_CANFD_MAX_DATA_LEN (64U) + +#define IFX_CANFD_ERR_MASK (CY_CANFD_RX_FIFO_0_WATERMARK_REACHED | \ + CY_CANFD_RX_FIFO_0_FULL | \ + CY_CANFD_RX_FIFO_0_MSG_LOST | \ + CY_CANFD_RX_FIFO_1_WATERMARK_REACHED | \ + CY_CANFD_RX_FIFO_1_FULL | \ + CY_CANFD_RX_FIFO_1_MSG_LOST | \ + CY_CANFD_TX_FIFO_1_WATERMARK_REACHED | \ + CY_CANFD_TX_FIFO_1_FULL | \ + CY_CANFD_TX_FIFO_1_MSG_LOST | \ + CY_CANFD_TIMESTAMP_WRAPAROUND | \ + CY_CANFD_MRAM_ACCESS_FAILURE | \ + CY_CANFD_TIMEOUT_OCCURRED | \ + CY_CANFD_BIT_ERROR_CORRECTED | \ + CY_CANFD_BIT_ERROR_UNCORRECTED | \ + CY_CANFD_ERROR_LOG_OVERFLOW | \ + CY_CANFD_ERROR_PASSIVE | \ + CY_CANFD_WARNING_STATUS | \ + CY_CANFD_BUS_OFF_STATUS | \ + CY_CANFD_WATCHDOG_INTERRUPT | \ + CY_CANFD_PROTOCOL_ERROR_ARB_PHASE | \ + CY_CANFD_PROTOCOL_ERROR_DATA_PHASE | \ + CY_CANFD_ACCESS_RESERVED_ADDR) + +static uint8_t ifx_canfd_dlc_to_len(uint8_t dlc) +{ + switch (dlc) + { + case 0: return 0; + case 1: return 1; + case 2: return 2; + case 3: return 3; + case 4: return 4; + case 5: return 5; + case 6: return 6; + case 7: return 7; + case 8: return 8; + case 9: return 12; + case 10: return 16; + case 11: return 20; + case 12: return 24; + case 13: return 32; + case 14: return 48; + case 15: return 64; + default: return 0; + } +} + +static uint8_t ifx_canfd_len_to_dlc(uint8_t len) +{ + if (len <= 8) + { + return len; + } + if (len <= 12) + { + return 9; + } + if (len <= 16) + { + return 10; + } + if (len <= 20) + { + return 11; + } + if (len <= 24) + { + return 12; + } + if (len <= 32) + { + return 13; + } + if (len <= 48) + { + return 14; + } + return 15; +} + +static void ifx_canfd_irq_handler(struct ifx_canfd *can) +{ + Cy_CANFD_IrqHandler(can->config->base, can->config->channel, &can->context); +} + +static void ifx_canfd_tx_callback(struct ifx_canfd *can) +{ + rt_hw_can_isr(&can->can_dev, RT_CAN_EVENT_TX_DONE | ((rt_uint32_t)can->config->tx_buffer_index << 8)); +} + +static void ifx_canfd_rx_callback(struct ifx_canfd *can, bool rxFIFOMsg, uint8_t msgBufOrRxFIFONum, + cy_stc_canfd_rx_buffer_t *rxBuffer) +{ + uint8_t data_len; + + can->rx_fifo_msg = rxFIFOMsg; + can->rx_buf_fifo_num = msgBufOrRxFIFONum; + can->rx_id = rxBuffer->r0_f->id; + can->rx_rtr = rxBuffer->r0_f->rtr; + can->rx_xtd = rxBuffer->r0_f->xtd; + + data_len = ifx_canfd_dlc_to_len((uint8_t)rxBuffer->r1_f->dlc); + if (data_len > IFX_CANFD_MAX_DATA_LEN) + { + data_len = IFX_CANFD_MAX_DATA_LEN; + } + can->rx_len = data_len; + + rt_memset(can->rx_data, 0, sizeof(can->rx_data)); + rt_memcpy(can->rx_data, (uint8_t *)rxBuffer->data_area_f, data_len); + can->rx_pending = true; + + rt_hw_can_isr(&can->can_dev, RT_CAN_EVENT_RX_IND | ((rt_uint32_t)msgBufOrRxFIFONum << 8)); + +} + +static void ifx_canfd_error_callback(struct ifx_canfd *can, uint32_t errorMask) +{ + + Cy_CANFD_ClearInterrupt(can->config->base, can->config->channel, errorMask & IFX_CANFD_ERR_MASK); + +} + +#ifdef BSP_USING_CANFD0 +void canfd0_isr_callback(void) +{ + rt_interrupt_enter(); + ifx_canfd_irq_handler(&can_obj[CANFD0_INDEX]); + rt_interrupt_leave(); +} + +static void canfd0_tx_callback(void) +{ + ifx_canfd_tx_callback(&can_obj[CANFD0_INDEX]); +} + +void canfd0_rx_callback(bool rxFIFOMsg, uint8_t msgBufOrRxFIFONum, cy_stc_canfd_rx_buffer_t *rxBuffer) +{ + ifx_canfd_rx_callback(&can_obj[CANFD0_INDEX], rxFIFOMsg, msgBufOrRxFIFONum, rxBuffer); +} + +static void canfd0_error_callback(uint32_t errorMask) +{ + ifx_canfd_error_callback(&can_obj[CANFD0_INDEX], errorMask); +} +#endif + +#ifdef BSP_USING_CANFD1 +void canfd1_isr_callback(void) +{ + rt_interrupt_enter(); + ifx_canfd_irq_handler(&can_obj[CANFD1_INDEX]); + rt_interrupt_leave(); +} + +static void canfd1_tx_callback(void) +{ + ifx_canfd_tx_callback(&can_obj[CANFD1_INDEX]); +} + +void canfd1_rx_callback(bool rxFIFOMsg, uint8_t msgBufOrRxFIFONum, cy_stc_canfd_rx_buffer_t *rxBuffer) +{ + ifx_canfd_rx_callback(&can_obj[CANFD1_INDEX], rxFIFOMsg, msgBufOrRxFIFONum, rxBuffer); +} + +static void canfd1_error_callback(uint32_t errorMask) +{ + ifx_canfd_error_callback(&can_obj[CANFD1_INDEX], errorMask); +} +#endif + +static void ifx_canfd_set_interrupt_mask(struct ifx_canfd *can) +{ + Cy_CANFD_SetInterruptMask(can->config->base, can->config->channel, can->irq_mask); + Cy_CANFD_SetInterruptLine(can->config->base, can->config->channel, CY_CANFD_INTERRUPT_LINE_0_EN); + Cy_CANFD_EnableInterruptLine(can->config->base, can->config->channel, CY_CANFD_INTERRUPT_LINE_0_EN); +} + +static rt_err_t ifx_canfd_configure(struct rt_can_device *can_dev, struct can_configure *cfg) +{ + cy_en_canfd_status_t status; + struct ifx_canfd *can; + + RT_ASSERT(can_dev != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + can = rt_container_of(can_dev, struct ifx_canfd, can_dev); + RT_ASSERT(can != RT_NULL); + RT_ASSERT(can->config != RT_NULL); + RT_ASSERT(can->config->canfd_config != RT_NULL); + + can->user_tx_cb = can->config->canfd_config->txCallback; + can->user_rx_cb = can->config->canfd_config->rxCallback; + can->user_err_cb = can->config->canfd_config->errorCallback; + + Cy_CANFD_EnableMRAM(can->config->base, can->config->channel_mask, can->config->mram_delay_us); + + status = Cy_CANFD_Init(can->config->base, can->config->channel, can->config->canfd_config, &can->context); + if (status != CY_CANFD_SUCCESS) + { + return -RT_ERROR; + } + + can->context.canFDInterruptHandling.canFDTxInterruptFunction = can->tx_cb; + can->context.canFDInterruptHandling.canFDRxInterruptFunction = can->rx_cb; + can->context.canFDInterruptHandling.canFDErrorInterruptFunction = can->err_cb; + + Cy_CANFD_ConfigChangesEnable(can->config->base, can->config->channel); + Cy_CANFD_TestModeConfig(can->config->base, can->config->channel, can->config->test_mode); + Cy_CANFD_ConfigChangesDisable(can->config->base, can->config->channel); + + can->tx_buffer.t0_f = &can->tx_t0; + can->tx_buffer.t1_f = &can->tx_t1; + can->tx_buffer.data_area_f = can->tx_data; + + can->rx_pending = false; + + return RT_EOK; +} + +static rt_err_t ifx_canfd_control(struct rt_can_device *can_dev, int cmd, void *arg) +{ + struct ifx_canfd *can; + rt_uint32_t argval; + + RT_ASSERT(can_dev != RT_NULL); + can = rt_container_of(can_dev, struct ifx_canfd, can_dev); + RT_ASSERT(can != RT_NULL); + RT_ASSERT(can->config != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + argval = (rt_uint32_t)arg; + if (argval & RT_DEVICE_FLAG_INT_RX) + { + can->irq_mask &= ~(CY_CANFD_RX_BUFFER_NEW_MESSAGE | CY_CANFD_RX_FIFO_0_NEW_MESSAGE | CY_CANFD_RX_FIFO_1_NEW_MESSAGE); + } + if (argval & RT_DEVICE_FLAG_INT_TX) + { + can->irq_mask &= ~(CY_CANFD_TRANSMISSION_COMPLETE | CY_CANFD_TRANSMISSION_CANCEL_FINISHED); + } + if (argval & RT_DEVICE_CAN_INT_ERR) + { + can->irq_mask &= ~IFX_CANFD_ERR_MASK; + } + ifx_canfd_set_interrupt_mask(can); + NVIC_ClearPendingIRQ(can->config->irq); + break; + + case RT_DEVICE_CTRL_SET_INT: + argval = (rt_uint32_t)arg; + if (argval & RT_DEVICE_FLAG_INT_RX) + { + can->irq_mask |= (CY_CANFD_RX_BUFFER_NEW_MESSAGE | CY_CANFD_RX_FIFO_0_NEW_MESSAGE | CY_CANFD_RX_FIFO_1_NEW_MESSAGE); + } + if (argval & RT_DEVICE_FLAG_INT_TX) + { + can->irq_mask |= (CY_CANFD_TRANSMISSION_COMPLETE | CY_CANFD_TRANSMISSION_CANCEL_FINISHED); + } + if (argval & RT_DEVICE_CAN_INT_ERR) + { + can->irq_mask |= IFX_CANFD_ERR_MASK; + } + ifx_canfd_set_interrupt_mask(can); + + if ((can->config->irq_cfg == RT_NULL) || (can->config->isr == RT_NULL)) + { + return -RT_ERROR; + } + Cy_SysInt_Init(can->config->irq_cfg, can->config->isr); + NVIC_EnableIRQ(can->config->irq); + break; + + case RT_CAN_CMD_SET_MODE: + argval = (rt_uint32_t)arg; + if (argval == RT_CAN_MODE_NORMAL) + { + Cy_CANFD_ConfigChangesEnable(can->config->base, can->config->channel); + Cy_CANFD_TestModeConfig(can->config->base, can->config->channel, CY_CANFD_TEST_MODE_DISABLE); + Cy_CANFD_ConfigChangesDisable(can->config->base, can->config->channel); + } + else if (argval == RT_CAN_MODE_LISTEN) + { + Cy_CANFD_ConfigChangesEnable(can->config->base, can->config->channel); + Cy_CANFD_TestModeConfig(can->config->base, can->config->channel, CY_CANFD_TEST_MODE_BUS_MONITORING); + Cy_CANFD_ConfigChangesDisable(can->config->base, can->config->channel); + } + else if (argval == RT_CAN_MODE_LOOPBACK) + { + Cy_CANFD_ConfigChangesEnable(can->config->base, can->config->channel); + Cy_CANFD_TestModeConfig(can->config->base, can->config->channel, CY_CANFD_TEST_MODE_INTERNAL_LOOP_BACK); + Cy_CANFD_ConfigChangesDisable(can->config->base, can->config->channel); + } + else + { + return -RT_ERROR; + } + break; + + case RT_CAN_CMD_SET_BAUD: + return -RT_ERROR; + + case RT_CAN_CMD_GET_STATUS: + { + struct rt_can_status *status = (struct rt_can_status *)arg; + if (status != RT_NULL) + { + rt_memset(status, 0, sizeof(*status)); + status->errcode = (rt_uint32_t)Cy_CANFD_GetLastError(can->config->base, can->config->channel); + } + break; + } + + default: + return -RT_ERROR; + } + + return RT_EOK; +} + +static rt_ssize_t ifx_canfd_sendmsg(struct rt_can_device *can_dev, const void *buf, rt_uint32_t boxno) +{ + struct ifx_canfd *can; + struct rt_can_msg *msg_rt = (struct rt_can_msg *)buf; + cy_en_canfd_status_t status; + uint8_t data_len; + + RT_ASSERT(can_dev != RT_NULL); + RT_ASSERT(buf != RT_NULL); + + can = rt_container_of(can_dev, struct ifx_canfd, can_dev); + RT_ASSERT(can != RT_NULL); + + if (boxno != can->config->tx_buffer_index) + { + boxno = can->config->tx_buffer_index; + } + + data_len = msg_rt->len; + if (data_len > IFX_CANFD_MAX_DATA_LEN) + { + return -RT_ERROR; + } + + if ((!can->config->canfd_config->canFDMode) && (data_len > 8)) + { + return -RT_ERROR; + } + + can->tx_t0.id = msg_rt->id; + can->tx_t0.rtr = msg_rt->rtr ? CY_CANFD_RTR_REMOTE_FRAME : CY_CANFD_RTR_DATA_FRAME; + can->tx_t0.xtd = msg_rt->ide ? CY_CANFD_XTD_EXTENDED_ID : CY_CANFD_XTD_STANDARD_ID; + can->tx_t0.esi = CY_CANFD_ESI_ERROR_ACTIVE; + + can->tx_t1.dlc = ifx_canfd_len_to_dlc(data_len); + can->tx_t1.brs = can->config->enable_brs; + can->tx_t1.fdf = can->config->canfd_config->canFDMode ? CY_CANFD_FDF_CAN_FD_FRAME : CY_CANFD_FDF_STANDARD_FRAME; + can->tx_t1.efc = false; + can->tx_t1.mm = 0; + + rt_memset(can->tx_data, 0, sizeof(can->tx_data)); + rt_memcpy((uint8_t *)can->tx_data, msg_rt->data, data_len); + + status = Cy_CANFD_UpdateAndTransmitMsgBuffer(can->config->base, can->config->channel, + &can->tx_buffer, (uint8_t)boxno, &can->context); + if (status != CY_CANFD_SUCCESS) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +static rt_ssize_t ifx_canfd_recvmsg(struct rt_can_device *can_dev, void *buf, rt_uint32_t boxno) +{ + struct ifx_canfd *can; + struct rt_can_msg *msg_rt = (struct rt_can_msg *)buf; + rt_uint8_t copy_len; + + RT_ASSERT(can_dev != RT_NULL); + RT_ASSERT(buf != RT_NULL); + + can = rt_container_of(can_dev, struct ifx_canfd, can_dev); + RT_ASSERT(can != RT_NULL); + + if (!can->rx_pending) + { + return 0; + } + + if (boxno != can->rx_buf_fifo_num) + { + return 0; + } + + msg_rt->id = can->rx_id; + msg_rt->ide = (can->rx_xtd == CY_CANFD_XTD_EXTENDED_ID) ? 1 : 0; + msg_rt->rtr = (can->rx_rtr == CY_CANFD_RTR_REMOTE_FRAME) ? 1 : 0; + msg_rt->rsv = RT_NULL; + msg_rt->len = can->rx_len; + msg_rt->priv = boxno; + msg_rt->hdr_index = RT_NULL; + + copy_len = can->rx_len; + if (copy_len > sizeof(msg_rt->data)) + { + copy_len = sizeof(msg_rt->data); + msg_rt->len = copy_len; + } + + rt_memcpy(msg_rt->data, can->rx_data, copy_len); + can->rx_pending = false; + + return sizeof(struct rt_can_msg); +} + +static const struct rt_can_ops ifx_can_ops = +{ + .configure = ifx_canfd_configure, + .control = ifx_canfd_control, + .sendmsg = ifx_canfd_sendmsg, + .recvmsg = ifx_canfd_recvmsg +}; + +static void ifx_canfd_get_config(void) +{ + struct can_configure config = CANDEFAULTCONFIG; + + for (rt_size_t i = 0; i < (sizeof(can_obj) / sizeof(can_obj[0])); i++) + { + can_obj[i].can_dev.config = config; + can_obj[i].can_dev.config.msgboxsz = 64; + can_obj[i].can_dev.config.sndboxnumber = 1; + can_obj[i].can_dev.config.ticks = 50; + } +} + +int rt_hw_can_init(void) +{ + rt_err_t result = RT_EOK; + rt_size_t obj_num = sizeof(can_obj) / sizeof(struct ifx_canfd); + + ifx_canfd_get_config(); + + for (rt_size_t i = 0; i < obj_num; i++) + { + can_obj[i].config = &can_config[i]; + can_obj[i].can_dev.ops = &ifx_can_ops; + +#ifdef BSP_USING_CANFD0 + if (i == CANFD0_INDEX) + { + can_obj[i].tx_cb = canfd0_tx_callback; + can_obj[i].rx_cb = canfd0_rx_callback; + can_obj[i].err_cb = canfd0_error_callback; + can_obj[i].config->isr = canfd0_isr_callback; + } +#endif + +#ifdef BSP_USING_CANFD1 + if (i == CANFD1_INDEX) + { + can_obj[i].tx_cb = canfd1_tx_callback; + can_obj[i].rx_cb = canfd1_rx_callback; + can_obj[i].err_cb = canfd1_error_callback; + can_obj[i].config->isr = canfd1_isr_callback; + } +#endif + + result = rt_hw_can_register(&can_obj[i].can_dev, can_obj[i].config->name, can_obj[i].can_dev.ops, RT_NULL); + RT_ASSERT(result == RT_EOK); + } + + return result; +} +INIT_PREV_EXPORT(rt_hw_can_init); + +#endif /* RT_USING_CAN */ diff --git a/libraries/HAL_Drivers/drv_canfd.h b/libraries/HAL_Drivers/drv_canfd.h new file mode 100644 index 00000000..5b743352 --- /dev/null +++ b/libraries/HAL_Drivers/drv_canfd.h @@ -0,0 +1,81 @@ +/****************************************************************************** + * Copyright 2020-2026 The RT-Thread Development Team. All Rights Reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *****************************************************************************/ + +#ifndef __DRV_CANFD_H__ +#define __DRV_CANFD_H__ + +#include +#include +#include + +#include "board.h" +#include "cy_canfd.h" +#include "cy_sysint.h" + +#ifdef RT_USING_CAN + +struct ifx_canfd_config +{ + const char *name; + CANFD_Type *base; + uint32_t channel; + uint32_t channel_mask; + uint16_t mram_delay_us; + IRQn_Type irq; + cy_stc_sysint_t *irq_cfg; + cy_israddress isr; + const cy_stc_canfd_config_t *canfd_config; + cy_stc_canfd_test_mode_t test_mode; + bool enable_brs; + uint8_t tx_buffer_index; +}; + +struct ifx_canfd +{ + struct rt_can_device can_dev; + struct ifx_canfd_config *config; + + cy_stc_canfd_context_t context; + uint32_t irq_mask; + + volatile bool rx_pending; + bool rx_fifo_msg; + uint8_t rx_buf_fifo_num; + uint32_t rx_id; + uint8_t rx_len; + cy_en_canfd_rtr_t rx_rtr; + cy_en_canfd_xtd_t rx_xtd; + uint8_t rx_data[64]; + + cy_stc_canfd_t0_t tx_t0; + cy_stc_canfd_t1_t tx_t1; + uint32_t tx_data[CY_CANFD_MESSAGE_DATA_BUFFER_SIZE]; + cy_stc_canfd_tx_buffer_t tx_buffer; + + cy_canfd_tx_msg_func_ptr_t user_tx_cb; + cy_canfd_rx_msg_func_ptr_t user_rx_cb; + cy_canfd_error_func_ptr_t user_err_cb; + + cy_canfd_tx_msg_func_ptr_t tx_cb; + cy_canfd_rx_msg_func_ptr_t rx_cb; + cy_canfd_error_func_ptr_t err_cb; +}; + +int rt_hw_can_init(void); + +#endif /* RT_USING_CAN */ + +#endif /* __DRV_CANFD_H__ */ diff --git a/libraries/HAL_Drivers/drv_ipc.c b/libraries/HAL_Drivers/drv_ipc.c new file mode 100644 index 00000000..3abb77c4 --- /dev/null +++ b/libraries/HAL_Drivers/drv_ipc.c @@ -0,0 +1,364 @@ +/****************************************************************************** + * Copyright 2020-2026 The RT-Thread Development Team. All Rights Reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *****************************************************************************/ +#include +#include +#include + +#include "board.h" +#include "cy_ipc_pipe.h" + +#include "drv_ipc.h" + +#define EDGE_IPC_RX_QUEUE_SIZE (128U) + +#if defined(COMPONENT_CM33) || ((__CORTEX_M) == 33U) + #define EDGE_IPC_LOCAL_EP_ADDR CM33_IPC_PIPE_EP_ADDR + #define EDGE_IPC_PEER_EP_ADDR CM55_IPC_PIPE_EP_ADDR + #define EDGE_IPC_LOCAL_CLIENT_ID CM33_IPC_PIPE_CLIENT_ID + #define EDGE_IPC_TX_INTR_MASK CY_IPC_CYPIPE_INTR_MASK_EP1 + #define EDGE_IPC_LOCAL_CHAN CY_IPC_CHAN_CYPIPE_EP1 + #define EDGE_IPC_LOCAL_INTR CY_IPC_INTR_CYPIPE_EP1 + #define EDGE_IPC_LOCAL_PRIOR CY_IPC_INTR_CYPIPE_PRIOR_EP1 + #define EDGE_IPC_LOCAL_MUX CY_IPC_INTR_CYPIPE_MUX_EP1 + #define EDGE_IPC_PEER_CHAN CY_IPC_CHAN_CYPIPE_EP2 + #define EDGE_IPC_PEER_INTR CY_IPC_INTR_CYPIPE_EP2 + #define EDGE_IPC_PEER_PRIOR CY_IPC_INTR_CYPIPE_PRIOR_EP2 + #define EDGE_IPC_PEER_MUX CY_IPC_INTR_CYPIPE_MUX_EP2 +#elif defined(COMPONENT_CM55) || ((__CORTEX_M) == 55U) + #define EDGE_IPC_LOCAL_EP_ADDR CM55_IPC_PIPE_EP_ADDR + #define EDGE_IPC_PEER_EP_ADDR CM33_IPC_PIPE_EP_ADDR + #define EDGE_IPC_LOCAL_CLIENT_ID CM55_IPC_PIPE_CLIENT_ID + #define EDGE_IPC_TX_INTR_MASK CY_IPC_CYPIPE_INTR_MASK_EP2 + #define EDGE_IPC_LOCAL_CHAN CY_IPC_CHAN_CYPIPE_EP2 + #define EDGE_IPC_LOCAL_INTR CY_IPC_INTR_CYPIPE_EP2 + #define EDGE_IPC_LOCAL_PRIOR CY_IPC_INTR_CYPIPE_PRIOR_EP2 + #define EDGE_IPC_LOCAL_MUX CY_IPC_INTR_CYPIPE_MUX_EP2 + #define EDGE_IPC_PEER_CHAN CY_IPC_CHAN_CYPIPE_EP1 + #define EDGE_IPC_PEER_INTR CY_IPC_INTR_CYPIPE_EP1 + #define EDGE_IPC_PEER_PRIOR CY_IPC_INTR_CYPIPE_PRIOR_EP1 + #define EDGE_IPC_PEER_MUX CY_IPC_INTR_CYPIPE_MUX_EP1 +#else + #error "Unsupported core for edge_ipc_device" +#endif + +struct edge_ipc_device { + struct rt_device parent; + cy_stc_ipc_pipe_ep_t pipe_ep_array[CY_IPC_MAX_ENDPOINTS]; + cy_ipc_pipe_callback_ptr_t cb_array[CY_IPC_CYPIPE_CLIENT_CNT]; + + edge_rc_frame_t rx_queue[EDGE_IPC_RX_QUEUE_SIZE]; + volatile rt_uint16_t rx_head; + volatile rt_uint16_t rx_tail; + + volatile rt_uint32_t tx_pool_idx; + volatile rt_uint32_t stats_tx_ok; + volatile rt_uint32_t stats_tx_err; + volatile rt_uint32_t stats_rx_ok; + volatile rt_uint32_t stats_rx_err; + volatile rt_uint32_t stats_rx_drop; + volatile rt_uint32_t stats_sema_fail; + + rt_bool_t initialized; +}; + +static struct edge_ipc_device g_edge_ipc_dev; +CY_SECTION_SHAREDMEM static edge_rc_frame_t g_edge_ipc_tx_pool[EDGE_IPC_FRAME_POOL_SIZE]; + +static rt_bool_t edge_ipc_lock_sema(void) +{ + uint32_t retry = 0; + + while (retry++ < EDGE_IPC_SEMA_RETRY_MAX) { + if (Cy_IPC_Sema_Set(IPC_DEMO_SEMA_NUM, false) == CY_IPC_SEMA_SUCCESS) { + return RT_TRUE; + } + } + + return RT_FALSE; +} + +static void edge_ipc_unlock_sema(void) +{ + (void)Cy_IPC_Sema_Clear(IPC_DEMO_SEMA_NUM, false); +} + +static rt_bool_t edge_ipc_rx_queue_push(struct edge_ipc_device* dev, const edge_rc_frame_t* frame) +{ + rt_base_t level; + rt_uint16_t next; + + level = rt_hw_interrupt_disable(); + next = (rt_uint16_t)((dev->rx_head + 1U) % EDGE_IPC_RX_QUEUE_SIZE); + + if (next == dev->rx_tail) { + rt_hw_interrupt_enable(level); + return RT_FALSE; + } + + dev->rx_queue[dev->rx_head] = *frame; + dev->rx_head = next; + rt_hw_interrupt_enable(level); + + return RT_TRUE; +} + +static rt_bool_t edge_ipc_rx_queue_pop(struct edge_ipc_device* dev, edge_rc_frame_t* frame) +{ + rt_base_t level; + + level = rt_hw_interrupt_disable(); + + if (dev->rx_tail == dev->rx_head) { + rt_hw_interrupt_enable(level); + return RT_FALSE; + } + + *frame = dev->rx_queue[dev->rx_tail]; + dev->rx_tail = (rt_uint16_t)((dev->rx_tail + 1U) % EDGE_IPC_RX_QUEUE_SIZE); + + rt_hw_interrupt_enable(level); + return RT_TRUE; +} + +static void edge_ipc_pipe_isr(void) +{ + Cy_IPC_Pipe_ExecuteCallback(EDGE_IPC_LOCAL_EP_ADDR); +} + +static void edge_ipc_rx_callback(uint32_t* msg_data) +{ + struct edge_ipc_device* dev = &g_edge_ipc_dev; + edge_rc_frame_t* rx = (edge_rc_frame_t*)msg_data; + + if (rx == RT_NULL) { + dev->stats_rx_err++; + return; + } + + if (rx->client_id != EDGE_IPC_LOCAL_CLIENT_ID + || rx->magic != RC_MAGIC_WORD + || edge_rc_checksum(rx) != rx->checksum) { + dev->stats_rx_err++; + return; + } + + if (!edge_ipc_rx_queue_push(dev, rx)) { + dev->stats_rx_drop++; + return; + } + + dev->stats_rx_ok++; + + if (dev->parent.rx_indicate) { + dev->parent.rx_indicate(&dev->parent, 1); + } +} + +static rt_err_t edge_ipc_hw_init(struct edge_ipc_device* dev) +{ + cy_en_ipc_pipe_status_t status; + cy_stc_ipc_pipe_config_t ipc_config = { + { .ipcNotifierNumber = EDGE_IPC_LOCAL_INTR, + .ipcNotifierPriority = EDGE_IPC_LOCAL_PRIOR, + .ipcNotifierMuxNumber = EDGE_IPC_LOCAL_MUX, + .epAddress = EDGE_IPC_LOCAL_EP_ADDR, + { .epChannel = EDGE_IPC_LOCAL_CHAN, + .epIntr = EDGE_IPC_LOCAL_INTR, + .epIntrmask = CY_IPC_CYPIPE_INTR_MASK } }, + { .ipcNotifierNumber = EDGE_IPC_PEER_INTR, + .ipcNotifierPriority = EDGE_IPC_PEER_PRIOR, + .ipcNotifierMuxNumber = EDGE_IPC_PEER_MUX, + .epAddress = EDGE_IPC_PEER_EP_ADDR, + { .epChannel = EDGE_IPC_PEER_CHAN, + .epIntr = EDGE_IPC_PEER_INTR, + .epIntrmask = CY_IPC_CYPIPE_INTR_MASK } }, + .endpointClientsCount = CY_IPC_CYPIPE_CLIENT_CNT, + .endpointsCallbacksArray = RT_NULL, + .userPipeIsrHandler = &edge_ipc_pipe_isr + }; + + ipc_config.endpointsCallbacksArray = dev->cb_array; + + Cy_IPC_Pipe_Config(dev->pipe_ep_array); + Cy_IPC_Pipe_Init(&ipc_config); + + status = Cy_IPC_Pipe_RegisterCallback(EDGE_IPC_LOCAL_EP_ADDR, + &edge_ipc_rx_callback, + (uint32_t)EDGE_IPC_LOCAL_CLIENT_ID); + + if (status != CY_IPC_PIPE_SUCCESS) { + return -RT_ERROR; + } + + dev->initialized = RT_TRUE; + return RT_EOK; +} + +static rt_err_t edge_ipc_dev_init(rt_device_t rt_dev) +{ + struct edge_ipc_device* dev = (struct edge_ipc_device*)rt_dev; + + if (dev->initialized) { + return RT_EOK; + } + + return edge_ipc_hw_init(dev); +} + +static rt_err_t edge_ipc_dev_open(rt_device_t rt_dev, rt_uint16_t oflag) +{ + (void)rt_dev; + (void)oflag; + return RT_EOK; +} + +static rt_err_t edge_ipc_dev_close(rt_device_t rt_dev) +{ + (void)rt_dev; + return RT_EOK; +} + +static rt_ssize_t edge_ipc_dev_read(rt_device_t rt_dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + struct edge_ipc_device* dev = (struct edge_ipc_device*)rt_dev; + edge_rc_frame_t* frame = (edge_rc_frame_t*)buffer; + rt_size_t read_cnt = 0; + + (void)pos; + + if (buffer == RT_NULL || size == 0) { + return 0; + } + + while (read_cnt < size) { + if (!edge_ipc_rx_queue_pop(dev, &frame[read_cnt])) { + break; + } + read_cnt++; + } + + return read_cnt; +} + +static rt_ssize_t edge_ipc_dev_write(rt_device_t rt_dev, rt_off_t pos, const void* buffer, rt_size_t size) +{ + struct edge_ipc_device* dev = (struct edge_ipc_device*)rt_dev; + const edge_rc_frame_t* frame = (const edge_rc_frame_t*)buffer; + rt_size_t write_cnt = 0; + cy_en_ipc_pipe_status_t status; + + (void)pos; + + if (buffer == RT_NULL || size == 0) { + return 0; + } + + while (write_cnt < size) { + edge_rc_frame_t* tx; + rt_uint32_t slot = dev->tx_pool_idx++ % EDGE_IPC_FRAME_POOL_SIZE; + + tx = &g_edge_ipc_tx_pool[slot]; + *tx = frame[write_cnt]; + tx->client_id = EDGE_IPC_LOCAL_CLIENT_ID == CM33_IPC_PIPE_CLIENT_ID ? CM55_IPC_PIPE_CLIENT_ID : CM33_IPC_PIPE_CLIENT_ID; + tx->intr_mask = (rt_uint16_t)EDGE_IPC_TX_INTR_MASK; + tx->magic = RC_MAGIC_WORD; + tx->checksum = edge_rc_checksum(tx); + + if (!edge_ipc_lock_sema()) { + dev->stats_sema_fail++; + break; + } + + status = Cy_IPC_Pipe_SendMessage(EDGE_IPC_PEER_EP_ADDR, + EDGE_IPC_LOCAL_EP_ADDR, + (void*)tx, + 0UL); + edge_ipc_unlock_sema(); + + if (status != CY_IPC_PIPE_SUCCESS) { + dev->stats_tx_err++; + break; + } + + dev->stats_tx_ok++; + write_cnt++; + } + + return write_cnt; +} + +static rt_err_t edge_ipc_dev_control(rt_device_t rt_dev, int cmd, void* args) +{ + struct edge_ipc_device* dev = (struct edge_ipc_device*)rt_dev; + + if (cmd == EDGE_IPC_CTRL_GET_STATS) { + edge_ipc_device_stats_t* stats = (edge_ipc_device_stats_t*)args; + + if (stats == RT_NULL) { + return -RT_EINVAL; + } + + stats->tx_ok = dev->stats_tx_ok; + stats->tx_err = dev->stats_tx_err; + stats->rx_ok = dev->stats_rx_ok; + stats->rx_err = dev->stats_rx_err; + stats->rx_drop = dev->stats_rx_drop; + stats->sema_fail = dev->stats_sema_fail; + + return RT_EOK; + } + + return -RT_ENOSYS; +} + +#ifdef RT_USING_DEVICE_OPS +static const struct rt_device_ops edge_ipc_dev_ops = { + edge_ipc_dev_init, + edge_ipc_dev_open, + edge_ipc_dev_close, + edge_ipc_dev_read, + edge_ipc_dev_write, + edge_ipc_dev_control +}; +#endif + +rt_device_t edge_ipc_device_find(void) +{ + return rt_device_find(EDGE_IPC_DEVICE_NAME); +} + +int edge_ipc_device_register(void) +{ + struct edge_ipc_device* dev = &g_edge_ipc_dev; + + rt_memset(dev, 0, sizeof(*dev)); + +#ifdef RT_USING_DEVICE_OPS + dev->parent.ops = &edge_ipc_dev_ops; +#else + dev->parent.init = edge_ipc_dev_init; + dev->parent.open = edge_ipc_dev_open; + dev->parent.close = edge_ipc_dev_close; + dev->parent.read = edge_ipc_dev_read; + dev->parent.write = edge_ipc_dev_write; + dev->parent.control = edge_ipc_dev_control; +#endif + + return rt_device_register(&dev->parent, + EDGE_IPC_DEVICE_NAME, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); +} +INIT_PREV_EXPORT(edge_ipc_device_register); diff --git a/libraries/HAL_Drivers/drv_ipc.h b/libraries/HAL_Drivers/drv_ipc.h new file mode 100644 index 00000000..0aa69366 --- /dev/null +++ b/libraries/HAL_Drivers/drv_ipc.h @@ -0,0 +1,46 @@ +/****************************************************************************** + * Copyright 2020-2026 The RT-Thread Development Team. All Rights Reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *****************************************************************************/ +#ifndef DRV_IPC_H +#define DRV_IPC_H + +#include "ipc_common.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define EDGE_IPC_DEVICE_NAME "ipc0" +#define EDGE_IPC_CTRL_GET_STATS (0x1000) + +typedef struct +{ + rt_uint32_t tx_ok; + rt_uint32_t tx_err; + rt_uint32_t rx_ok; + rt_uint32_t rx_err; + rt_uint32_t rx_drop; + rt_uint32_t sema_fail; +} edge_ipc_device_stats_t; + +rt_device_t edge_ipc_device_find(void); +int edge_ipc_device_register(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/HAL_Drivers/drv_spi.c b/libraries/HAL_Drivers/drv_spi.c index 5bb852fd..fc2fb7e0 100644 --- a/libraries/HAL_Drivers/drv_spi.c +++ b/libraries/HAL_Drivers/drv_spi.c @@ -1,293 +1,245 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team +/****************************************************************************** + * Copyright 2020-2026 The RT-Thread Development Team. All Rights Reserved. * - * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at * - * Change Logs: - * Date Author Notes - * 2022-07-18 Rbb666 first version - * 2023-03-30 Rbb666 update spi driver - */ + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *****************************************************************************/ -#include +#include "drv_spi.h" -#ifdef RT_USING_SPI +#ifdef BSP_USING_SPI +#include +#include +#include "cy_scb_spi.h" +#include "cy_sysint.h" +#include "mtb_hal_spi.h" -//#define DRV_DEBUG -#define DBG_TAG "drv.spi" -#ifdef DRV_DEBUG - #define DBG_LVL DBG_LOG -#else - #define DBG_LVL DBG_INFO -#endif /* DRV_DEBUG */ -#include +#define GET_PIN(PORTx, PIN) ((((uint8_t)(PORTx)) << 3U) + ((uint8_t)(PIN))) +#define INT_PRIORITY 7u + +struct ifx_spi { + struct rt_spi_bus spi_bus; + const char* name; + + CySCB_Type* base; + cy_stc_scb_spi_config_t runtime_cfg; + const cy_stc_scb_spi_config_t* default_cfg; + const mtb_hal_spi_configurator_t* hal_cfg; + cy_stc_scb_spi_context_t* context; + mtb_hal_spi_t spi_obj; + + uint16_t cs_pin; + + cy_stc_sysint_t intr_cfg; + + uint32_t freq; + struct rt_completion cpt; +}; -#ifdef BSP_USING_SPI0 - static struct rt_spi_bus spi_bus0; -#endif #ifdef BSP_USING_SPI1 - static struct rt_spi_bus spi_bus1; - cy_stc_scb_spi_context_t scb_9_spi_context; -#endif -#ifdef BSP_USING_SPI3 - static struct rt_spi_bus spi_bus3; -#endif -#ifdef BSP_USING_SPI6 - static struct rt_spi_bus spi_bus6; -#endif +static cy_stc_scb_spi_context_t scb_9_spi_context; -static struct ifx_spi_handle spi_bus_obj[] = -{ -#if defined(BSP_USING_SPI0) - { - .bus_name = "spi0", - .sck_pin = GET_PIN(15, 0), - .miso_pin = GET_PIN(15, 2), - .mosi_pin = GET_PIN(15, 1), - }, -#endif -#if defined(BSP_USING_SPI1) - { +extern const cy_stc_scb_spi_config_t CYBSP_SPI_9_config; +extern const mtb_hal_spi_configurator_t CYBSP_SPI_9_hal_config; - .bus_name = "spi1", - .sck_pin = GET_PIN(15, 0), - .miso_pin = GET_PIN(15, 2), - .mosi_pin = GET_PIN(15, 1), +#define scb_9_HW SCB9 +#define scb_9_IRQ scb_9_interrupt_IRQn - .base = scb_9_HW, - .cy_stc_scb_spi_config = &scb_9_config, - .mtb_hal_spi_configurator = &scb_9_hal_config, - .context = &scb_9_spi_context, - .intr_cfg = {.intrSrc = scb_9_IRQ, .intrPriority = INT_PRIORITY }, - }, -#endif -#if defined(BSP_USING_SPI2) - { - .bus_name = "spi2", - .sck_pin = GET_PIN(8, 0), - .miso_pin = GET_PIN(8, 4), - .mosi_pin = GET_PIN(8, 1), - }, +#ifndef BSP_SPI1_CS_PIN +#define BSP_SPI1_CS_PIN GET_PIN(15, 3) #endif -#if defined(BSP_USING_SPI3) - { - .bus_name = "spi3", - .sck_pin = GET_PIN(6, 2), - .miso_pin = GET_PIN(6, 1), - .mosi_pin = GET_PIN(6, 0), - }, #endif -#if defined(BSP_USING_SPI6) + +static struct ifx_spi ifx_spi_obj[] = { +#ifdef BSP_USING_SPI1 { - .bus_name = "spi6", - .sck_pin = GET_PIN(12, 2), - .miso_pin = GET_PIN(12, 1), - .mosi_pin = GET_PIN(12, 0), + .name = "spi1", + .base = scb_9_HW, + .default_cfg = &CYBSP_SPI_9_config, + .hal_cfg = &CYBSP_SPI_9_hal_config, + .context = &scb_9_spi_context, + .cs_pin = BSP_SPI1_CS_PIN, + .intr_cfg = { .intrSrc = scb_9_IRQ, .intrPriority = INT_PRIORITY }, }, #endif }; -static struct ifx_spi spi_config[sizeof(spi_bus_obj) / sizeof(spi_bus_obj[0])] = {0}; - -/* private rt-thread spi ops function */ -static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration); -static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message); - -static struct rt_spi_ops ifx_spi_ops = +static void ifx_spi_set_cs(struct ifx_spi* spi, rt_base_t level) { - .configure = spi_configure, - .xfer = spixfer, -}; - + RT_ASSERT(spi); + rt_pin_write(spi->cs_pin, level); +} -static void spi_interrupt_callback() +static void ifx_spi_irq_handler_generic(struct ifx_spi* spi) { rt_interrupt_enter(); - mtb_hal_spi_process_interrupt(spi_bus_obj[0].spi_obj); + mtb_hal_spi_process_interrupt(&spi->spi_obj); + + if (!mtb_hal_spi_is_busy(&spi->spi_obj)) { + rt_completion_done(&spi->cpt); + } rt_interrupt_leave(); } - -static void spi_event_handler(void* handler_arg, mtb_hal_spi_event_t event) +#ifdef BSP_USING_SPI1 +static void ifx_spi1_irq_handler(void) { - rt_kprintf("spi event handler\n"); + ifx_spi_irq_handler_generic(&ifx_spi_obj[0]); } +#endif - -static void ifx_spi_init(struct ifx_spi *spi_device) +static rt_err_t ifx_hw_spi_init(struct ifx_spi* spi) { - RT_ASSERT(spi_device != RT_NULL); - - rt_err_t result = RT_EOK; - - static uint8_t init_flag = 1; - - if (init_flag) - { - - result = Cy_SCB_SPI_Init(spi_device->spi_handle_t->base, spi_device->spi_handle_t->cy_stc_scb_spi_config, spi_device->spi_handle_t->context); - Cy_SCB_SPI_Enable(spi_device->spi_handle_t->base); - result = mtb_hal_spi_setup(spi_device->spi_handle_t->spi_obj, spi_device->spi_handle_t->mtb_hal_spi_configurator, spi_device->spi_handle_t->context, NULL); - Cy_SCB_SPI_SetActiveSlaveSelect(spi_device->spi_handle_t->base, CY_SCB_SPI_SLAVE_SELECT0); + RT_ASSERT(spi); - if (result != RT_EOK) - { - LOG_E("spi%s init fail", spi_device->spi_handle_t->bus_name); - return; - } + /* Configure CS pin as output, set high (inactive) */ + rt_pin_mode(spi->cs_pin, PIN_MODE_OUTPUT); + ifx_spi_set_cs(spi, PIN_HIGH); - Cy_SysInt_Init(&(spi_device->spi_handle_t->intr_cfg), spi_interrupt_callback); - NVIC_EnableIRQ(spi_device->spi_handle_t->intr_cfg.intrSrc); + spi->runtime_cfg = *spi->default_cfg; + if (Cy_SCB_SPI_Init(spi->base, &spi->runtime_cfg, spi->context) != CY_SCB_SPI_SUCCESS) + return -RT_ERROR; + Cy_SCB_SPI_Enable(spi->base); - result = mtb_hal_spi_set_frequency(spi_device->spi_handle_t->spi_obj, spi_device->spi_handle_t->freq); - if (result != CY_RSLT_SUCCESS) - { - LOG_E("%s set frequency fail", spi_device->spi_handle_t->bus_name); - return; - } - LOG_I("[%s] freq:[%d]HZ", spi_device->spi_handle_t->bus_name, spi_device->spi_handle_t->freq); + if (mtb_hal_spi_setup(&spi->spi_obj, spi->hal_cfg, spi->context, NULL) != CY_RSLT_SUCCESS) + return -RT_ERROR; - /* Register a callback function to be called when the interrupt fires */ - mtb_hal_spi_register_callback(spi_device->spi_handle_t->spi_obj, (mtb_hal_spi_event_callback_t)spi_event_handler, NULL); + cy_israddress isr_func = RT_NULL; + if (rt_strcmp(spi->name, "spi1") == 0) + isr_func = ifx_spi1_irq_handler; - /* Enable the events that will trigger the call back function */ - mtb_hal_spi_enable_event(spi_device->spi_handle_t->spi_obj, MTB_HAL_SPI_IRQ_DONE, true); + if (isr_func) { + Cy_SysInt_Init(&spi->intr_cfg, isr_func); + NVIC_EnableIRQ(spi->intr_cfg.intrSrc); } - init_flag = 0; + rt_completion_init(&spi->cpt); + spi->freq = 1000000; + if (mtb_hal_spi_set_frequency(&spi->spi_obj, spi->freq) != CY_RSLT_SUCCESS) + return -RT_ERROR; + + return RT_EOK; } -static rt_err_t spi_configure(struct rt_spi_device *device, - struct rt_spi_configuration *configuration) +static rt_err_t spi_configure(struct rt_spi_device* device, struct rt_spi_configuration* cfg) { - RT_ASSERT(device != RT_NULL); - RT_ASSERT(configuration != RT_NULL); + RT_ASSERT(device); + RT_ASSERT(cfg); - struct ifx_spi *spi_device = rt_container_of(device->bus, struct ifx_spi, spi_bus); + struct ifx_spi* spi = rt_container_of(device->bus, struct ifx_spi, spi_bus); - /* data_width */ - if (configuration->data_width <= 8) - { - spi_device->spi_handle_t->spi_obj->data_bits = 8; - } - else if (configuration->data_width <= 16) - { - spi_device->spi_handle_t->spi_obj->data_bits = 16; - } - else - { - return -RT_EIO; - } + if (cfg->data_width == 0 || cfg->data_width > 16) + return -RT_EINVAL; - uint32_t max_hz; - max_hz = configuration->max_hz; - spi_device->spi_handle_t->freq = max_hz; + spi->spi_obj.data_bits = (cfg->data_width <= 8) ? 8 : 16; + spi->freq = cfg->max_hz; + if (mtb_hal_spi_set_frequency(&spi->spi_obj, spi->freq) != CY_RSLT_SUCCESS) + return -RT_ERROR; - /* MSB or LSB */ - switch (configuration->mode & RT_SPI_MODE_3) - { + spi->runtime_cfg.enableMsbFirst = ((cfg->mode & RT_SPI_MSB) == RT_SPI_MSB) ? true : false; + + switch (cfg->mode & RT_SPI_MODE_3) { case RT_SPI_MODE_0: - spi_device->spi_handle_t->cy_stc_scb_spi_config->sclkMode = CY_SCB_SPI_CPHA0_CPOL0; + spi->runtime_cfg.sclkMode = CY_SCB_SPI_CPHA0_CPOL0; break; case RT_SPI_MODE_1: - spi_device->spi_handle_t->cy_stc_scb_spi_config->sclkMode = CY_SCB_SPI_CPHA0_CPOL1; + spi->runtime_cfg.sclkMode = CY_SCB_SPI_CPHA1_CPOL0; break; case RT_SPI_MODE_2: - spi_device->spi_handle_t->cy_stc_scb_spi_config->sclkMode = CY_SCB_SPI_CPHA1_CPOL0; + spi->runtime_cfg.sclkMode = CY_SCB_SPI_CPHA0_CPOL1; break; case RT_SPI_MODE_3: - spi_device->spi_handle_t->cy_stc_scb_spi_config->sclkMode = CY_SCB_SPI_CPHA1_CPOL1; + spi->runtime_cfg.sclkMode = CY_SCB_SPI_CPHA1_CPOL1; break; } - ifx_spi_init(spi_device); + + Cy_SCB_SPI_Disable(spi->base, spi->context); + if (Cy_SCB_SPI_Init(spi->base, &spi->runtime_cfg, spi->context) != CY_SCB_SPI_SUCCESS) { + rt_kprintf("Cy_SCB_SPI_Init fail!!\n"); + return -RT_ERROR; + } + + Cy_SCB_SPI_Enable(spi->base); return RT_EOK; } -static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) +static rt_ssize_t spixfer(struct rt_spi_device* device, struct rt_spi_message* message) { - struct ifx_spi *spi_device = rt_container_of(device->bus, struct ifx_spi, spi_bus); + RT_ASSERT(device); + RT_ASSERT(message); - if (message->cs_take && !(device->config.mode & RT_SPI_NO_CS) && (device->cs_pin != PIN_NONE)) - { - rt_pin_write(device->cs_pin, (device->config.mode & RT_SPI_CS_HIGH) ? PIN_HIGH : PIN_LOW); - } - - int result = RT_EOK; - if (message->length > 0) - { - result = mtb_hal_spi_transfer(spi_device->spi_handle_t->spi_obj, message->send_buf, message->length, message->recv_buf, message->length, 0); - if (result != RT_EOK) - { - rt_kprintf("spi transfer failed.\n"); - } - } + struct ifx_spi* spi = rt_container_of(device->bus, struct ifx_spi, spi_bus); + cy_rslt_t result = CY_RSLT_SUCCESS; + rt_err_t wait_ret = RT_EOK; - if (message->cs_release && !(device->config.mode & RT_SPI_NO_CS) && (device->cs_pin != PIN_NONE)) - { - rt_pin_write(device->cs_pin, (device->config.mode & RT_SPI_CS_HIGH) ? PIN_LOW : PIN_HIGH); + if (message->cs_take && !(device->config.mode & RT_SPI_NO_CS)) { + ifx_spi_set_cs(spi, (device->config.mode & RT_SPI_CS_HIGH) ? PIN_HIGH : PIN_LOW); } - return (result == RT_EOK) ? message->length : -RT_ERROR; -} -/** - * Attach the spi device to SPI bus, this function must be used after initialization. - */ -rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin) -{ - RT_ASSERT(bus_name != RT_NULL); - RT_ASSERT(device_name != RT_NULL); - - rt_err_t result; - struct rt_spi_device *spi_device; + if (message->length > 0) { + if (message->send_buf == RT_NULL && message->recv_buf == RT_NULL) { + result = (cy_rslt_t)-RT_EINVAL; + goto __exit; + } - /* attach the device to spi bus*/ - spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); - RT_ASSERT(spi_device != RT_NULL); + mtb_hal_spi_clear(&spi->spi_obj); + rt_completion_init(&spi->cpt); - result = rt_spi_bus_attach_device_cspin(spi_device, device_name, bus_name, cs_pin, RT_NULL); - if (result != RT_EOK) - { - LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result); + if (message->send_buf == RT_NULL && message->recv_buf != RT_NULL) { + result = mtb_hal_spi_transfer(&spi->spi_obj, RT_NULL, 0x00, message->recv_buf, message->length, 0x00); + } else if (message->send_buf != RT_NULL && message->recv_buf == RT_NULL) { + result = mtb_hal_spi_transfer(&spi->spi_obj, message->send_buf, message->length, RT_NULL, 0x00, 0x00); + } else if (message->send_buf != RT_NULL && message->recv_buf != RT_NULL) { + result = mtb_hal_spi_transfer(&spi->spi_obj, message->send_buf, message->length, message->recv_buf, message->length, 0x00); + } + if (result == CY_RSLT_SUCCESS) { + wait_ret = rt_completion_wait(&spi->cpt, RT_WAITING_FOREVER); + } } - RT_ASSERT(result == RT_EOK); +__exit: + if (message->cs_release && !(device->config.mode & RT_SPI_NO_CS)) { + ifx_spi_set_cs(spi, (device->config.mode & RT_SPI_CS_HIGH) ? PIN_LOW : PIN_HIGH); + } - LOG_D("%s attach to %s done", device_name, bus_name); + if (result != CY_RSLT_SUCCESS || wait_ret != RT_EOK) + return 0; - return result; + return message->length; } -int rt_hw_spi_init(void) -{ - int result = RT_EOK; - - for (int spi_index = 0; spi_index < sizeof(spi_bus_obj) / sizeof(spi_bus_obj[0]); spi_index++) - { - spi_bus_obj[spi_index].spi_obj = rt_malloc(sizeof(mtb_hal_spi_t)); - RT_ASSERT(spi_bus_obj[spi_index].spi_obj != RT_NULL); +static const struct rt_spi_ops ifx_spi_ops = { + .configure = spi_configure, + .xfer = spixfer, +}; - spi_config[spi_index].spi_handle_t = &spi_bus_obj[spi_index]; +static int rt_hw_spi_init(void) +{ + for (int i = 0; i < sizeof(ifx_spi_obj) / sizeof(ifx_spi_obj[0]); i++) { + struct ifx_spi* obj = &ifx_spi_obj[i]; - rt_err_t err = rt_spi_bus_register(&spi_config[spi_index].spi_bus, spi_bus_obj[spi_index].bus_name, &ifx_spi_ops); - if (RT_EOK != err) - { - LOG_E("%s bus register failed.", spi_config[spi_index].spi_handle_t->bus_name); + if (ifx_hw_spi_init(obj) == RT_EOK) { + if (rt_spi_bus_register(&obj->spi_bus, obj->name, &ifx_spi_ops) != RT_EOK) + return -RT_ERROR; + } else { return -RT_ERROR; } - - LOG_D("MOSI PIN:[%d], MISO PIN[%d], CLK PIN[%d]\n", - spi_bus_obj[spi_index].mosi_pin, spi_bus_obj[spi_index].miso_pin, - spi_bus_obj[spi_index].sck_pin); - - /* initialize completion object */ - rt_completion_init(&spi_config[spi_index].cpt); } - - return result; + return RT_EOK; } INIT_BOARD_EXPORT(rt_hw_spi_init); -#endif /* RT_USING_SPI */ + +#endif /* BSP_USING_SPI */ diff --git a/libraries/HAL_Drivers/drv_spi.h b/libraries/HAL_Drivers/drv_spi.h index 78f58f5f..2c53245f 100644 --- a/libraries/HAL_Drivers/drv_spi.h +++ b/libraries/HAL_Drivers/drv_spi.h @@ -1,51 +1,33 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team +/****************************************************************************** + * Copyright 2020-2026 RT-Thread Development Team. All Rights Reserved. * - * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at * - * Change Logs: - * Date Author Notes - * 2022-07-18 Rbb666 first version - */ - -#ifndef __DRV_SPI__ -#define __DRV_SPI__ + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *****************************************************************************/ +#ifndef DRV_SPI_H__ +#define DRV_SPI_H__ #include #include -#include "drv_gpio.h" - -#define INT_PRIORITY 7u - -struct ifx_spi_handle -{ - const char *bus_name; - mtb_hal_spi_t *spi_obj; - - uint16_t sck_pin; - uint16_t miso_pin; - uint16_t mosi_pin; - uint32_t freq; +#include "board.h" - CySCB_Type *base; - cy_stc_scb_spi_config_t *cy_stc_scb_spi_config; - mtb_hal_spi_configurator_t *mtb_hal_spi_configurator; - cy_stc_scb_spi_context_t *context; - cy_stc_sysint_t intr_cfg; -}; - -/* ifx spi dirver class */ -struct ifx_spi -{ - rt_uint32_t cs_pin; - - struct ifx_spi_handle *spi_handle_t; - struct rt_spi_configuration *rt_spi_cfg_t; - struct rt_spi_bus spi_bus; - - struct rt_completion cpt; -}; +#ifdef __cplusplus +extern "C" { +#endif -rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin); +rt_err_t drv_spi_init(void); +#ifdef __cplusplus +} #endif + +#endif /* DRV_SPI_H__ */ diff --git a/libraries/HAL_Drivers/ipc_common.h b/libraries/HAL_Drivers/ipc_common.h new file mode 100644 index 00000000..6677d1d6 --- /dev/null +++ b/libraries/HAL_Drivers/ipc_common.h @@ -0,0 +1,83 @@ +/****************************************************************************** + * Copyright 2020-2026 The RT-Thread Development Team. All Rights Reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *****************************************************************************/ +#ifndef EDGE_IPC_COMMON_H +#define EDGE_IPC_COMMON_H + +#include "cy_ipc_pipe.h" + +#define CY_IPC_MAX_ENDPOINTS (5UL) +#define CY_IPC_CYPIPE_CLIENT_CNT (8UL) + +#define CY_IPC_CHAN_CYPIPE_EP1 (4UL) +#define CY_IPC_INTR_CYPIPE_EP1 (4UL) +#define CY_IPC_CHAN_CYPIPE_EP2 (15UL) +#define CY_IPC_INTR_CYPIPE_EP2 (5UL) + +#define CY_IPC_CYPIPE_CHAN_MASK_EP1 CY_IPC_CH_MASK(CY_IPC_CHAN_CYPIPE_EP1) +#define CY_IPC_CYPIPE_INTR_MASK_EP1 CY_IPC_INTR_MASK(CY_IPC_INTR_CYPIPE_EP1) +#define CY_IPC_INTR_CYPIPE_PRIOR_EP1 (1UL) +#define CY_IPC_INTR_CYPIPE_MUX_EP1 (CY_IPC0_INTR_MUX(CY_IPC_INTR_CYPIPE_EP1)) +#define CM33_IPC_PIPE_EP_ADDR (1UL) +#define CM33_IPC_PIPE_CLIENT_ID (3UL) + +#define CY_IPC_CYPIPE_CHAN_MASK_EP2 CY_IPC_CH_MASK(CY_IPC_CHAN_CYPIPE_EP2) +#define CY_IPC_CYPIPE_INTR_MASK_EP2 CY_IPC_INTR_MASK(CY_IPC_INTR_CYPIPE_EP2) +#define CY_IPC_INTR_CYPIPE_PRIOR_EP2 (1UL) +#define CY_IPC_INTR_CYPIPE_MUX_EP2 (CY_IPC0_INTR_MUX(CY_IPC_INTR_CYPIPE_EP2)) +#define CM55_IPC_PIPE_EP_ADDR (2UL) +#define CM55_IPC_PIPE_CLIENT_ID (5UL) + +#define CY_IPC_CYPIPE_INTR_MASK (CY_IPC_CYPIPE_CHAN_MASK_EP1 | CY_IPC_CYPIPE_CHAN_MASK_EP2) +#define IPC_DEMO_SEMA_NUM (48UL) + +#define RC_CHANNEL_COUNT (8U) +#define RC_MAGIC_WORD (0x5243444DU) +#define RC_ROLE_M33 (0x33U) +#define RC_ROLE_M55_ECHO (0x55U) + +/* Stress-test tuning knobs */ +#define EDGE_IPC_FRAME_POOL_SIZE (64U) +#define EDGE_IPC_ECHO_QUEUE_SIZE (64U) +#define EDGE_IPC_STRESS_HZ (1000U) +#define EDGE_IPC_STRESS_BURST (4U) +#define EDGE_IPC_SEMA_RETRY_MAX (2U) +#define EDGE_IPC_PRINT_INTERVAL_MS (1000U) + +typedef struct +{ + uint8_t client_id; + uint16_t intr_mask; + uint8_t role; + uint32_t magic; + uint32_t seq; + uint16_t channel[RC_CHANNEL_COUNT]; + uint32_t checksum; +} edge_rc_frame_t; + +static inline uint32_t edge_rc_checksum(const edge_rc_frame_t* frame) +{ + uint32_t sum = frame->magic ^ frame->role ^ frame->seq; + uint32_t i; + + for (i = 0; i < RC_CHANNEL_COUNT; i++) { + sum ^= ((uint32_t)frame->channel[i] << (i & 0x7)); + sum = (sum << 3) | (sum >> 29); + } + + return sum; +} + +#endif diff --git a/libraries/M33_Config/Kconfig b/libraries/M33_Config/Kconfig index c1926fff..94bdbe9d 100644 --- a/libraries/M33_Config/Kconfig +++ b/libraries/M33_Config/Kconfig @@ -91,14 +91,17 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_SPI bool "Enable SPI" select RT_USING_PIN + select RT_USING_SPI default n if BSP_USING_SPI config BSP_USING_SPI1 - bool "Enable SPI1" - default n - config BSP_USING_SPI2 - bool "Enable SPI2" + bool "Enable SPI1 (SCB9)" default n + if BSP_USING_SPI1 + config BSP_SPI1_CS_PIN + int "SPI1 CS PIN number" + default 123 + endif endif menuconfig BSP_USING_ADC @@ -111,6 +114,23 @@ menu "On-chip Peripheral Drivers" default n endif + menuconfig BSP_USING_CANFD + bool "Enable CANFD" + select RT_USING_CAN + default n + if BSP_USING_CANFD + config BSP_USING_CANFD0 + bool "Enable CANFD0" + default n + config BSP_USING_CANFD1 + bool "Enable CANFD1" + default n + endif + + config BSP_USING_IPC + bool "Enable IPC" + default n + menuconfig BSP_USING_I2C bool "Enable I2C" default n diff --git a/libraries/M55_Config/Kconfig b/libraries/M55_Config/Kconfig index ecfb9660..e5204f4b 100644 --- a/libraries/M55_Config/Kconfig +++ b/libraries/M55_Config/Kconfig @@ -82,14 +82,17 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_SPI bool "Enable SPI" select RT_USING_PIN + select RT_USING_SPI default n if BSP_USING_SPI config BSP_USING_SPI1 - bool "Enable SPI1" - default n - config BSP_USING_SPI2 - bool "Enable SPI2" + bool "Enable SPI1 (SCB9)" default n + if BSP_USING_SPI1 + config BSP_SPI1_CS_PIN + int "SPI1 CS PIN number" + default 123 + endif endif menuconfig BSP_USING_ADC @@ -102,6 +105,23 @@ menu "On-chip Peripheral Drivers" default n endif + menuconfig BSP_USING_CANFD + bool "Enable CANFD" + select RT_USING_CAN + default n + if BSP_USING_CANFD + config BSP_USING_CANFD0 + bool "Enable CANFD0" + default n + config BSP_USING_CANFD1 + bool "Enable CANFD1" + default n + endif + + config BSP_USING_IPC + bool "Enable IPC" + default n + menuconfig BSP_USING_I2C bool "Enable I2C" default n diff --git a/libraries/components/mtb-device-support-pse8xxgp/pdl/SConscript b/libraries/components/mtb-device-support-pse8xxgp/pdl/SConscript index 65b7ccd3..2280d37c 100644 --- a/libraries/components/mtb-device-support-pse8xxgp/pdl/SConscript +++ b/libraries/components/mtb-device-support-pse8xxgp/pdl/SConscript @@ -65,6 +65,9 @@ if GetDepend(['RT_USING_PWM']): if GetDepend(['RT_USING_SPI']): src += ['drivers/source/cy_scb_spi.c'] +if GetDepend(['RT_USING_CAN']): + src += ['drivers/source/cy_canfd.c'] + if GetDepend('BSP_USING_LCD'): src += Split(''' drivers/source/cy_mipidsi.c diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.config b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.config new file mode 100644 index 00000000..dcc0de6f --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.config @@ -0,0 +1,1399 @@ +# Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib) + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=1024 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048 + +# +# kservice optimization +# +CONFIG_RT_KSERVICE_USING_STDLIB=y +# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +# end of kservice optimization + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_INIT is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +CONFIG_RT_USING_MEMHEAP=y +CONFIG_RT_MEMHEAP_FAST_MODE=y +# CONFIG_RT_MEMHEAP_BEST_MODE is not set +# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set +CONFIG_RT_USING_MEMHEAP_AS_HEAP=y +CONFIG_RT_USING_MEMHEAP_AUTO_BINDING=y +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=1024 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart5" +# end of Kernel Device Object + +CONFIG_RT_VER_NUM=0x50002 +# CONFIG_RT_USING_STDC_ATOMIC is not set +# end of RT-Thread Kernel + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_POSIX=y +CONFIG_DFS_USING_WORKDIR=y +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_DFS_FD_MAX=16 +CONFIG_RT_USING_DFS_V1=y +# CONFIG_RT_USING_DFS_V2 is not set +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set +CONFIG_RT_DFS_ELM_LFN_UNICODE=0 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 +# end of elm-chan's FatFs, Generic FAT Filesystem Module + +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_CROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_TMPFS is not set +# CONFIG_RT_USING_DFS_MQUEUE is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=128 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set +# CONFIG_RT_USING_KTIME is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# CONFIG_RT_USING_VBUS is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_NES_SIMULATOR is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_VECTOR is not set +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_MM32 is not set + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers + +# +# HC32 DDL Drivers +# +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set +# end of HC32 DDL Drivers + +# +# NXP HAL & SDK Drivers +# +# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set +# end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32VW55X_WIFI is not set +# end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK + +# +# FT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# end of FT32 HAL & SDK Drivers +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90384 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# CONFIG_PKG_USING_QMI8658 is not set +# CONFIG_PKG_USING_ICM20948 is not set +# CONFIG_PKG_USING_SCD4X is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_LCD_SPI_DRIVER is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SEAN_WS2812B is not set +# CONFIG_PKG_USING_IC74HC165 is not set +# CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_CAN_UDS is not set +# CONFIG_PKG_USING_ISOTP_C is not set +# CONFIG_PKG_USING_IKUNLED is not set +# CONFIG_PKG_USING_INS5T8025 is not set +# CONFIG_PKG_USING_IRUART is not set +# CONFIG_PKG_USING_ST7305 is not set +# CONFIG_PKG_USING_TM1668 is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +# CONFIG_RT_CHERRYUSB_DEVICE is not set +# CONFIG_RT_CHERRYUSB_HOST is not set + +# +# Hardware Drivers Config +# + +# +# Select SOC Multi Core Mode +# +CONFIG_SOC_Enable_CM55=y +# CONFIG_SOC_Enable_CM33_DeepSleep is not set +# end of Select SOC Multi Core Mode + +CONFIG_SOC_SERIES_IFX_PSOCE84=y +CONFIG_KIT_PROCE84_EVK_M33=y + +# +# Onboard Peripheral Drivers +# +CONFIG_BSP_USING_USB_TO_UART=y +# CONFIG_BSP_USING_AUDIO is not set +# CONFIG_BSP_USING_AHT20 is not set +# CONFIG_BSP_USING_USB is not set +# CONFIG_BSP_USING_FREERTOS is not set +# CONFIG_BSP_USING_LSM6DS3 is not set +# end of Onboard Peripheral Drivers + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_CANFD is not set +CONFIG_BSP_USING_IPC=y +# CONFIG_BSP_USING_I2C is not set +CONFIG_BSP_USING_UART=y +# CONFIG_BSP_USING_UART1 is not set +CONFIG_BSP_USING_UART2=y +CONFIG_BSP_USING_UART5=y +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_HYPERAM is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_TIM is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_SDIO is not set +# CONFIG_BSP_USING_LCD is not set +# CONFIG_BSP_USING_FILESYSTEM is not set +# CONFIG_USING_LVGL is not set +# end of On-chip Peripheral Drivers +# end of Hardware Drivers Config diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.cproject b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.cproject new file mode 100644 index 00000000..d0ad74f6 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.cproject @@ -0,0 +1,269 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.gitignore b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.gitignore new file mode 100644 index 00000000..3e1f4fd4 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h +/makefile.targets +!proj_cm33_s_signed.hex \ No newline at end of file diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.project b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.project new file mode 100644 index 00000000..6aa897cc --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.project @@ -0,0 +1,29 @@ + + + project + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + com.cypress.studio.app.cymodusnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + Edgi_Talk_M33_IPC + + diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.settings/.OpenOCD.Debug.rttlaunch b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.settings/.OpenOCD.Debug.rttlaunch new file mode 100644 index 00000000..5bb288b6 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.settings/.OpenOCD.Debug.rttlaunch @@ -0,0 +1,58 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.settings/.rtmenus b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.settings/.rtmenus new file mode 100644 index 00000000..648fcc38 Binary files /dev/null and b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.settings/.rtmenus differ diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.settings/Edgi_Talk_M33_IPC.DAPLink.Debug.rttlaunch b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.settings/Edgi_Talk_M33_IPC.DAPLink.Debug.rttlaunch new file mode 100644 index 00000000..ad8f3686 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.settings/Edgi_Talk_M33_IPC.DAPLink.Debug.rttlaunch @@ -0,0 +1,65 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.settings/Edgi_Talk_M33_IPC.OpenOCD.Debug.rttlaunch b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.settings/Edgi_Talk_M33_IPC.OpenOCD.Debug.rttlaunch new file mode 100644 index 00000000..84d42e9f --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.settings/Edgi_Talk_M33_IPC.OpenOCD.Debug.rttlaunch @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.settings/ilg.gnumcueclipse.managedbuild.cross.arm.prefs b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.settings/ilg.gnumcueclipse.managedbuild.cross.arm.prefs new file mode 100644 index 00000000..09800d8f --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.settings/ilg.gnumcueclipse.managedbuild.cross.arm.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +toolchain.path.1287942917=${toolchain_install_path}/ARM/GNU_Tools_for_ARM_Embedded_Processors/13.3/bin diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.settings/language.settings.xml b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.settings/language.settings.xml new file mode 100644 index 00000000..3f166b47 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.settings/language.settings.xml @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.settings/local_temp_storage.prefs b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.settings/local_temp_storage.prefs new file mode 100644 index 00000000..2be04c38 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.settings/local_temp_storage.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +temp.toolchain.exec.path=E\:\\SomeIDE\\RT-ThreadStudio\\repo\\Extract\\ToolChain_Support_Packages\\ARM\\GNU_Tools_for_ARM_Embedded_Processors\\13.3/bin diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.settings/org.eclipse.core.runtime.prefs b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.settings/org.eclipse.core.runtime.prefs new file mode 100644 index 00000000..9f1acfcf --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.settings/org.eclipse.core.runtime.prefs @@ -0,0 +1,3 @@ +content-types/enabled=true +content-types/org.eclipse.cdt.core.asmSource/file-extensions=s +eclipse.preferences.version=1 \ No newline at end of file diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.settings/projcfg.ini b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.settings/projcfg.ini new file mode 100644 index 00000000..dd44fc02 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/.settings/projcfg.ini @@ -0,0 +1,20 @@ +#RT-Thread Studio Project Configuration +#Thu Mar 26 17:40:16 CST 2026 +project_type=rt-thread +chip_name=CY8C624ALQI_S2D42 +os_branch=full +example_name= +os_version=latest +selected_rtt_version=latest +cfg_version=v3.0 +board_base_nano_proj=False +is_use_scons_build=True +output_project_path=D\:\\Desktop\\Talk\\sdk-bsp-psoc_e84-edgi-talk\\projects\\Edgi_Talk_IPC +project_base_bsp=true +hardware_adapter=KitProg3 +project_name=Edgi_Talk_M33_IPC +is_base_example_project=True +board_name=psoce84 +device_vendor=Infineon +bsp_version=1.0.0 +bsp_path=repo/Extract/Board_Support_Packages/Infineon/PSOC62-IFX-PROTO-KIT/1.0.0 diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/Kconfig b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/Kconfig new file mode 100644 index 00000000..4e0bfdd5 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/Kconfig @@ -0,0 +1,34 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "rt-thread" + +# you can change the RTT_ROOT default "rt-thread" +# example : default "F:/git_repositories/rt-thread" + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +config ENV_DIR + string + option env="ENV_ROOT" + default "/" + +config PLATFORM_DIR + string + option env="PLATFORM_DIR" + default "D:/Desktop/Talk/sdk-bsp-psoc_e84-edgi-talk/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/platform" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "$RTT_DIR/../libraries/components/CherryUSB-1.6.0/Kconfig.rtt" +source "$RTT_DIR/../libraries/M33_Config/Kconfig" diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/README.md b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/README.md new file mode 100644 index 00000000..4aa74e2e --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/README.md @@ -0,0 +1,204 @@ +# Edgi_Talk_M33_IPC Dual-Core Communication Example Project + +[**中文**](./README_zh.md) | **English** + +## Overview + +This project implements **IPC (Inter-Processor Communication)** dual-core communication on the **Edgi-Talk M33 core**, demonstrating message passing between **Cortex-M33** and **Cortex-M55**. + +M33 acts as the **sender**, periodically sending "Hello M33" messages to M55 and receiving "Hello M55" replies. + +## Default Configuration + +* Communication frequency: 1000ms +* Message format: ASCII encoded text messages +* Uses Infineon PSoC E84 on-chip IPC Pipe hardware + +## Build and Flash + +1. Build the project using RT-Thread Studio or SCons. +2. Flash firmware to M33 core via KitProg3 (DAP). +3. Both M33 and M55 projects must be built and flashed for dual-core communication. +4. Connect serial port to view communication logs as shown below: + +![alt text](figures/1.png) + +## Important Notes + +### Serial Connection + +This project uses **UART5** as the debug serial port. An external **CH340 USB-to-Serial module** is required: + +* **Serial Port**: UART5 +* **Baud Rate**: 115200 +* **Data Bits**: 8 +* **Stop Bits**: 1 +* **Parity**: None + +### CH340 Module Connection + +Connect the CH340 module to the development board as follows: + +**Connection Diagram**: + +![serial_connection](figures/2.png) + +> ⚠️ **Important Notes**: +> 1. TX and RX must be cross-connected (CH340 TX to board RX) +> 2. Ensure GND is common between both devices + +## Usage + +### 1. Configuration and Build + +Open in RT-Thread Studio: + +``` +RT-Thread Settings -> Hardware Drivers Config -> On-chip Peripheral Drivers +``` + +Check `Enable IPC` option. + +### 2. Run Example + +**Step 1: Start M55 Receiver** + +In M55 serial terminal, type: + +``` +msh> ipc_test_run +``` + +M55 will enter listening mode, waiting for messages from M33. + +**Step 2: Start M33 Sender** + +In M33 serial terminal, type: + +``` +msh> ipc_test_run +``` + +M33 will start sending "Hello M33" messages every second and receive "Hello M55" replies. + +### 3. Observe Output + +**M33 Output Example**: + +``` +======================================== +[M33] IPC Demo Started +---------------------------------------- +Mode: Sender +Target: Cortex-M55 +Message: Hello M33 +Interval: 1000 ms +======================================== + +[M33] TX -> [M55]: "Hello M33" | Seq: 1 | Time: 1234 ms +[M33] RX <- [M55]: "Hello M55" | Seq: 1 | Time: 1256 ms +[M33] TX -> [M55]: "Hello M33" | Seq: 2 | Time: 2234 ms +[M33] RX <- [M55]: "Hello M55" | Seq: 2 | Time: 2256 ms +---------------------------------------- +[M33] Statistics: TX=10, RX=10 +---------------------------------------- +``` + +**M55 Output Example**: + +``` +======================================== +[M55] IPC Listener Running +---------------------------------------- +Mode: Receiver & Responder +Peer: Cortex-M33 +Response: Hello M55 +======================================== + +[M55] RX <- [M33]: "Hello M33" | Seq: 1 | Time: 1250 ms +[M55] TX -> [M33]: "Hello M55" | Seq: 1 | Time: 1252 ms +[M55] RX <- [M33]: "Hello M33" | Seq: 2 | Time: 2250 ms +[M55] TX -> [M33]: "Hello M55" | Seq: 2 | Time: 2252 ms +---------------------------------------- +[M55] Statistics: RX=10, TX=10 +---------------------------------------- +``` + +## Data Protocol + +IPC communication uses the `edge_rc_frame_t` structure: + +```c +typedef struct { + uint8_t client_id; // Client ID + uint16_t intr_mask; // Interrupt mask + uint8_t role; // Role identifier (M33/M55_ECHO) + uint32_t magic; // Magic word (0x5243444DU) + uint32_t seq; // Sequence number + uint16_t channel[8]; // 8-channel data (stores ASCII messages) + uint32_t checksum; // Checksum +} edge_rc_frame_t; +``` + +Message "Hello M33" encoding: + +```c +channel[0] = 0x4865 /* 'He' */ +channel[1] = 0x6C6C /* 'll' */ +channel[2] = 0x6F20 /* 'o ' (space) */ +channel[3] = 0x4D33 /* 'M3' */ +channel[4] = 0x0033 /* '3' */ +``` + +## Startup Sequence + +M55 depends on M33 boot flow. Flash in this order: + +``` ++------------------+ +| Secure M33 | +| (Secure Core) | ++------------------+ + | + v ++------------------+ +| M33 | +| (IPC Sender) | ++------------------+ + | + v ++-------------------+ +| M55 | +| (IPC Receiver) | ++-------------------+ +``` + +## Hardware Connection + +This example uses Infineon PSoC E84 on-chip IPC hardware: + +* Uses IPC Pipe hardware in CM0P +* CM33 uses EP1 (Endpoint 1) +* CM55 uses EP2 (Endpoint 2) +* Uses semaphores for mutual exclusion +* No external wiring required + +## Configuration Parameters + +The following parameters can be modified in `libraries/HAL_Drivers/ipc_common.h`: + +* `EDGE_IPC_FRAME_POOL_SIZE`: Transmit buffer pool size (default 64) +* `EDGE_IPC_RX_QUEUE_SIZE`: Receive queue size (default 128) +* `EDGE_IPC_SEMA_RETRY_MAX`: Semaphore retry count (default 2) + +## Notes + +* This project targets M33 core as IPC sender. +* For M55 receiver, see [projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/README.md](../Edgi_Talk_M55_IPC/README.md). +* IPC driver is located at `libraries/HAL_Drivers/drv_ipc.c`. +* Ensure both cores are configured with `BSP_USING_IPC`. + +## References + +* IPC driver referenced from `D:\Desktop\Fmt\FMT-Firmware\target\infineon\edge-e83` +* Infineon PSoC E84 Technical Reference Manual diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/README_zh.md b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/README_zh.md new file mode 100644 index 00000000..041b5fea --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/README_zh.md @@ -0,0 +1,192 @@ +# Edgi_Talk_M33_IPC 双核通信示例工程 + +**中文** | [**English**](./README.md) + +## 简介 + +本工程在 **Edgi-Talk M33 核心**上实现 **IPC（Inter-Processor Communication）** 双核通信功能，演示了 **Cortex-M33** 与 **Cortex-M55** 之间的消息传递机制。 + +M33 作为**发送端**，定期向 M55 发送 "Hello M33" 消息，并接收 M55 的 "Hello M55" 回复。 + +## 默认配置 + +* 通信频率：1000ms +* 消息格式：ASCII 编码的文本消息 +* 使用 Infineon PSoC E84 片内 IPC Pipe 硬件 + +## 编译与下载 + +1. 使用 RT-Thread Studio 或 SCons 编译工程。 +2. 通过 KitProg3 (DAP) 下载固件到 M33 核心。 +3. 同时需要编译并下载 M55 工程才能完成双核通信。 +4. 连接串口查看通信日志，输出如下如图： + +![alt text](figures/1.png) + +## 注意事项 + +### 串口连接 + +本工程使用 **UART5** 作为调试串口，需要外接 **CH340 USB 转串��模块**： + +* **串口**: UART5 +* **波特率**: 115200 +* **数据位**: 8 +* **停止位**: 1 +* **校验位**: None + +### CH340 模块连接 + +请按以下方式连接 CH340 模块到开发板： + +**连接位置示意图**： + +![serial_connection](figures/2.png) + +> ⚠️ **重要提示**： +> 1. TX 和 RX 需要交叉连接（CH340 的 TX 接开发板的 RX） +> 2. 确保两个设备的 GND 共地 + +## 使用方法 + +### 1. 配置和编译 + +在 RT-Thread Studio 中打开： + +``` +RT-Thread Settings -> Hardware Drivers Config -> On-chip Peripheral Drivers +``` + +勾选 `Enable IPC` 选项。 + +### 2. 运行示例 + +**第一步：启动 M55 接收端** + +在 M55 的串口终端输入： + +``` +msh> ipc_test_run +``` + +M55 将进入监听模式，等待来自 M33 的消息。 + +**第二步：启动 M33 发送端** + +在 M33 的串口终端输入： + +``` +msh> ipc_test_run +``` + +M33 将开始每秒发送 "Hello M33" 消息，并接收 M55 的 "Hello M55" 回复。 + +### 3. 观察输出 + +**M33 输出示例：** + +``` +======================================== +[M33] IPC Demo Started +---------------------------------------- +Mode: Sender +Target: Cortex-M55 +Message: Hello M33 +Interval: 1000 ms +======================================== + +[M33] TX -> [M55]: "Hello M33" | Seq: 1 | Time: 1234 ms +[M33] RX <- [M55]: "Hello M55" | Seq: 1 | Time: 1256 ms +[M33] TX -> [M55]: "Hello M33" | Seq: 2 | Time: 2234 ms +[M33] RX <- [M55]: "Hello M55" | Seq: 2 | Time: 2256 ms +---------------------------------------- +[M33] Statistics: TX=10, RX=10 +---------------------------------------- +``` + +**M55 输出示例：** + +``` +======================================== +[M55] IPC Listener Running +---------------------------------------- +Mode: Receiver & Responder +Peer: Cortex-M33 +Response: Hello M55 +======================================== + +[M55] RX <- [M33]: "Hello M33" | Seq: 1 | Time: 1250 ms +[M55] TX -> [M33]: "Hello M55" | Seq: 1 | Time: 1252 ms +[M55] RX <- [M33]: "Hello M33" | Seq: 2 | Time: 2250 ms +[M55] TX -> [M33]: "Hello M55" | Seq: 2 | Time: 2252 ms +---------------------------------------- +[M55] Statistics: RX=10, TX=10 +---------------------------------------- +``` + +## 数据协议 + +IPC 通信使用 `edge_rc_frame_t` 结构体： + +```c +typedef struct { + uint8_t client_id; // 客户端 ID + uint16_t intr_mask; // 中断掩码 + uint8_t role; // 角色标识 (M33/M55_ECHO) + uint32_t magic; // 魔术字 (0x5243444DU) + uint32_t seq; // 序列号 + uint16_t channel[8]; // 8通道数据（存储 ASCII 消息） + uint32_t checksum; // 校验和 +} edge_rc_frame_t; +``` + +消息 "Hello M33" 编码方式： + +```c +channel[0] = 0x4865 /* 'He' */ +channel[1] = 0x6C6C /* 'll' */ +channel[2] = 0x6F20 /* 'o ' (space) */ +channel[3] = 0x4D33 /* 'M3' */ +channel[4] = 0x0033 /* '3' */ +``` + +## 启动流程 + +M55 依赖 M33 启动流程，烧录顺序如下： + +``` ++------------------+ +| Secure M33 | +| (安全内核启动) | ++------------------+ + | + v ++------------------+ +| M33 | +| (IPC 发送端) | ++------------------+ + | + v ++-------------------+ +| M55 | +| (IPC 接收端) | ++-------------------+ +``` + +## 硬件连接 + +本示例使用 Infineon PSoC E84 的片内 IPC 硬件： + +* 使用 CM0P 中的 IPC Pipe 硬件 +* CM33 使用 EP1 (Endpoint 1) +* CM55 使用 EP2 (Endpoint 2) +* 使用信号量进行互斥访问 +* 不需要外部连线 + +## 配置参数 + +在 `libraries/HAL_Drivers/ipc_common.h` 中可修改以下参数： + +* `EDGE_IPC_FRAME_POOL_SIZE`: 发送缓冲池大小（默认 64） +* `EDGE_IPC_RX_QUEUE_SIZE`: 接收队列大小（默认 128） +* `EDGE_IPC_SEMA_RETRY_MAX`: 信号量重试次数（默认 2） diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/SConscript b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/SConscript new file mode 100644 index 00000000..20f7689c --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/SConstruct b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/SConstruct new file mode 100644 index 00000000..2dd5ea16 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/SConstruct @@ -0,0 +1,166 @@ +import os +import sys +import rtconfig +import platform +import subprocess +import uuid + +if os.path.exists('rt-thread'): + RTT_ROOT = os.path.normpath(os.getcwd() + '/rt-thread') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../rt-thread') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except Exception as e: + print("Error message:", e) + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + sys.exit(-1) + +TARGET = 'rt-thread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], ENV=os.environ, + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env.AppendUnique(CPPPATH=[os.getcwd()]) + +OBJCOPY = os.path.join(rtconfig.EXEC_PATH, 'arm-none-eabi-objcopy') + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') +if os.path.exists(SDK_ROOT + '/libraries/components'): + libraries_path_prefix = SDK_ROOT + '/libraries/components' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/../../libraries/components' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +IFX_library = 'Packages' +rtconfig.BSP_LIBRARY_TYPE = IFX_library + +# set spawn +def ourspawn(sh, escape, cmd, args, e): + filename = str(uuid.uuid4()) + newargs = ' '.join(args[1:]) + cmdline = cmd + " " + newargs + if (len(cmdline) > 16 * 1024): + f = open(filename, 'w') + f.write(' '.join(args[1:]).replace('\\', '/')) + f.close() + # exec + cmdline = cmd + " @" + filename + proc = subprocess.Popen(cmdline, stdin=subprocess.PIPE, stdout=subprocess.PIPE, + stderr=subprocess.PIPE, shell = False, env = e) + data, err = proc.communicate() + rv = proc.wait() + def res_output(_output, _s): + if len(_s): + if isinstance(_s, str): + _output(_s) + elif isinstance(_s, bytes): + _output(str(_s, 'UTF-8')) + else: + _output(str(_s)) + res_output(sys.stderr.write, err) + res_output(sys.stdout.write, data) + if os.path.isfile(filename): + os.remove(filename) + return rv + +if platform.system() == 'Windows': + env['SPAWN'] = ourspawn + +# Add project libs with VariantDir +if os.path.exists(os.path.join(os.getcwd(), "libs", "SConscript")): + env.VariantDir('build/libs', 'libs', duplicate=0) +else: + env.VariantDir('build/libs', '../../libs', duplicate=0) + objs.extend(SConscript('../../libs/SConscript', variant_dir='build/libs', duplicate=0)) + +if os.path.exists(os.path.join(os.getcwd(), "libraries")): + # Set VariantDir for libraries + env.VariantDir('build/libraries/HAL_Drivers', 'libraries/HAL_Drivers', duplicate=0) + env.VariantDir('build/libraries/components', 'libraries/components', duplicate=0) + env.VariantDir('build/libraries/Common/board', 'libraries/Common/board', duplicate=0) + + objs.extend(SConscript('libraries/HAL_Drivers/SConscript', variant_dir='build/libraries/HAL_Drivers', duplicate=0)) + objs.extend(SConscript('libraries/components/Infineon_cmsis-latest/SConscript', variant_dir='build/libraries/components/Infineon_cmsis-latest', duplicate=0)) + objs.extend(SConscript('libraries/components/Infineon_core-lib-latest/SConscript', variant_dir='build/libraries/components/Infineon_core-lib-latest', duplicate=0)) + objs.extend(SConscript('libraries/components/mtb-device-support-pse8xxgp/hal/SConscript', variant_dir='build/libraries/components/mtb-device-support-pse8xxgp/hal', duplicate=0)) + objs.extend(SConscript('libraries/components/mtb-device-support-pse8xxgp/pdl/SConscript', variant_dir='build/libraries/components/mtb-device-support-pse8xxgp/pdl', duplicate=0)) + objs.extend(SConscript('libraries/components/async-transfer/SConscript', variant_dir='build/libraries/components/async-transfer', duplicate=0)) + objs.extend(SConscript('libraries/components/mtb-device-support-pse8xxgp/device-utils/syspm/SConscript', variant_dir='build/libraries/components/mtb-device-support-pse8xxgp/device-utils/syspm', duplicate=0)) + objs.extend(SConscript('libraries/components/serial-memory/SConscript', variant_dir='build/libraries/components/serial-memory', duplicate=0)) + objs.extend(SConscript('libraries/components/Infineon_retarget-io-latest/SConscript', variant_dir='build/libraries/components/Infineon_retarget-io-latest', duplicate=0)) + objs.extend(SConscript('libraries/components/ASRC/SConscript', variant_dir='build/libraries/components/ASRC', duplicate=0)) + objs.extend(SConscript('libraries/components/SConscript', variant_dir='build/libraries/components', duplicate=0)) + objs.extend(SConscript('libraries/components/mtb-srf/SConscript', variant_dir='build/libraries/components/mtb-srf', duplicate=0)) + objs.extend(SConscript('libraries/components/mtb-ipc/SConscript', variant_dir='build/libraries/components/mtb-ipc', duplicate=0)) + objs.extend(SConscript('libraries/components/littlefs/SConscript', variant_dir='build/libraries/components/littlefs', duplicate=0)) + objs.extend(SConscript('libraries/Common/board/SConscript', variant_dir='build/libraries/Common/board', duplicate=0)) +else: + # Set VariantDir for external libraries + env.VariantDir('build/libraries/HAL_Drivers', '../../../libraries/HAL_Drivers', duplicate=0) + env.VariantDir('build/libraries/components', '../../../libraries/components', duplicate=0) + env.VariantDir('build/libraries/Common/board', '../../../libraries/Common/board', duplicate=0) + + objs.extend(SConscript('../../../libraries/HAL_Drivers/SConscript', variant_dir='build/libraries/HAL_Drivers', duplicate=0)) + objs.extend(SConscript('../../../libraries/components/Infineon_cmsis-latest/SConscript', variant_dir='build/libraries/components/Infineon_cmsis-latest', duplicate=0)) + objs.extend(SConscript('../../../libraries/components/Infineon_core-lib-latest/SConscript', variant_dir='build/libraries/components/Infineon_core-lib-latest', duplicate=0)) + objs.extend(SConscript('../../../libraries/components/mtb-device-support-pse8xxgp/hal/SConscript', variant_dir='build/libraries/components/mtb-device-support-pse8xxgp/hal', duplicate=0)) + objs.extend(SConscript('../../../libraries/components/mtb-device-support-pse8xxgp/pdl/SConscript', variant_dir='build/libraries/components/mtb-device-support-pse8xxgp/pdl', duplicate=0)) + objs.extend(SConscript('../../../libraries/components/async-transfer/SConscript', variant_dir='build/libraries/components/async-transfer', duplicate=0)) + objs.extend(SConscript('../../../libraries/components/mtb-device-support-pse8xxgp/device-utils/syspm/SConscript', variant_dir='build/libraries/components/mtb-device-support-pse8xxgp/device-utils/syspm', duplicate=0)) + objs.extend(SConscript('../../../libraries/components/serial-memory/SConscript', variant_dir='build/libraries/components/serial-memory', duplicate=0)) + objs.extend(SConscript('../../../libraries/components/Infineon_retarget-io-latest/SConscript', variant_dir='build/libraries/components/Infineon_retarget-io-latest', duplicate=0)) + objs.extend(SConscript('../../../libraries/components/ASRC/SConscript', variant_dir='build/libraries/components/ASRC', duplicate=0)) + objs.extend(SConscript('../../../libraries/components/SConscript', variant_dir='build/libraries/components', duplicate=0)) + objs.extend(SConscript('../../../libraries/components/mtb-srf/SConscript', variant_dir='build/libraries/components/mtb-srf', duplicate=0)) + objs.extend(SConscript('../../../libraries/components/mtb-ipc/SConscript', variant_dir='build/libraries/components/mtb-ipc', duplicate=0)) + objs.extend(SConscript('../../../libraries/components/littlefs/SConscript', variant_dir='build/libraries/components/littlefs', duplicate=0)) + objs.extend(SConscript('../../../libraries/Common/board/SConscript', variant_dir='build/libraries/Common/board', duplicate=0)) + +# make a building +DoBuilding(TARGET, objs) + +# Generate HEX file +DEBUG_DIR = 'build' +if not os.path.exists(DEBUG_DIR): + os.makedirs(DEBUG_DIR) +hex_file = env.Command(DEBUG_DIR + '/rtthread.hex', TARGET, OBJCOPY + ' -O ihex $SOURCE $TARGET') + +# Secure image packaging using edgeprotecttools (Windows only) +if platform.system() == 'Windows': + # SDK_ROOT is the project directory, go up 3 levels to reach sdk-bsp root + SDK_BSP_ROOT = os.path.dirname(os.path.dirname(os.path.dirname(SDK_ROOT))) + EDGEPROTECTTOOLS = os.path.join(SDK_BSP_ROOT, 'tools', 'edgeprotecttools', 'bin', 'edgeprotecttools.exe') + BOOT_CONFIG = os.path.join(SDK_ROOT, 'config', 'boot_with_extended_boot_scons.json') + + if os.path.exists(EDGEPROTECTTOOLS) and os.path.exists(BOOT_CONFIG): + secure_image = env.Command( + 'secure_image', # Pseudo target + hex_file, + '"' + EDGEPROTECTTOOLS + '" run-config -i "' + BOOT_CONFIG + '"' + ) + else: + print("edgeprotecttools or boot config not found, skipping secure image packaging") + print("EDGEPROTECTTOOLS:", EDGEPROTECTTOOLS) + print("BOOT_CONFIG:", BOOT_CONFIG) diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/applications/SConscript b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/applications/SConscript new file mode 100644 index 00000000..034056ec --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/applications/SConscript @@ -0,0 +1,16 @@ +import rtconfig +from building import * +import os + +cwd = GetCurrentDir() +path = [cwd] +src = Glob('*.c') + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = path) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/applications/main.c b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/applications/main.c new file mode 100644 index 00000000..9fba07b5 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/applications/main.c @@ -0,0 +1,139 @@ +#include +#include +#include +#include + +#include "drv_ipc.h" + +#define LED_PIN_B GET_PIN(16, 5) +#define MSG_INTERVAL_MS (1000U) + +static void ipc_test_run(void) +{ + rt_device_t ipc_dev; + edge_rc_frame_t tx_frame; + edge_rc_frame_t rx_frame; + rt_uint32_t seq = 0; + rt_tick_t last_send_tick = 0; + rt_uint32_t tx_count = 0; + rt_uint32_t rx_count = 0; + + /* 查找 IPC 设备 */ + ipc_dev = edge_ipc_device_find(); + if (ipc_dev == RT_NULL) { + if (edge_ipc_device_register() != RT_EOK) { + rt_kprintf("[M33] IPC: Device register failed\r\n"); + return; + } + ipc_dev = edge_ipc_device_find(); + if (ipc_dev == RT_NULL) { + rt_kprintf("[M33] IPC: Device not found\r\n"); + return; + } + } + + /* 打开 IPC 设备 */ + if (rt_device_open(ipc_dev, RT_DEVICE_OFLAG_RDWR) != RT_EOK) { + rt_kprintf("[M33] IPC: Open device failed\r\n"); + return; + } + + rt_kprintf("\r\n"); + rt_kprintf("========================================\r\n"); + rt_kprintf("[M33] IPC Demo Started\r\n"); + rt_kprintf("----------------------------------------\r\n"); + rt_kprintf("Mode: Sender\r\n"); + rt_kprintf("Target: Cortex-M55\r\n"); + rt_kprintf("Message: Hello M33\r\n"); + rt_kprintf("Interval: %d ms\r\n", MSG_INTERVAL_MS); + rt_kprintf("========================================\r\n"); + rt_kprintf("\r\n"); + + last_send_tick = rt_tick_get(); + + while (1) { + /* 定时发送消息 */ + if ((rt_tick_get() - last_send_tick) >= rt_tick_from_millisecond(MSG_INTERVAL_MS)) { + /* 准备发送消息 - "Hello M33" */ + memset(&tx_frame, 0, sizeof(tx_frame)); + tx_frame.client_id = CM55_IPC_PIPE_CLIENT_ID; + tx_frame.role = RC_ROLE_M33; + tx_frame.magic = RC_MAGIC_WORD; + tx_frame.seq = ++seq; + /* Encode "Hello M33" into channels (2 chars per channel) */ + tx_frame.channel[0] = 0x4865UL; /* 'He' in ASCII */ + tx_frame.channel[1] = 0x6C6CUL; /* 'll' in ASCII */ + tx_frame.channel[2] = 0x6F20UL; /* 'o ' in ASCII */ + tx_frame.channel[3] = 0x4D33UL; /* 'M3' in ASCII */ + tx_frame.channel[4] = 0x0033UL; /* '3' in ASCII */ + tx_frame.checksum = edge_rc_checksum(&tx_frame); + + /* 发送消息 */ + if (rt_device_write(ipc_dev, 0, &tx_frame, 1) == 1) { + rt_kprintf("[M33] TX -> [M55]: \"Hello M33\" | Seq: %5lu | Time: %8lu ms\r\n", + seq, rt_tick_get() * 1000 / RT_TICK_PER_SECOND); + tx_count++; + } else { + rt_kprintf("[M33] TX Failed\r\n"); + } + + last_send_tick = rt_tick_get(); + } + + /* 接收 M55 的回复 */ + if (rt_device_read(ipc_dev, 0, &rx_frame, 1) == 1) { + if (rx_frame.magic == RC_MAGIC_WORD && + rx_frame.role == RC_ROLE_M55_ECHO && + edge_rc_checksum(&rx_frame) == rx_frame.checksum) { + + /* 解析消息 - Check for "Hello M55" */ + if (rx_frame.channel[0] == 0x4865UL && /* 'He' */ + rx_frame.channel[1] == 0x6C6CUL && /* 'll' */ + rx_frame.channel[2] == 0x6F20UL && /* 'o ' */ + rx_frame.channel[3] == 0x4D35UL && /* 'M5' */ + rx_frame.channel[4] == 0x0035UL) { /* '5' */ + + rt_kprintf("[M33] RX <- [M55]: \"Hello M55\" | Seq: %5lu | Time: %8lu ms\r\n", + rx_frame.seq, rt_tick_get() * 1000 / RT_TICK_PER_SECOND); + rx_count++; + + /* 每 10 次交互打印统计信息 */ + if (rx_count % 10 == 0) { + rt_kprintf("----------------------------------------\r\n"); + rt_kprintf("[M33] Statistics: TX=%lu, RX=%lu\r\n", tx_count, rx_count); + rt_kprintf("----------------------------------------\r\n"); + } + } + } else { + rt_kprintf("[M33] Invalid message received\r\n"); + } + } + + rt_thread_mdelay(10); + } +} +MSH_CMD_EXPORT(ipc_test_run, Start M33 IPC test); + +int main(void) +{ + rt_kprintf("\r\n"); + rt_kprintf("========================================\r\n"); + rt_kprintf(" RT-Thread on Cortex-M33 Core \r\n"); + rt_kprintf("========================================\r\n"); + rt_kprintf("Command: ipc_test_run\r\n"); + rt_kprintf("Status: Running\r\n"); + rt_kprintf("========================================\r\n"); + rt_kprintf("\r\n"); + + rt_pin_mode(LED_PIN_B, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED_PIN_B, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED_PIN_B, PIN_LOW); + rt_thread_mdelay(500); + } + + return 0; +} diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/board/SConscript b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/board/SConscript new file mode 100644 index 00000000..86b45468 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/board/SConscript @@ -0,0 +1,79 @@ +import os +import rtconfig +from building import * + +Import("SDK_LIB") + +objs = [] +cwd = GetCurrentDir() +list = os.listdir(cwd) + +# add general drivers +src = Glob('*.c') + +path = [cwd] + +startup_path_prefix = SDK_LIB +Tool_path = None +index = "mtb-device-support-pse8xxgp" + +for filename in os.listdir(startup_path_prefix): + if index in filename: + Tool_path = os.path.join(startup_path_prefix, filename) + + + +CPPDEFINES = [ + "BLHS_SUPPORT", + "COMPONENT_55500", + "COMPONENT_55500A1", + "COMPONENT_APP_KIT_PSE84_EVAL_EPC2", + "COMPONENT_CM33", + "COMPONENT_CM33_0", + "COMPONENT_CYW55513_MOD_PSE84_SOM", + "COMPONENT_Debug", + "COMPONENT_GCC_ARM", + "COMPONENT_GFXSS", + "COMPONENT_HCI_UART", + "COMPONENT_MTB_DEVICE_SUPPORT", + "COMPONENT_MTB_HAL", + "COMPONENT_MW_ASYNC_TRANSFER", + "COMPONENT_MW_BT_FW_IFX_CYW55500A1", + "COMPONENT_MW_CMSIS", + "COMPONENT_MW_CORE_LIB", + "COMPONENT_MW_CORE_MAKE", + "COMPONENT_MW_MTB_DSL_PSE8XXGP", + "COMPONENT_MW_MTB_IPC", + "COMPONENT_MW_MTB_SRF", + "COMPONENT_MW_SE_RT_SERVICES_UTILS", + "COMPONENT_NON_SECURE_DEVICE", + "COMPONENT_PSE84", + "COMPONENT_SM", + "COMPONENT_SOFTFP", + "COMPONENT_WIFI_INTERFACE_SDIO", + "COMPONENT_wlbga_iPA_sLNA_ANT0_LHL_XTAL_IN", + "CORE_NAME_CM33_0=1", + "CY_APPNAME_proj_cm33_ns", + "CYBSP_MCUBOOT_HEADER_SIZE=0x400", + "CYBSP_WIFI_WL_HOSTWAKE_DRIVE_MODE=MTB_HAL_GPIO_DRIVE_OPENDRAINDRIVESLOW", + "CYBSP_WIFI_WL_HOSTWAKE_INIT_STATE=WHD_TRUE", + "CY_PDL_FLASH_BOOT", + "CY_RETARGET_IO_CONVERT_LF_TO_CRLF", + "CY_SUPPORTS_DEVICE_VALIDATION", + "CY_TARGET_BOARD=APP_KIT_PSE84_EVAL_EPC2", + "CY_WIFI_COUNTRY=WHD_COUNTRY_UNITED_STATES", + "DEBUG", + "FLASH_BOOT", + "PSE846GPS2DBZC4A", + "TARGET_APP_KIT_PSE84_EVAL_EPC2", + "TRXV5", +] + + +group = DefineGroup("Drivers", src, depend=[""], CPPPATH=path, CPPDEFINES=CPPDEFINES) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) +Return("group") diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/board/board.c b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/board/board.c new file mode 100644 index 00000000..ac903b98 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/board/board.c @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-06-29 Rbb666 first version + * 2025-08-20 Hydevcode + */ + +#include "board.h" +#define ES8388_CTRL GET_PIN(16, 2) +#define SPEAKER_OE_CTRL GET_PIN(21, 6) +#define WIFI_OE_CTRL GET_PIN(16, 3) +#define WIFI_WL_REG_OE_CTRL GET_PIN(11, 6) +#define CTRL GET_PIN(7, 2) + +void cy_bsp_all_init(void) +{ + cy_rslt_t result; + + /* Initialize the device and board peripherals */ + result = cybsp_init(); + + /* Board init failed. Stop program execution */ + if (result != CY_RSLT_SUCCESS) + { + CY_ASSERT(0); + } + + if (CY_SYSLIB_RESET_HIB_WAKEUP == (Cy_SysLib_GetResetReason() & + CY_SYSLIB_RESET_HIB_WAKEUP)) + { + Cy_SysLib_ClearResetReason(); + Cy_SysPm_IoUnfreeze(); + Cy_SysPm_TriggerXRes(); + + } +#ifdef SOC_Enable_CM55 + Cy_SysEnableCM55(MXCM55, CY_CM55_APP_BOOT_ADDR, 10); +#ifdef SOC_Enable_CM33_DeepSleep + while (1) + { + Cy_SysPm_CpuEnterDeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT); + } +#endif +#endif + +} + +void _start(void) +{ + extern int entry(void); + entry(); + while (1); + __builtin_unreachable(); +} + +void poweroff(void) +{ + rt_pin_mode(WIFI_OE_CTRL, PIN_MODE_OUTPUT); + rt_pin_write(WIFI_OE_CTRL, PIN_LOW); + + rt_pin_mode(WIFI_WL_REG_OE_CTRL, PIN_MODE_OUTPUT); + rt_pin_write(WIFI_WL_REG_OE_CTRL, PIN_LOW); + + rt_pin_mode(ES8388_CTRL, PIN_MODE_OUTPUT); + rt_pin_write(ES8388_CTRL, PIN_LOW); + + rt_pin_mode(SPEAKER_OE_CTRL, PIN_MODE_OUTPUT); + rt_pin_write(SPEAKER_OE_CTRL, PIN_LOW); + + rt_pin_mode(CTRL, PIN_MODE_OUTPUT); + rt_pin_write(CTRL, PIN_LOW); + + Cy_SysClk_PllDisable(SRSS_DPLL_LP_0_PATH_NUM); + Cy_SysPm_SystemEnterHibernate(); +} + +#ifdef RT_USING_MSH + MSH_CMD_EXPORT(poweroff, The software enables the system to shut down. Simply press the button to restart it.); +#endif + +//Mos管控制 +#define ES8388_CTRL GET_PIN(16, 2) //ES8388 电源 Enable引脚 +#define SPEAKER_OE_CTRL GET_PIN(21, 6) //功放 Enable引脚 +#define WIFI_OE_CTRL GET_PIN(16, 3) //WIFI Enable引脚 +#define WIFI_WL_REG_OE_CTRL GET_PIN(11, 6) //WiFi寄存器开关 +#define CTRL GET_PIN(7, 2) //底板 3V3 DCDC电源控制 +int en_gpio(void) +{ + rt_pin_mode(WIFI_OE_CTRL, PIN_MODE_OUTPUT); + rt_pin_write(WIFI_OE_CTRL, PIN_HIGH); + + rt_pin_mode(WIFI_WL_REG_OE_CTRL, PIN_MODE_OUTPUT); + rt_pin_write(WIFI_WL_REG_OE_CTRL, PIN_HIGH); + + rt_pin_mode(ES8388_CTRL, PIN_MODE_OUTPUT); + rt_pin_write(ES8388_CTRL, PIN_HIGH); + + rt_pin_mode(SPEAKER_OE_CTRL, PIN_MODE_OUTPUT); + rt_pin_write(SPEAKER_OE_CTRL, PIN_HIGH); + + return 0; +} +INIT_BOARD_EXPORT(en_gpio); \ No newline at end of file diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/board/board.h b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/board/board.h new file mode 100644 index 00000000..a42c6841 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/board/board.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-06-29 Rbb666 first version + * 2022-07-26 Rbb666 Add Flash Config + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "drv_common.h" +#include "drv_gpio.h" + +#include "cy_result.h" +#include "cybsp_types.h" +#include "mtb_hal.h" +#include "cybsp.h" + +#ifdef BSP_USING_USBD + #include "cy_usb_dev.h" + #include "cy_usb_dev_hid.h" +#endif + +/*SRAM CONFIG*/ +#define IFX_SRAM_SIZE (256) +#define IFX_SRAM_END (0x240BD000 + IFX_SRAM_SIZE * 1024) + +#ifdef __ARMCC_VERSION + extern int Image$$RW_IRAM1$$ZI$$Limit; + #define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) + #define HEAP_END IFX_SRAM_END +#elif __ICCARM__ + #pragma section="HEAP" + #define HEAP_BEGIN (__segment_end("HEAP")) +#else + extern unsigned int __end__; + extern unsigned int __HeapLimit; + #define HEAP_BEGIN (void*)&__end__ + #define HEAP_END (void*)&__HeapLimit +#endif + +void cy_bsp_all_init(void); + +#endif + diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/board/linker_scripts/link.ld b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/board/linker_scripts/link.ld new file mode 100644 index 00000000..18112819 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/board/linker_scripts/link.ld @@ -0,0 +1,384 @@ +/***************************************************************************//** +* \file pse84_ns_cm33.ld +* \version 1.0.0 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright (c) (2020-2025), Cypress Semiconductor Corporation (an Infineon company) or +* an affiliate of Cypress Semiconductor Corporation. +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ +/* Specify the output format for the linker script */ +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +/* Search for libraries in the current directory */ +SEARCH_DIR(.) +/* Specify the group of libraries to link against */ +GROUP(-lgcc -lc -lnosys) +/* Define the entry point of the program, which is the reset handler */ +ENTRY(Reset_Handler) + +/* Define the stack size for the application */ +/* To set stack size in application add makefile ldflags: -Wl,--defsym=APP_MSP_STACK_SIZE= */ +PROVIDE(__StackSize = DEFINED(APP_MSP_STACK_SIZE) ? APP_MSP_STACK_SIZE : 0x1000); + +/* Include the device memory definitions generated by the Device Configurator */ +/* This file is automatically generated. */ + +MEMORY +{ + m33_nvm : ORIGIN = 0x60340000, LENGTH = 0x00200000 + m33_nvm_C : ORIGIN = 0x08340000, LENGTH = 0x00200000 + m33_trailer : ORIGIN = 0x60540000, LENGTH = 0x00040000 + m33_trailer_C : ORIGIN = 0x08540000, LENGTH = 0x00040000 + m33_m55_shared : ORIGIN = 0x261C0000, LENGTH = 0x00040000 + m33_m55_shared_C : ORIGIN = 0x061C0000, LENGTH = 0x00040000 + m33_code : ORIGIN = 0x24058000, LENGTH = 0x00065000 + m33_code_C : ORIGIN = 0x04058000, LENGTH = 0x00065000 + m33_data : ORIGIN = 0x240BD000, LENGTH = 0x00040000 + m33_data_C : ORIGIN = 0x040BD000, LENGTH = 0x00040000 + m33_allocatable_shared : ORIGIN = 0x240FE000, LENGTH = 0x00001000 + m33_allocatable_shared_C : ORIGIN = 0x040FE000, LENGTH = 0x00001000 +} + +REGION_ALIAS("m33_nvm_sel", m33_nvm_C) +REGION_ALIAS("m33_trailer_sel", m33_trailer_C) +REGION_ALIAS("m33_m55_shared_sel", m33_m55_shared_C) +REGION_ALIAS("m33_code_sel", m33_code_C) +REGION_ALIAS("m33_data_sel", m33_data_C) +REGION_ALIAS("m33_allocatable_shared_sel", m33_allocatable_shared_C) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ + +/* Device definitions */ +VECTORS_ALIGNMENT = 0x400; + +/* Compute the difference between C-AHB address and S-AHB address for +* section m33_code. This value is used to correctly copy code in the +* copy table. This is needed because the code needs to be accessed from +* the C-AHB address (faster, better performance) but since this is a read-only +* address to perform the copy we need to specify the S-AHB address which +* allows for writes as well. +*/ +m33_code_sel_Offset = ORIGIN(m33_code) - ORIGIN(m33_code_sel); + +/* The size of the MCU boot header area at the start of main code region */ +MCUBOOT_HEADER_SIZE = 0x400; + +/* Define the sections */ +SECTIONS +{ + /* This section reserves a space for MCUBoot header */ + .mcu_boot_header(READONLY) : ALIGN(MCUBOOT_HEADER_SIZE) + { + . += MCUBOOT_HEADER_SIZE; + } > m33_nvm_sel + + /* This section is intended to hold the main non-secure (NS) application code for the Cortex-M33 */ + /* Performance-sensitive or critical functions that need to be executed in sram are manually excluded */ + .app_code_main : ALIGN(VECTORS_ALIGNMENT) + { + /* Keep the vector table */ + KEEP(*(.vectors)) + /* Keep initializers */ + KEEP(*(.init)) + /* Keep finalizers */ + KEEP(*(.fini)) + /* Static constructors */ + *crtbegin.*(.ctors) + *crtbegin?.*(.ctors) + *(EXCLUDE_FILE(*crtend?.* *crtend.*) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + /* Static destructors and atexit() */ + *crtbegin.*(.dtors) + *crtbegin?.*(.dtors) + *(EXCLUDE_FILE(*crtend?.* *crtend.*) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + . = ALIGN(4); + + /* Array of pointers to preinint functions */ + PROVIDE_HIDDEN(__preinit_array_start = .); + + KEEP(*(.preinit_array)) + + PROVIDE_HIDDEN(__preinit_array_end = .); + + . = ALIGN(4); + + /* Array of pointers to init functions */ + PROVIDE_HIDDEN(__init_array_start = .); + + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + + PROVIDE_HIDDEN(__init_array_end = .); + + . = ALIGN(4); + + /* Array of pointers to finalizer functions */ + + PROVIDE_HIDDEN(__fini_array_start = .); + + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + + PROVIDE_HIDDEN(__fini_array_end = .); + + /* Read only code (constants) */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + /* Exclude certain files from this section as they will be placed in RAM */ + *(EXCLUDE_FILE(*cy_syslib.* *cy_syslib_ext.* *cy_smif.* *cy_smif_memnum.* *cy_smif_memslot.* *cy_smif_sfdp.* *cy_smif_hb_flash.* *mtb_hal_memoryspi.* *mtb_serial_memory.* *freertos/Source*.* *cy_clib_support*.* *cy_mutex_pool*.* *cy_time.* *cyabs_*.* *cy_worker_thread.* *cmsis*.*) .text*) + + + } > m33_nvm_sel + + /* Exception tables for ARM architecture */ + .ARM.extab (READONLY): ALIGN(4) + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + + } > m33_nvm_sel + + /* Exception index tables for ARM architecture */ + .ARM.exidx (READONLY): ALIGN(4) + { + __exidx_start = .; + + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + __exidx_end = .; + + } > m33_nvm_sel + + /* Define copying of data from flash memory to RAM during the startup */ + .copy.table (READONLY): ALIGN(4) + { + __copy_table_start__ = .; + + /* Initialized data in SRAM */ + LONG (LOADADDR(.data)) /* From load address in ext flash */ + LONG (ADDR(.data)) /* To run address in RAM */ + LONG (SIZEOF(.data)/4) /* Size in words */ + + /* Performance-sensitive or critical functions that need to be executed in SRAM */ + LONG(LOADADDR(.app_code_ram)) /* From load address in ext flash */ + LONG(ADDR(.app_code_ram) + m33_code_sel_Offset) /* To run address in RAM - using S-AHB for copying */ + LONG(SIZEOF(.app_code_ram)/4) /* Size in words */ + + __copy_table_end__ = .; + + } > m33_nvm_sel + + /* Define zeroing of the uninitialized data section */ + .zero.table (READONLY): ALIGN(4) + { + __zero_table_start__ = .; + + LONG(__bss_start__) /* Start of the zero-initialized data section */ + LONG((__bss_end__ - __bss_start__)/4) /* Size of the zero-initialized data section in words */ + + __zero_table_end__ = .; + + } > m33_nvm_sel + + /* A section for performance-sensitive or critical functions that need to be executed in SRAM */ + .app_code_ram : ALIGN(4) + { + KEEP(*(.cy_sram_code)) + KEEP(*(.cy_ramfunc)) + KEEP(*(.text.cy_os_common)) + *cy_syslib_ext.*(.text*) + *cy_syslib.*(.text*) + *cy_smif.*(.text*) + *cy_smif_memnum.*(.text*) + *cy_smif_memslot.*(.text*) + *cy_smif_sfdp.*(.text*) + *cy_smif_hb_flash.*(.text*) + *mtb_hal_memoryspi.*(.text*) + *mtb_serial_memory.*(.text*) + *freertos/Source*.*(.text*) + *cy_clib_support*.*(.text*) + *cy_mutex_pool*.*(.text*) + *cy_time.*(.text*) + *cyabs_*.*(.text*) + *cy_worker_thread.*(.text*) + *cmsis*.*(.text*) + + /* section information for utest */ + . = ALIGN(4); + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* section information for initialization */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + . = ALIGN(4); + } > m33_code_sel AT > m33_nvm_sel + + + /* A section for the vector table */ + .ram_vectors (NOLOAD) : ALIGN(VECTORS_ALIGNMENT) + { + KEEP(*(.ram_vectors)) + } > m33_data + + /* A section for initialized data memory */ + .data : ALIGN(4) + { + __data_start__ = .; + + *(.data*) + KEEP(*(.jcr*)) + + . = ALIGN(4); + + __data_end__ = .; + } > m33_data AT > m33_nvm_sel + + /* A section for non-initialized data memory */ + .bss(NOLOAD) : ALIGN(4) + { + __bss_start__ = .; + + *(.bss*) + *(COMMON) + + . = ALIGN(4); + + __bss_end__ = .; + } > m33_data + + /* A section for variables that should not be initialized during the device startup */ + .noinit (NOLOAD) : + { + KEEP(*(.noinit)) + } > m33_data + + /* A section for the heap memory */ + .heap(NOLOAD) : ALIGN(8) + { + __HeapBase = .; + __end__ = .; + end = __end__; + + KEEP(*(.heap*)) + + . = ORIGIN(m33_data) + LENGTH(m33_data) - __StackSize; + __HeapLimit = .; + } > m33_data + + /* Define stack top, and stack limit */ + __StackTop = ORIGIN(m33_data) + LENGTH(m33_data); + __StackLimit = __StackTop - __StackSize; + PROVIDE(__stack = __StackTop); + + /* Check if data + stack still allows for Heap to be placed */ + ASSERT( + __HeapLimit > __HeapBase, + "Error: RAM region overflowed with stack. Ensure that the stack size is within the available RAM." + ) + + /* A section for shared RAM memory where only the Cortex-M33 Non Secure can allocate data but all cores can access */ + .cy_sharedmem(NOLOAD) : ALIGN(4) + { + KEEP(*(.cy_sharedmem)) + + . = ALIGN(4); + } > m33_allocatable_shared + + /* A section for shared SOC memory */ + .cy_shared_socmem (NOLOAD) : ALIGN(4) + { + KEEP(*(.cy_shared_socmem)) + + . = ALIGN(4); + } > m33_m55_shared + + + /* Reserve a trail space for the signature for the bootloader - do not place any code here */ + .cy_trailer(NOLOAD) : + { + } > m33_trailer_sel + +} diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/config/boot_with_extended_boot.json b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/config/boot_with_extended_boot.json new file mode 100644 index 00000000..843eb74a --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/config/boot_with_extended_boot.json @@ -0,0 +1,65 @@ +{ + "schema-version": 1.0, + "content": [ + { + "name": "relocate_proj_cm33_ns", + "description": "relocate the hex to a programmable (S-BUS) address", + "enabled": true, + "commands": [ + { + "command": "hex-relocate", + "inputs": [ + { + "file": "../Debug/rtthread.hex", + "regions": [ + { "start": "0x02000000", "size": "0x00080000", "dest": "0x22000000" }, + { "start": "0x04000000", "size": "0x00100000", "dest": "0x24000000" }, + { "start": "0x06000000", "size": "0x00500000", "dest": "0x26000000" }, + { "start": "0x08000000", "size": "0x01000000", "dest": "0x60000000" }, + { "start": "0x0C000000", "size": "0x01000000", "dest": "0x64000000" }, + { "start": "0x12000000", "size": "0x00080000", "dest": "0x32000000" }, + { "start": "0x14000000", "size": "0x00100000", "dest": "0x34000000" }, + { "start": "0x16000000", "size": "0x00500000", "dest": "0x36000000" }, + { "start": "0x18000000", "size": "0x01000000", "dest": "0x70000000" }, + { "start": "0x1C000000", "size": "0x01000000", "dest": "0x74000000" } + ] + } + ], + "outputs": [ + { + "file": "../Debug/rtthread.hex" + } + ] + } + ] + }, + { + "name": "merge", + "description": "combine individual project hex files into a single hex", + "enabled": true, + "commands" : + [ + { + "command" : "merge", + "inputs" : + [ + { + "file" : "../Debug/rtthread.hex" + }, + { + "file" : "../tools/edgeprotecttools/cm33_s_signed_fw/proj_cm33_s_signed.hex" + } + ], + "outputs" : + [ + { + "file" : "../Debug/rtthread.hex", + "format" : "ihex", + "overlap" : "ignore" + } + ] + } + ] + } + ] +} diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/config/boot_with_extended_boot_scons.json b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/config/boot_with_extended_boot_scons.json new file mode 100644 index 00000000..f8ed7d35 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/config/boot_with_extended_boot_scons.json @@ -0,0 +1,65 @@ +{ + "schema-version": 1.0, + "content": [ + { + "name": "relocate_proj_cm33_ns", + "description": "relocate the hex to a programmable (S-BUS) address", + "enabled": true, + "commands": [ + { + "command": "hex-relocate", + "inputs": [ + { + "file": "rtthread.hex", + "regions": [ + { "start": "0x02000000", "size": "0x00080000", "dest": "0x22000000" }, + { "start": "0x04000000", "size": "0x00100000", "dest": "0x24000000" }, + { "start": "0x06000000", "size": "0x00500000", "dest": "0x26000000" }, + { "start": "0x08000000", "size": "0x01000000", "dest": "0x60000000" }, + { "start": "0x0C000000", "size": "0x01000000", "dest": "0x64000000" }, + { "start": "0x12000000", "size": "0x00080000", "dest": "0x32000000" }, + { "start": "0x14000000", "size": "0x00100000", "dest": "0x34000000" }, + { "start": "0x16000000", "size": "0x00500000", "dest": "0x36000000" }, + { "start": "0x18000000", "size": "0x01000000", "dest": "0x70000000" }, + { "start": "0x1C000000", "size": "0x01000000", "dest": "0x74000000" } + ] + } + ], + "outputs": [ + { + "file": "build/rtthread.hex" + } + ] + } + ] + }, + { + "name": "merge", + "description": "combine individual project hex files into a single hex", + "enabled": true, + "commands" : + [ + { + "command" : "merge", + "inputs" : + [ + { + "file" : "build/rtthread.hex" + }, + { + "file" : "../../../tools/edgeprotecttools/cm33_s_signed_fw/proj_cm33_s_signed.hex" + } + ], + "outputs" : + [ + { + "file" : "build/rtthread.hex", + "format" : "ihex", + "overlap" : "ignore" + } + ] + } + ] + } + ] +} diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/figures/1.png b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/figures/1.png new file mode 100644 index 00000000..84f25ca8 Binary files /dev/null and b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/figures/1.png differ diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/figures/2.png b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/figures/2.png new file mode 100644 index 00000000..71b0cdb8 Binary files /dev/null and b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/figures/2.png differ diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/mklinks.bat b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/mklinks.bat new file mode 100644 index 00000000..39e904f2 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/mklinks.bat @@ -0,0 +1,7 @@ +@echo off +cd /d "%~dp0" +@echo on +mklink /J rt-thread ..\..\..\rt-thread +mklink /J libraries ..\..\..\libraries +mklink /J libs ..\..\libs +mklink /J tools ..\..\..\tools \ No newline at end of file diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/rtconfig.h b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/rtconfig.h new file mode 100644 index 00000000..157cb3c9 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/rtconfig.h @@ -0,0 +1,395 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib) */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 1024 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 2048 + +/* kservice optimization */ + +#define RT_KSERVICE_USING_STDLIB +/* end of kservice optimization */ +#define RT_USING_DEBUG +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_MEMHEAP +#define RT_MEMHEAP_FAST_MODE +#define RT_USING_MEMHEAP_AS_HEAP +#define RT_USING_MEMHEAP_AUTO_BINDING +#define RT_USING_HEAP +/* end of Memory Management */ + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 1024 +#define RT_CONSOLE_DEVICE_NAME "uart5" +/* end of Kernel Device Object */ +#define RT_VER_NUM 0x50002 +/* end of RT-Thread Kernel */ + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_POSIX +#define DFS_USING_WORKDIR +#define DFS_FD_MAX 16 +#define RT_USING_DFS_V1 +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_LFN_UNICODE_0 +#define RT_DFS_ELM_LFN_UNICODE 0 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +#define RT_DFS_ELM_REENTRANT +#define RT_DFS_ELM_MUTEX_TIMEOUT 3000 +/* end of elm-chan's FatFs, Generic FAT Filesystem Module */ +#define RT_USING_DFS_DEVFS +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_RB_BUFSZ 128 +#define RT_USING_PIN + +/* Using USB */ + +/* end of Using USB */ +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Utilities */ + +/* end of Utilities */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ + +/* WCH HAL & SDK Drivers */ + +/* end of WCH HAL & SDK Drivers */ + +/* AT32 HAL & SDK Drivers */ + +/* end of AT32 HAL & SDK Drivers */ + +/* HC32 DDL Drivers */ + +/* end of HC32 DDL Drivers */ + +/* NXP HAL & SDK Drivers */ + +/* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ + +/* FT32 HAL & SDK Drivers */ + +/* end of FT32 HAL & SDK Drivers */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ + +/* Hardware Drivers Config */ + +/* Select SOC Multi Core Mode */ + +#define SOC_Enable_CM55 +/* end of Select SOC Multi Core Mode */ +#define SOC_SERIES_IFX_PSOCE84 +#define KIT_PROCE84_EVK_M33 + +/* Onboard Peripheral Drivers */ + +#define BSP_USING_USB_TO_UART +/* end of Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_IPC +#define BSP_USING_UART +#define BSP_USING_UART2 +#define BSP_USING_UART5 +/* end of On-chip Peripheral Drivers */ +/* end of Hardware Drivers Config */ + +#endif diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/rtconfig.py b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/rtconfig.py new file mode 100644 index 00000000..b0c9e974 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC/rtconfig.py @@ -0,0 +1,135 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m33' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armclang' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m33 -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections -nostartfiles' + CFLAGS = DEVICE + ' -g -Wall -pipe' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O3 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O ihex $TARGET rtthread.hex\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'armclang': + # toolchains + CC = 'armclang' + CXX = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m4 ' + CFLAGS += ' -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 ' + CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' + CFLAGS += ' -gdwarf-3 -ffunction-sections ' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' + LFLAGS += ' --list rt-thread.map ' + LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" ' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' + + EXEC_PATH += '/ARM/ARMCLANG/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O1' # armclang recommend + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.config b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.config new file mode 100644 index 00000000..72b9f291 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.config @@ -0,0 +1,1397 @@ +# Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib) + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=1024 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048 + +# +# kservice optimization +# +CONFIG_RT_KSERVICE_USING_STDLIB=y +# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +# end of kservice optimization + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_INIT is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +CONFIG_RT_USING_MEMHEAP=y +CONFIG_RT_MEMHEAP_FAST_MODE=y +# CONFIG_RT_MEMHEAP_BEST_MODE is not set +# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set +CONFIG_RT_USING_MEMHEAP_AS_HEAP=y +CONFIG_RT_USING_MEMHEAP_AUTO_BINDING=y +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=1024 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart2" +# end of Kernel Device Object + +CONFIG_RT_VER_NUM=0x50002 +# CONFIG_RT_USING_STDC_ATOMIC is not set +# end of RT-Thread Kernel + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_POSIX=y +CONFIG_DFS_USING_WORKDIR=y +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_DFS_FD_MAX=16 +CONFIG_RT_USING_DFS_V1=y +# CONFIG_RT_USING_DFS_V2 is not set +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set +CONFIG_RT_DFS_ELM_LFN_UNICODE=0 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 +# end of elm-chan's FatFs, Generic FAT Filesystem Module + +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_CROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_TMPFS is not set +# CONFIG_RT_USING_DFS_MQUEUE is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=128 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set +# CONFIG_RT_USING_KTIME is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# CONFIG_RT_USING_VBUS is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_NES_SIMULATOR is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_VECTOR is not set +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_MM32 is not set + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers + +# +# HC32 DDL Drivers +# +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set +# end of HC32 DDL Drivers + +# +# NXP HAL & SDK Drivers +# +# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set +# end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32VW55X_WIFI is not set +# end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK + +# +# FT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# end of FT32 HAL & SDK Drivers +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90384 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# CONFIG_PKG_USING_QMI8658 is not set +# CONFIG_PKG_USING_ICM20948 is not set +# CONFIG_PKG_USING_SCD4X is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_LCD_SPI_DRIVER is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SEAN_WS2812B is not set +# CONFIG_PKG_USING_IC74HC165 is not set +# CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_CAN_UDS is not set +# CONFIG_PKG_USING_ISOTP_C is not set +# CONFIG_PKG_USING_IKUNLED is not set +# CONFIG_PKG_USING_INS5T8025 is not set +# CONFIG_PKG_USING_IRUART is not set +# CONFIG_PKG_USING_ST7305 is not set +# CONFIG_PKG_USING_TM1668 is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +# CONFIG_RT_CHERRYUSB_DEVICE is not set +# CONFIG_RT_CHERRYUSB_HOST is not set + +# +# Hardware Drivers Config +# +CONFIG_SOC_SERIES_IFX_PSOCE84=y +CONFIG_KIT_PROCE84_EVK_M55=y + +# +# Onboard Peripheral Drivers +# +CONFIG_BSP_USING_USB_TO_UART=y +# CONFIG_BSP_USING_AUDIO is not set +# CONFIG_BSP_USING_AHT20 is not set +# CONFIG_BSP_USING_USB is not set +# CONFIG_BSP_USING_FREERTOS is not set +# CONFIG_BSP_USING_LSM6DS3 is not set +# end of Onboard Peripheral Drivers + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_CANFD is not set +CONFIG_BSP_USING_IPC=y +# CONFIG_BSP_USING_I2C is not set +CONFIG_BSP_USING_UART=y +# CONFIG_BSP_USING_UART1 is not set +CONFIG_BSP_USING_UART2=y +# CONFIG_BSP_USING_UART5 is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_HYPERAM is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_TIM is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_SDIO is not set +# CONFIG_BSP_USING_LCD is not set +# CONFIG_BSP_USING_FILESYSTEM is not set +# CONFIG_USING_LVGL is not set +# end of On-chip Peripheral Drivers + +# +# Board extended module Drivers +# +# CONFIG_RT_USING_WIFI_HOST_DRIVER is not set +# end of Board extended module Drivers +# end of Hardware Drivers Config diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.cproject b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.cproject new file mode 100644 index 00000000..d9261db8 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.cproject @@ -0,0 +1,272 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.gitignore b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.gitignore new file mode 100644 index 00000000..f5de05e5 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h +!edgeprotecttools.exe +/makefile.targets diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.project b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.project new file mode 100644 index 00000000..560cbede --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.project @@ -0,0 +1,29 @@ + + + project + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + com.cypress.studio.app.cymodusnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + Edgi_Talk_M55_IPC + + diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.settings/.OpenOCD.Debug.rttlaunch b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.settings/.OpenOCD.Debug.rttlaunch new file mode 100644 index 00000000..5bb288b6 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.settings/.OpenOCD.Debug.rttlaunch @@ -0,0 +1,58 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.settings/.rtmenus b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.settings/.rtmenus new file mode 100644 index 00000000..28dc3462 Binary files /dev/null and b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.settings/.rtmenus differ diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.settings/Edgi_Talk_M55_IPC.OpenOCD.DAPLink.Debug.rttlaunch b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.settings/Edgi_Talk_M55_IPC.OpenOCD.DAPLink.Debug.rttlaunch new file mode 100644 index 00000000..aa717ac4 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.settings/Edgi_Talk_M55_IPC.OpenOCD.DAPLink.Debug.rttlaunch @@ -0,0 +1,65 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.settings/Edgi_Talk_M55_IPC.OpenOCD.Debug.rttlaunch b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.settings/Edgi_Talk_M55_IPC.OpenOCD.Debug.rttlaunch new file mode 100644 index 00000000..2c0a72a8 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.settings/Edgi_Talk_M55_IPC.OpenOCD.Debug.rttlaunch @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.settings/ilg.gnumcueclipse.managedbuild.cross.arm.prefs b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.settings/ilg.gnumcueclipse.managedbuild.cross.arm.prefs new file mode 100644 index 00000000..09800d8f --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.settings/ilg.gnumcueclipse.managedbuild.cross.arm.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +toolchain.path.1287942917=${toolchain_install_path}/ARM/GNU_Tools_for_ARM_Embedded_Processors/13.3/bin diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.settings/language.settings.xml b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.settings/language.settings.xml new file mode 100644 index 00000000..6abf005e --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.settings/language.settings.xml @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.settings/local_temp_storage.prefs b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.settings/local_temp_storage.prefs new file mode 100644 index 00000000..2be04c38 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.settings/local_temp_storage.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +temp.toolchain.exec.path=E\:\\SomeIDE\\RT-ThreadStudio\\repo\\Extract\\ToolChain_Support_Packages\\ARM\\GNU_Tools_for_ARM_Embedded_Processors\\13.3/bin diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.settings/org.eclipse.core.runtime.prefs b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.settings/org.eclipse.core.runtime.prefs new file mode 100644 index 00000000..9f1acfcf --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.settings/org.eclipse.core.runtime.prefs @@ -0,0 +1,3 @@ +content-types/enabled=true +content-types/org.eclipse.cdt.core.asmSource/file-extensions=s +eclipse.preferences.version=1 \ No newline at end of file diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.settings/projcfg.ini b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.settings/projcfg.ini new file mode 100644 index 00000000..63cd06e1 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/.settings/projcfg.ini @@ -0,0 +1,20 @@ +#RT-Thread Studio Project Configuration +#Thu Mar 26 17:40:49 CST 2026 +project_type=rt-thread +chip_name=CY8C624ALQI_S2D42 +os_branch=full +example_name= +os_version=5.0.2 +selected_rtt_version=5.0.2 +cfg_version=v3.0 +board_base_nano_proj=False +is_use_scons_build=True +output_project_path=D\:\\Desktop\\Talk\\sdk-bsp-psoc_e84-edgi-talk\\projects\\Edgi_Talk_IPC +project_base_bsp=true +hardware_adapter=KitProg3 +project_name=Edgi_Talk_M55_IPC +is_base_example_project=True +board_name=psoce84 +device_vendor=Infineon +bsp_path=repo/Extract/Board_Support_Packages/Infineon/PSOC62-IFX-PROTO-KIT/1.0.0 +bsp_version=1.0.0 diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/Kconfig b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/Kconfig new file mode 100644 index 00000000..ed410f25 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/Kconfig @@ -0,0 +1,34 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "rt-thread" + +# you can change the RTT_ROOT default "rt-thread" +# example : default "F:/git_repositories/rt-thread" + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +config ENV_DIR + string + option env="ENV_ROOT" + default "/" + +config PLATFORM_DIR + string + option env="PLATFORM_DIR" + default "D:/Desktop/Talk/sdk-bsp-psoc_e84-edgi-talk/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/platform" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "$RTT_DIR/../libraries/components/CherryUSB-1.6.0/Kconfig.rtt" +source "$RTT_DIR/../libraries/M55_Config/Kconfig" diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/README.md b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/README.md new file mode 100644 index 00000000..a69fff91 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/README.md @@ -0,0 +1,164 @@ +# Edgi_Talk_M55_IPC Dual-Core Communication Example Project + +[**中文**](./README_zh.md) | **English** + +## Overview + +This project implements **IPC (Inter-Processor Communication)** dual-core communication on the **Edgi-Talk M55 core**, demonstrating message passing between **Cortex-M55** and **Cortex-M33**. + +M55 acts as the **receiver and responder**, receiving "Hello M33" messages from M33 and replying with "Hello M55". + +## Default Configuration + +* Response mode: Automatic reply +* Message format: ASCII encoded text messages +* Uses Infineon PSoC E84 on-chip IPC Pipe hardware + +## Build and Flash + +1. Build the project using RT-Thread Studio or SCons. +2. Flash firmware to M55 core via KitProg3 (DAP). +3. Both M33 and M55 projects must be built and flashed for dual-core communication. +4. Connect serial port to view communication logs as shown below: + +![alt text](figures/1.png) + +## Usage + +### 1. Configuration and Build + +Open in RT-Thread Studio: + +``` +RT-Thread Settings -> Hardware Drivers Config -> On-chip Peripheral Drivers +``` + +Check `Enable IPC` option. + +### 2. Run Example + +In M55 serial terminal, type: + +``` +msh> ipc_test_run +``` + +M55 will start a listener thread, waiting for messages from M33 and automatically replying. + +### 3. Observe Output + +**M55 Output Example**: + +``` +======================================== +[M55] IPC Listener Running +---------------------------------------- +Mode: Receiver & Responder +Peer: Cortex-M33 +Response: Hello M55 +======================================== + +[M55] RX <- [M33]: "Hello M33" | Seq: 1 | Time: 1250 ms +[M55] TX -> [M33]: "Hello M55" | Seq: 1 | Time: 1252 ms +[M55] RX <- [M33]: "Hello M33" | Seq: 2 | Time: 2250 ms +[M55] TX -> [M33]: "Hello M55" | Seq: 2 | Time: 2252 ms +---------------------------------------- +[M55] Statistics: RX=10, TX=10 +---------------------------------------- +``` + +**Corresponding M33 Output**: + +``` +======================================== +[M33] IPC Demo Started +---------------------------------------- +Mode: Sender +Target: Cortex-M55 +Message: Hello M33 +Interval: 1000 ms +======================================== + +[M33] TX -> [M55]: "Hello M33" | Seq: 1 | Time: 1234 ms +[M33] RX <- [M55]: "Hello M55" | Seq: 1 | Time: 1256 ms +[M33] TX -> [M55]: "Hello M33" | Seq: 2 | Time: 2234 ms +[M33] RX <- [M55]: "Hello M55" | Seq: 2 | Time: 2256 ms +---------------------------------------- +[M33] Statistics: TX=10, RX=10 +---------------------------------------- +``` + +## Data Protocol + +IPC communication uses the `edge_rc_frame_t` structure: + +```c +typedef struct { + uint8_t client_id; // Client ID + uint16_t intr_mask; // Interrupt mask + uint8_t role; // Role identifier (M33/M55_ECHO) + uint32_t magic; // Magic word (0x5243444DU) + uint32_t seq; // Sequence number + uint16_t channel[8]; // 8-channel data (stores ASCII messages) + uint32_t checksum; // Checksum +} edge_rc_frame_t; +``` + +Message "Hello M55" encoding: + +```c +channel[0] = 0x4865 /* 'He' */ +channel[1] = 0x6C6C /* 'll' */ +channel[2] = 0x6F20 /* 'o ' (space) */ +channel[3] = 0x4D35 /* 'M5' */ +channel[4] = 0x0035 /* '5' */ +``` + +## Startup Sequence + +M55 depends on M33 boot flow. Flash in this order: + +``` ++------------------+ +| Secure M33 | +| (Secure Core) | ++------------------+ + | + v ++------------------+ +| M33 | +| (IPC Sender) | ++------------------+ + | + v ++-------------------+ +| M55 | +| (IPC Receiver) | ++-------------------+ +``` + +## Hardware Connection + +This example uses Infineon PSoC E84 on-chip IPC hardware: + +* Uses IPC Pipe hardware in CM0P +* CM33 uses EP1 (Endpoint 1) +* CM55 uses EP2 (Endpoint 2) +* Uses semaphores for mutual exclusion +* No external wiring required + +## Working Principle + +1. **Receive messages**: M55 continuously reads from IPC device in a separate thread +2. **Verify messages**: Check magic word, role identifier, and checksum +3. **Parse messages**: Verify if it's a "Hello M33" message +4. **Send reply**: Construct "Hello M55" message and reply to M33 +5. **Statistics**: Print statistics every 10 messages processed + +## Configuration Parameters + +The following parameters can be modified in `libraries/HAL_Drivers/ipc_common.h`: + +* `EDGE_IPC_FRAME_POOL_SIZE`: Transmit buffer pool size (default 64) +* `EDGE_IPC_RX_QUEUE_SIZE`: Receive queue size (default 128) +* `EDGE_IPC_SEMA_RETRY_MAX`: Semaphore retry count (default 2) diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/README_zh.md b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/README_zh.md new file mode 100644 index 00000000..6f0dbcf4 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/README_zh.md @@ -0,0 +1,164 @@ +# Edgi_Talk_M55_IPC 双核通信示例工程 + +**中文** | [**English**](./README.md) + +## 简介 + +本工程在 **Edgi-Talk M55 核心**上实现 **IPC（Inter-Processor Communication）** 双核通信功能，演示了 **Cortex-M55** 与 **Cortex-M33** 之间的消息传递机制。 + +M55 作为**接收端和响应端**，接收来自 M33 的 "Hello M33" 消息，并回复 "Hello M55"。 + +## 默认配置 + +* 响应模式：自动回复 +* 消息格式：ASCII 编码的文本消息 +* 使用 Infineon PSoC E84 片内 IPC Pipe 硬件 + +## 编译与下载 + +1. 使用 RT-Thread Studio 或 SCons 编译工程。 +2. 通过 KitProg3 (DAP) 下载固件到 M55 核心。 +3. 同时需要编译并下载 M33 工程才能完成双核通信。 +4. 连接串口查看通信日志，输出如下如图： + +![alt text](figures/1.png) + +## 使用方法 + +### 1. 配置和编译 + +在 RT-Thread Studio 中打开： + +``` +RT-Thread Settings -> Hardware Drivers Config -> On-chip Peripheral Drivers +``` + +勾选 `Enable IPC` 选项。 + +### 2. 运行示例 + +在 M55 的串口终端输入： + +``` +msh> ipc_test_run +``` + +M55 将启动监听线程，等待来自 M33 的消息并自动回复。 + +### 3. 观察输出 + +**M55 输出示例：** + +``` +======================================== +[M55] IPC Listener Running +---------------------------------------- +Mode: Receiver & Responder +Peer: Cortex-M33 +Response: Hello M55 +======================================== + +[M55] RX <- [M33]: "Hello M33" | Seq: 1 | Time: 1250 ms +[M55] TX -> [M33]: "Hello M55" | Seq: 1 | Time: 1252 ms +[M55] RX <- [M33]: "Hello M33" | Seq: 2 | Time: 2250 ms +[M55] TX -> [M33]: "Hello M55" | Seq: 2 | Time: 2252 ms +---------------------------------------- +[M55] Statistics: RX=10, TX=10 +---------------------------------------- +``` + +**对应的 M33 输出：** + +``` +======================================== +[M33] IPC Demo Started +---------------------------------------- +Mode: Sender +Target: Cortex-M55 +Message: Hello M33 +Interval: 1000 ms +======================================== + +[M33] TX -> [M55]: "Hello M33" | Seq: 1 | Time: 1234 ms +[M33] RX <- [M55]: "Hello M55" | Seq: 1 | Time: 1256 ms +[M33] TX -> [M55]: "Hello M33" | Seq: 2 | Time: 2234 ms +[M33] RX <- [M55]: "Hello M55" | Seq: 2 | Time: 2256 ms +---------------------------------------- +[M33] Statistics: TX=10, RX=10 +---------------------------------------- +``` + +## 数据协议 + +IPC 通信使用 `edge_rc_frame_t` 结构体： + +```c +typedef struct { + uint8_t client_id; // 客户端 ID + uint16_t intr_mask; // 中断掩码 + uint8_t role; // 角色标识 (M33/M55_ECHO) + uint32_t magic; // 魔术字 (0x5243444DU) + uint32_t seq; // 序列号 + uint16_t channel[8]; // 8通道数据（存储 ASCII 消息） + uint32_t checksum; // 校验和 +} edge_rc_frame_t; +``` + +消息 "Hello M55" 编码方式： + +```c +channel[0] = 0x4865 /* 'He' */ +channel[1] = 0x6C6C /* 'll' */ +channel[2] = 0x6F20 /* 'o ' (space) */ +channel[3] = 0x4D35 /* 'M5' */ +channel[4] = 0x0035 /* '5' */ +``` + +## 启动流程 + +M55 依赖 M33 启动流程，烧录顺序如下： + +``` ++------------------+ +| Secure M33 | +| (安全内核启动) | ++------------------+ + | + v ++------------------+ +| M33 | +| (IPC 发送端) | ++------------------+ + | + v ++-------------------+ +| M55 | +| (IPC 接收端) | ++-------------------+ +``` + +## 硬件连接 + +本示例使用 Infineon PSoC E84 的片内 IPC 硬件： + +* 使用 CM0P 中的 IPC Pipe 硬件 +* CM33 使用 EP1 (Endpoint 1) +* CM55 使用 EP2 (Endpoint 2) +* 使用信号量进行互斥访问 +* 不需要外部连线 + +## 工作原理 + +1. **接收消息**：M55 在独立线程中循环读取 IPC 设备 +2. **验证消息**：检查魔术字、角色标识和校验和 +3. **解析消息**：验证是否为 "Hello M33" 消息 +4. **发送回复**：构造 "Hello M55" 消息并回复给 M33 +5. **统计信息**：每处理 10 条消息打印一次统计 + +## 配置参数 + +在 `libraries/HAL_Drivers/ipc_common.h` 中可修改以下参数： + +* `EDGE_IPC_FRAME_POOL_SIZE`: 发送缓冲池大小（默认 64） +* `EDGE_IPC_RX_QUEUE_SIZE`: 接收队列大小（默认 128） +* `EDGE_IPC_SEMA_RETRY_MAX`: 信号量重试次数（默认 2） \ No newline at end of file diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/SConscript b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/SConscript new file mode 100644 index 00000000..20f7689c --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/SConstruct b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/SConstruct new file mode 100644 index 00000000..dfd7328c --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/SConstruct @@ -0,0 +1,142 @@ +import os +import sys +import rtconfig +import platform +import subprocess +import uuid + +if os.path.exists('rt-thread'): + RTT_ROOT = os.path.normpath(os.getcwd() + '/rt-thread') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../rt-thread') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except Exception as e: + print("Error message:", e) + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + sys.exit(-1) + +TARGET = 'rt-thread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env.AppendUnique(CPPPATH=[os.getcwd()]) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') +if os.path.exists(SDK_ROOT + '/libraries/components'): + libraries_path_prefix = SDK_ROOT + '/libraries/components' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/../../libraries/components' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +IFX_library = 'Packages' +rtconfig.BSP_LIBRARY_TYPE = IFX_library + +# set spawn +def ourspawn(sh, escape, cmd, args, e): + filename = str(uuid.uuid4()) + newargs = ' '.join(args[1:]) + cmdline = cmd + " " + newargs + if (len(cmdline) > 16 * 1024): + f = open(filename, 'w') + f.write(' '.join(args[1:]).replace('\\', '/')) + f.close() + # exec + cmdline = cmd + " @" + filename + proc = subprocess.Popen(cmdline, stdin=subprocess.PIPE, stdout=subprocess.PIPE, + stderr=subprocess.PIPE, shell = False, env = e) + data, err = proc.communicate() + rv = proc.wait() + def res_output(_output, _s): + if len(_s): + if isinstance(_s, str): + _output(_s) + elif isinstance(_s, bytes): + _output(str(_s, 'UTF-8')) + else: + _output(str(_s)) + res_output(sys.stderr.write, err) + res_output(sys.stdout.write, data) + if os.path.isfile(filename): + os.remove(filename) + return rv + +if platform.system() == 'Windows': + env['SPAWN'] = ourspawn + +# Add project libs with VariantDir +if os.path.exists(os.path.join(os.getcwd(), "libs", "SConscript")): + env.VariantDir('build/libs', 'libs', duplicate=0) +else: + env.VariantDir('build/libs', '../../libs', duplicate=0) + objs.extend(SConscript('../../libs/SConscript', variant_dir='build/libs', duplicate=0)) + +if os.path.exists(os.path.join(os.getcwd(), "libraries")): + # Set VariantDir for libraries + env.VariantDir('build/libraries/HAL_Drivers', 'libraries/HAL_Drivers', duplicate=0) + env.VariantDir('build/libraries/components', 'libraries/components', duplicate=0) + env.VariantDir('build/libraries/M55_Config/board', 'libraries/M55_Config/board', duplicate=0) + env.VariantDir('build/libraries/Common/board', 'libraries/Common/board', duplicate=0) + + objs.extend(SConscript('libraries/HAL_Drivers/SConscript', variant_dir='build/libraries/HAL_Drivers', duplicate=0)) + objs.extend(SConscript('libraries/components/Infineon_cmsis-latest/SConscript', variant_dir='build/libraries/components/Infineon_cmsis-latest', duplicate=0)) + objs.extend(SConscript('libraries/components/Infineon_core-lib-latest/SConscript', variant_dir='build/libraries/components/Infineon_core-lib-latest', duplicate=0)) + objs.extend(SConscript('libraries/components/mtb-device-support-pse8xxgp/hal/SConscript', variant_dir='build/libraries/components/mtb-device-support-pse8xxgp/hal', duplicate=0)) + objs.extend(SConscript('libraries/components/mtb-device-support-pse8xxgp/pdl/SConscript', variant_dir='build/libraries/components/mtb-device-support-pse8xxgp/pdl', duplicate=0)) + objs.extend(SConscript('libraries/components/async-transfer/SConscript', variant_dir='build/libraries/components/async-transfer', duplicate=0)) + objs.extend(SConscript('libraries/components/mtb-device-support-pse8xxgp/device-utils/syspm/SConscript', variant_dir='build/libraries/components/mtb-device-support-pse8xxgp/device-utils/syspm', duplicate=0)) + objs.extend(SConscript('libraries/components/serial-memory/SConscript', variant_dir='build/libraries/components/serial-memory', duplicate=0)) + objs.extend(SConscript('libraries/components/Infineon_retarget-io-latest/SConscript', variant_dir='build/libraries/components/Infineon_retarget-io-latest', duplicate=0)) + objs.extend(SConscript('libraries/components/ASRC/SConscript', variant_dir='build/libraries/components/ASRC', duplicate=0)) + objs.extend(SConscript('libraries/components/mtb-srf/SConscript', variant_dir='build/libraries/components/mtb-srf', duplicate=0)) + objs.extend(SConscript('libraries/components/mtb-ipc/SConscript', variant_dir='build/libraries/components/mtb-ipc', duplicate=0)) + objs.extend(SConscript('libraries/components/littlefs/SConscript', variant_dir='build/libraries/components/littlefs', duplicate=0)) + objs.extend(SConscript('libraries/components/SConscript', variant_dir='build/libraries/components', duplicate=0)) + objs.extend(SConscript('libraries/Common/board/SConscript', variant_dir='build/libraries/Common/board', duplicate=0)) +else: + # Set VariantDir for external libraries + env.VariantDir('build/libraries/HAL_Drivers', '../../../libraries/HAL_Drivers', duplicate=0) + env.VariantDir('build/libraries/components', '../../../libraries/components', duplicate=0) + env.VariantDir('build/libraries/M55_Config/board', '../../../libraries/M55_Config/board', duplicate=0) + env.VariantDir('build/libraries/Common/board', '../../../libraries/Common/board', duplicate=0) + + objs.extend(SConscript('../../../libraries/HAL_Drivers/SConscript', variant_dir='build/libraries/HAL_Drivers', duplicate=0)) + objs.extend(SConscript('../../../libraries/components/Infineon_cmsis-latest/SConscript', variant_dir='build/libraries/components/Infineon_cmsis-latest', duplicate=0)) + objs.extend(SConscript('../../../libraries/components/Infineon_core-lib-latest/SConscript', variant_dir='build/libraries/components/Infineon_core-lib-latest', duplicate=0)) + objs.extend(SConscript('../../../libraries/components/mtb-device-support-pse8xxgp/hal/SConscript', variant_dir='build/libraries/components/mtb-device-support-pse8xxgp/hal', duplicate=0)) + objs.extend(SConscript('../../../libraries/components/mtb-device-support-pse8xxgp/pdl/SConscript', variant_dir='build/libraries/components/mtb-device-support-pse8xxgp/pdl', duplicate=0)) + objs.extend(SConscript('../../../libraries/components/async-transfer/SConscript', variant_dir='build/libraries/components/async-transfer', duplicate=0)) + objs.extend(SConscript('../../../libraries/components/mtb-device-support-pse8xxgp/device-utils/syspm/SConscript', variant_dir='build/libraries/components/mtb-device-support-pse8xxgp/device-utils/syspm', duplicate=0)) + objs.extend(SConscript('../../../libraries/components/serial-memory/SConscript', variant_dir='build/libraries/components/serial-memory', duplicate=0)) + objs.extend(SConscript('../../../libraries/components/Infineon_retarget-io-latest/SConscript', variant_dir='build/libraries/components/Infineon_retarget-io-latest', duplicate=0)) + objs.extend(SConscript('../../../libraries/components/ASRC/SConscript', variant_dir='build/libraries/components/ASRC', duplicate=0)) + objs.extend(SConscript('../../../libraries/components/mtb-srf/SConscript', variant_dir='build/libraries/components/mtb-srf', duplicate=0)) + objs.extend(SConscript('../../../libraries/components/mtb-ipc/SConscript', variant_dir='build/libraries/components/mtb-ipc', duplicate=0)) + objs.extend(SConscript('../../../libraries/components/littlefs/SConscript', variant_dir='build/libraries/components/littlefs', duplicate=0)) + objs.extend(SConscript('../../../libraries/components/SConscript', variant_dir='build/libraries/components', duplicate=0)) + objs.extend(SConscript('../../../libraries/Common/board/SConscript', variant_dir='build/libraries/Common/board', duplicate=0)) + +# make a building +DoBuilding(TARGET, objs) diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/applications/SConscript b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/applications/SConscript new file mode 100644 index 00000000..034056ec --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/applications/SConscript @@ -0,0 +1,16 @@ +import rtconfig +from building import * +import os + +cwd = GetCurrentDir() +path = [cwd] +src = Glob('*.c') + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = path) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/applications/main.c b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/applications/main.c new file mode 100644 index 00000000..3f8b55f8 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/applications/main.c @@ -0,0 +1,158 @@ +#include +#include +#include +#include + +#include "drv_ipc.h" + +#define LED_PIN_G GET_PIN(16, 6) + +static rt_device_t g_ipc_dev = RT_NULL; +static rt_thread_t g_ipc_thread = RT_NULL; + +static void ipc_demo_run(void) +{ + edge_rc_frame_t rx_frame; + edge_rc_frame_t tx_frame; + rt_uint32_t rx_count = 0; + rt_uint32_t tx_count = 0; + + rt_kprintf("\r\n"); + rt_kprintf("========================================\r\n"); + rt_kprintf("[M55] IPC Listener Running\r\n"); + rt_kprintf("----------------------------------------\r\n"); + rt_kprintf("Mode: Receiver & Responder\r\n"); + rt_kprintf("Peer: Cortex-M33\r\n"); + rt_kprintf("Response: Hello M55\r\n"); + rt_kprintf("========================================\r\n"); + rt_kprintf("\r\n"); + + while (1) { + /* 接收消息 */ + if (rt_device_read(g_ipc_dev, 0, &rx_frame, 1) == 1) { + /* 验证消息 */ + if (rx_frame.magic == RC_MAGIC_WORD && + rx_frame.role == RC_ROLE_M33 && + edge_rc_checksum(&rx_frame) == rx_frame.checksum) { + + /* 检查是否是 "Hello M33" 消息 */ + if (rx_frame.channel[0] == 0x4865UL && /* 'He' */ + rx_frame.channel[1] == 0x6C6CUL && /* 'll' */ + rx_frame.channel[2] == 0x6F20UL && /* 'o ' */ + rx_frame.channel[3] == 0x4D33UL && /* 'M3' */ + rx_frame.channel[4] == 0x0033UL) { /* '3' */ + + rt_kprintf("[M55] RX <- [M33]: \"Hello M33\" | Seq: %5lu | Time: %8lu ms\r\n", + rx_frame.seq, rt_tick_get() * 1000 / RT_TICK_PER_SECOND); + rx_count++; + + /* 准备回复消息 - "Hello M55" */ + memset(&tx_frame, 0, sizeof(tx_frame)); + tx_frame.client_id = CM33_IPC_PIPE_CLIENT_ID; + tx_frame.role = RC_ROLE_M55_ECHO; + tx_frame.magic = RC_MAGIC_WORD; + tx_frame.seq = rx_frame.seq; + /* Encode "Hello M55" into channels (2 chars per channel) */ + tx_frame.channel[0] = 0x4865UL; /* 'He' in ASCII */ + tx_frame.channel[1] = 0x6C6CUL; /* 'll' in ASCII */ + tx_frame.channel[2] = 0x6F20UL; /* 'o ' in ASCII */ + tx_frame.channel[3] = 0x4D35UL; /* 'M5' in ASCII */ + tx_frame.channel[4] = 0x0035UL; /* '5' in ASCII */ + tx_frame.checksum = edge_rc_checksum(&tx_frame); + + /* 发送回复 */ + if (rt_device_write(g_ipc_dev, 0, &tx_frame, 1) == 1) { + rt_kprintf("[M55] TX -> [M33]: \"Hello M55\" | Seq: %5lu | Time: %8lu ms\r\n", + tx_frame.seq, rt_tick_get() * 1000 / RT_TICK_PER_SECOND); + tx_count++; + + /* 每 10 次交互打印统计信息 */ + if (tx_count % 10 == 0) { + rt_kprintf("----------------------------------------\r\n"); + rt_kprintf("[M55] Statistics: RX=%lu, TX=%lu\r\n", rx_count, tx_count); + rt_kprintf("----------------------------------------\r\n"); + } + } else { + rt_kprintf("[M55] Send reply failed\r\n"); + } + } + } else { + rt_kprintf("[M55] Invalid message received\r\n"); + } + } + + rt_thread_mdelay(10); + } +} + +static void ipc_demo_entry(void* parameter) +{ + (void)parameter; + ipc_demo_run(); +} + +static int ipc_test_run(void) +{ + /* 查找 IPC 设备 */ + g_ipc_dev = edge_ipc_device_find(); + if (g_ipc_dev == RT_NULL) { + if (edge_ipc_device_register() != RT_EOK) { + rt_kprintf("[M55] IPC: Device register failed\r\n"); + return -RT_ERROR; + } + g_ipc_dev = edge_ipc_device_find(); + if (g_ipc_dev == RT_NULL) { + rt_kprintf("[M55] IPC: Device not found\r\n"); + return -RT_ERROR; + } + } + + /* 打开 IPC 设备 */ + if (rt_device_open(g_ipc_dev, RT_DEVICE_OFLAG_RDWR) != RT_EOK) { + rt_kprintf("[M55] IPC: Open device failed\r\n"); + return -RT_ERROR; + } + + /* 创建 IPC 处理线程 */ + if (g_ipc_thread == RT_NULL) { + g_ipc_thread = rt_thread_create("ipc_demo", + ipc_demo_entry, + RT_NULL, + 2048, + 25, + 10); + if (g_ipc_thread == RT_NULL) { + rt_kprintf("[M55] IPC: Create thread failed\r\n"); + return -RT_ENOMEM; + } + + rt_thread_startup(g_ipc_thread); + } + + return RT_EOK; +} +MSH_CMD_EXPORT(ipc_test_run, Start M55 IPC test); + +int main(void) +{ + rt_kprintf("\r\n"); + rt_kprintf("========================================\r\n"); + rt_kprintf(" RT-Thread on Cortex-M55 Core \r\n"); + rt_kprintf("========================================\r\n"); + rt_kprintf("Command: ipc_test_run\r\n"); + rt_kprintf("Status: Running\r\n"); + rt_kprintf("========================================\r\n"); + rt_kprintf("\r\n"); + + rt_pin_mode(LED_PIN_G, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED_PIN_G, PIN_LOW); + rt_thread_mdelay(500); + rt_pin_write(LED_PIN_G, PIN_HIGH); + rt_thread_mdelay(500); + } + + return 0; +} diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/board/SConscript b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/board/SConscript new file mode 100644 index 00000000..b26ca201 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/board/SConscript @@ -0,0 +1,71 @@ +import os +import rtconfig +from building import * + +Import("SDK_LIB") + +objs = [] +cwd = GetCurrentDir() +list = os.listdir(cwd) + +# add general drivers +src = Glob('*.c') + +path = [cwd] + +startup_path_prefix = SDK_LIB +Tool_path = None +index = "mtb-device-support-pse8xxgp" + +for filename in os.listdir(startup_path_prefix): + if index in filename: + Tool_path = os.path.join(startup_path_prefix, filename) + + + +CPPDEFINES = [ + "BLHS_SUPPORT", + "COMPONENT_55500", + "COMPONENT_55500A1", + "COMPONENT_APP_KIT_PSE84_EVAL_EPC2", + "COMPONENT_CM55", + "COMPONENT_CM55_0", + "COMPONENT_Debug", + "COMPONENT_GCC_ARM", + "COMPONENT_GFXSS", + "COMPONENT_HARDFP", + "COMPONENT_HCI_UART", + "COMPONENT_MTB_DEVICE_SUPPORT", + "COMPONENT_MTB_HAL", + "COMPONENT_MW_ASYNC_TRANSFER", + "COMPONENT_MW_CMSIS", + "COMPONENT_MW_CORE_LIB", + "COMPONENT_MW_CORE_MAKE", + # "COMPONENT_MW_MTB_IPC", + # "COMPONENT_MW_MTB_SRF", + "COMPONENT_MW_RETARGET_IO", + "COMPONENT_NON_SECURE_DEVICE", + "COMPONENT_PSE84", + "COMPONENT_SM", + "CORE_NAME_CM55_0=1", + "CYBSP_MCUBOOT_HEADER_SIZE=0x400", + "CY_APPNAME_proj_cm55", + "CY_RETARGET_IO_CONVERT_LF_TO_CRLF", + "CY_SUPPORTS_DEVICE_VALIDATION", + "CY_TARGET_BOARD=APP_KIT_PSE84_EVAL_EPC2", + "DEBUG", + "PSE846GPS2DBZC4A", + "TARGET_APP_KIT_PSE84_EVAL_EPC2", + "TRXV5", + "_BAREMETAL=0", + "FLASH_BOOT", + "CY_PDL_FLASH_BOOT", + "BUILD_KIT_PROCE84_EVK_M55", +] +group = DefineGroup("Drivers", src, depend=[""], CPPPATH=path, CPPDEFINES=CPPDEFINES) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) +Return("group") diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/board/board.c b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/board/board.c new file mode 100644 index 00000000..5e8a678b --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/board/board.c @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-06-29 Rbb666 first version + * 2025-08-20 Hydevcode + */ + +#include "board.h" +#define ES8388_CTRL GET_PIN(16, 2) +#define SPEAKER_OE_CTRL GET_PIN(21, 6) +#define WIFI_OE_CTRL GET_PIN(16, 3) +#define WIFI_WL_REG_OE_CTRL GET_PIN(11, 6) +#define CTRL GET_PIN(7, 2) + +void cy_bsp_all_init(void) +{ + cy_rslt_t result; + + /* Initialize the device and board peripherals */ + result = cybsp_init(); + + /* Board init failed. Stop program execution */ + if (result != CY_RSLT_SUCCESS) + { + CY_ASSERT(0); + } +} + +void _start(void) +{ + extern int entry(void); + entry(); + while (1); + __builtin_unreachable(); +} + +void poweroff(void) +{ + rt_pin_mode(WIFI_OE_CTRL, PIN_MODE_OUTPUT); + rt_pin_write(WIFI_OE_CTRL, PIN_LOW); + + rt_pin_mode(WIFI_WL_REG_OE_CTRL, PIN_MODE_OUTPUT); + rt_pin_write(WIFI_WL_REG_OE_CTRL, PIN_LOW); + + rt_pin_mode(ES8388_CTRL, PIN_MODE_OUTPUT); + rt_pin_write(ES8388_CTRL, PIN_LOW); + + rt_pin_mode(SPEAKER_OE_CTRL, PIN_MODE_OUTPUT); + rt_pin_write(SPEAKER_OE_CTRL, PIN_LOW); + + rt_pin_mode(CTRL, PIN_MODE_OUTPUT); + rt_pin_write(CTRL, PIN_LOW); + + Cy_SysClk_PllDisable(SRSS_DPLL_LP_0_PATH_NUM); + Cy_SysPm_SystemEnterHibernate(); +} + +#ifdef RT_USING_MSH + MSH_CMD_EXPORT(poweroff, The software enables the system to shut down. Simply press the button to restart it.); +#endif + +//Mos管控制 +#define ES8388_CTRL GET_PIN(16, 2) //ES8388 电源 Enable引脚 +#define SPEAKER_OE_CTRL GET_PIN(21, 6) //功放 Enable引脚 +#define WIFI_OE_CTRL GET_PIN(16, 3) //WIFI Enable引脚 +#define WIFI_WL_REG_OE_CTRL GET_PIN(11, 6) //WiFi寄存器开关 +#define CTRL GET_PIN(7, 2) //底板 3V3 DCDC电源控制 +int en_gpio(void) +{ + rt_pin_mode(WIFI_OE_CTRL, PIN_MODE_OUTPUT); + rt_pin_write(WIFI_OE_CTRL, PIN_HIGH); + + rt_pin_mode(WIFI_WL_REG_OE_CTRL, PIN_MODE_OUTPUT); + rt_pin_write(WIFI_WL_REG_OE_CTRL, PIN_HIGH); + + rt_pin_mode(ES8388_CTRL, PIN_MODE_OUTPUT); + rt_pin_write(ES8388_CTRL, PIN_HIGH); + + rt_pin_mode(SPEAKER_OE_CTRL, PIN_MODE_OUTPUT); + rt_pin_write(SPEAKER_OE_CTRL, PIN_HIGH); + + return 0; +} +INIT_BOARD_EXPORT(en_gpio); \ No newline at end of file diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/board/board.h b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/board/board.h new file mode 100644 index 00000000..93078cf7 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/board/board.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-06-29 Rbb666 first version + * 2022-07-26 Rbb666 Add Flash Config + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "drv_common.h" +#include "drv_gpio.h" + +#include "cy_result.h" +#include "cybsp_types.h" +#include "mtb_hal.h" +#include "cybsp.h" + +#ifdef BSP_USING_USBD + #include "cy_usb_dev.h" + #include "cy_usb_dev_hid.h" +#endif + +/*SRAM CONFIG*/ +#define IFX_SRAM_SIZE (1408) +#define IFX_SRAM_END (0x26060000 + IFX_SRAM_SIZE * 1024) + +#ifdef __ARMCC_VERSION + extern int Image$$RW_IRAM1$$ZI$$Limit; + #define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) + #define HEAP_END IFX_SRAM_END +#elif __ICCARM__ + #pragma section="HEAP" + #define HEAP_BEGIN (__segment_end("HEAP")) +#else + extern unsigned int __end__; + extern unsigned int __HeapLimit; + #define HEAP_BEGIN (void*)&__end__ + #define HEAP_END (void*)&__HeapLimit +#endif + +void cy_bsp_all_init(void); + +#endif + diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/board/linker_scripts/link.ld b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/board/linker_scripts/link.ld new file mode 100644 index 00000000..cc092732 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/board/linker_scripts/link.ld @@ -0,0 +1,448 @@ +/***************************************************************************//** +* \file pse84_ns_cm55.ld +* \version 1.0.0 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright (c) (2020-2025), Cypress Semiconductor Corporation (an Infineon company) or +* an affiliate of Cypress Semiconductor Corporation. +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ +/* Specify the output format for the linker script */ +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +/* Search for libraries in the current directory */ +SEARCH_DIR(.) +/* Specify the group of libraries to link against */ +GROUP(-lgcc -lc -lnosys) +GROUP(libgcc.a libc.a libm.a libnosys.a) +/* Define the entry point of the program, which is the reset handler */ +ENTRY(Reset_Handler) + +/* Define the stack size for the application */ +/* To set stack size in application add makefile ldflags: -Wl,--defsym=APP_MSP_STACK_SIZE= */ +PROVIDE(__StackSize = DEFINED(APP_MSP_STACK_SIZE) ? APP_MSP_STACK_SIZE : 0x1000); + +/* Include the device memory definitions generated by the Device Configurator */ +/* This file is automatically generated. */ + +MEMORY +{ + m55_data_INTERNAL : ORIGIN = 0x20000000, LENGTH = 0x00040000 + m55_code_INTERNAL : ORIGIN = 0x00000000, LENGTH = 0x00040000 + m55_nvm : ORIGIN = 0x60580000, LENGTH = 0x00800000 + m55_trailer : ORIGIN = 0x60D80000, LENGTH = 0x00040000 + m55_code_secondary : ORIGIN = 0x26000000, LENGTH = 0x00060000 + m55_data_secondary : ORIGIN = 0x26060000, LENGTH = 0x00160000 + m33_m55_shared : ORIGIN = 0x261C0000, LENGTH = 0x00040000 + gfx_mem : ORIGIN = 0x26200000, LENGTH = 0x00300000 + m55_allocatable_shared : ORIGIN = 0x240FF000, LENGTH = 0x00001000 +} + +REGION_ALIAS("m55_data_sel", m55_data_INTERNAL) +REGION_ALIAS("m55_code_sel", m55_code_INTERNAL) +REGION_ALIAS("m55_nvm_sel", m55_nvm) +REGION_ALIAS("m55_trailer_sel", m55_trailer) +REGION_ALIAS("m55_code_secondary_sel", m55_code_secondary) +REGION_ALIAS("m55_data_secondary_sel", m55_data_secondary) +REGION_ALIAS("m33_m55_shared_sel", m33_m55_shared) +REGION_ALIAS("gfx_mem_sel", gfx_mem) +REGION_ALIAS("m55_allocatable_shared_sel", m55_allocatable_shared) + + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ + +/* Device definitions */ +VECTORS_ALIGNMENT = 0x400; + +/* The size of the MCU boot header area at the start of main code region */ +MCUBOOT_HEADER_SIZE = 0x400; + +/* Define the sections */ +SECTIONS +{ + /* This section reserves a space for MCUBoot header */ + .mcu_boot_header (READONLY) : ALIGN(MCUBOOT_HEADER_SIZE) + { + . += MCUBOOT_HEADER_SIZE; + } > m55_nvm_sel + + /* This section is intended to hold the main application code for the Cortex-M55 */ + /* Performance-sensitive or critical functions that need to be executed in sram are manually excluded */ + .app_code_main : ALIGN(VECTORS_ALIGNMENT) + { + __text_begin = .; + __Vectors = . ; + /* Keep the vector table */ + KEEP(*(.vectors)) + + . = ALIGN(4); + + __Vectors_End = .; + + /* Keep initializers */ + KEEP(*(.init)) + /* Keep finalizers */ + KEEP(*(.fini)) + /* Static constructors */ + *crtbegin.*(.ctors) + *crtbegin?.*(.ctors) + *(EXCLUDE_FILE(*crtend?.* *crtend.*) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + /* Static destructors and atexit() */ + *crtbegin.*(.dtors) + *crtbegin?.*(.dtors) + *(EXCLUDE_FILE(*crtend?.* *crtend.*) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + /* Read only code (constants) */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + /* Exclude certain files from this section as they will be placed in RAM */ + *(EXCLUDE_FILE(*cy_syslib.* *cy_syslib_ext.* *cy_smif.* *cy_smif_memnum.* *cy_smif_memslot.* *cy_smif_sfdp.* *cy_smif_hb_flash.* *mtb_hal_memoryspi.* *mtb_serial_memory.* *freertos/Source*.* *cy_clib_support*.* *cy_mutex_pool*.* *cy_time.* *cyabs_*.* *cy_worker_thread.* *cmsis*.*) .text*) + + . = ALIGN(4); + /* section information for utest */ + . = ALIGN(4); + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* section information for initialization */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + __text_end = .; + _etext = .; + _estack = .; + } > m55_nvm_sel + . = ALIGN(4); + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + } > m55_nvm_sel + + . = ALIGN(4); + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + } > m55_nvm_sel + + /* Exception tables for ARM architecture */ + .ARM.extab (READONLY) : ALIGN(4) + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m55_nvm_sel + + /* Exception index tables for ARM architecture */ + .ARM.exidx (READONLY) : ALIGN(4) + { + __exidx_start = .; + + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + __exidx_end = .; + } > m55_nvm_sel + + + /* Define copying of data from flash memory to RAM during the startup */ + .copy.table (READONLY) : ALIGN(4) + { + __copy_table_start__ = .; + + /* Initialized data in DTCM */ + LONG(LOADADDR(.data)) /* From load address in ext flash */ + LONG(ADDR(.data)) /* To run address in DTCM */ + LONG(SIZEOF(.data)/4) /* Size in words */ + + /* Initialized data in SOC memory */ + LONG(LOADADDR(.cy_socmem_data)) /* From load address in ext flash */ + LONG(ADDR(.cy_socmem_data)) /* To run address in SOCMEM */ + LONG(SIZEOF(.cy_socmem_data)/4) /* Size in words */ + + /* Code in ITCM */ + LONG (LOADADDR(.app_code_itcm)) /* From load address in ext flash */ + LONG (ADDR(.app_code_itcm)) /* To run address in ITCM */ + LONG (SIZEOF(.app_code_itcm)/4) /* Size in words */ + + /* Code in SOC memory */ + LONG (LOADADDR(.app_code_socmem)) /* From load address in ext flash */ + LONG (ADDR(.app_code_socmem)) /* To run address in SOCMEM */ + LONG (SIZEOF(.app_code_socmem)/4) /* Size in words */ + + __copy_table_end__ = .; + } > m55_nvm_sel + + /* Define zeroing of the uninitialized data section */ + .zero.table (READONLY): ALIGN(4) + { + __zero_table_start__ = .; + + LONG(__bss_start__) /* Start of the zero-initialized data section */ + LONG((__bss_end__ - __bss_start__)/4) /* Size of the zero-initialized data section in words */ + + __zero_table_end__ = .; + } > m55_nvm_sel + + /* A section for performance-sensitive or critical functions that need to be executed in ITCM */ + .app_code_itcm : ALIGN(16) + { + /* Reserving the first 16 bytes to avoid debug symbols (that have default address 0x0) to be confused with actual code */ + . += 16; + KEEP(*(.cy_itcm)) + KEEP(*(.cy_sram_code)) + KEEP(*(.cy_ramfunc)) + KEEP(*(.text.cy_os_common)) + *cy_syslib_ext.*(.text*) + *cy_syslib.*(.text*) + *cy_smif.*(.text*) + *cy_smif_memnum.*(.text*) + *cy_smif_memslot.*(.text*) + *cy_smif_sfdp.*(.text*) + *cy_smif_hb_flash.*(.text*) + *mtb_hal_memoryspi.*(.text*) + *mtb_serial_memory.*(.text*) + *freertos/Source*.*(.text*) + *cy_clib_support*.*(.text*) + *cy_mutex_pool*.*(.text*) + *cy_time.*(.text*) + *cyabs_*.*(.text*) + *cy_worker_thread.*(.text*) + *cmsis*.*(.text*) + + . = ALIGN(4); + } > m55_code_INTERNAL AT > m55_nvm_sel + + /* A section for the vector table */ + .ram_vectors (NOLOAD) : ALIGN(VECTORS_ALIGNMENT) + { + __ram_vectors_start__ = .; + + KEEP(*(.ram_vectors)) + + __ram_vectors_end__ = .; + } > m55_code_INTERNAL + + /* A section for less performance-sensitive or critical functions that might be executed in SOC memory */ + .app_code_socmem : ALIGN(4) + { + KEEP(*(.cy_socmem_code)) + + . = ALIGN(4); + } > m55_code_secondary AT > m55_nvm_sel + + /* A section for initialized data memory */ + .data : ALIGN(4) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + + /* Array of pointers to preinit functions */ + PROVIDE_HIDDEN (__preinit_array_start = .); + + KEEP(*(.preinit_array)) + + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + + /* Array of pointers to init functions */ + PROVIDE_HIDDEN (__init_array_start = .); + + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + + /* Array of pointers to finalizer functions */ + + PROVIDE_HIDDEN (__fini_array_start = .); + + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + + . = ALIGN(4); + + KEEP(*(.cy_dtcm)) + + . = ALIGN(4); + + __data_end__ = .; + } > m55_data_INTERNAL AT > m55_nvm_sel + + /* A section for variables that should not be initialized during the device startup */ + .noinit (NOLOAD) : ALIGN(8) + { + __noinit_start__ = .; + + KEEP(*(.noinit)) + + . = ALIGN(4); + + __noinit_end__ = .; + } > m55_data_INTERNAL + + /* A section for non-initialized data memory */ + .bss(NOLOAD) : ALIGN(4) + { + __bss_start__ = .; + + *(.bss*) + *(COMMON) + + . = ALIGN(4); + + __bss_end__ = .; + } > m55_data_INTERNAL + + __StackTop = ORIGIN(m55_data_INTERNAL) + LENGTH(m55_data_INTERNAL); + __StackLimit = __StackTop - __StackSize; + PROVIDE(__stack = __StackTop); + + /* Check if .data + .noinit + .bss + stack exceeds RAM limit in region m55_data_INTERNAL */ + ASSERT( + __StackLimit >= __bss_end__, + "Error: m55_data_INTERNAL region overflowed with stack. Ensure that the stack size is within the available RAM." + ) + + /* A section for SOC memory data */ + .cy_socmem_data : ALIGN(4) + { + KEEP(*(.cy_socmem_data)) + + . = ALIGN(4); + + } > m55_data_secondary AT > m55_nvm_sel + + /* A section for the heap memory */ + .heap(NOLOAD) : ALIGN(8) + { + __HeapBase = .; + __end__ = .; + end = __end__; + + KEEP(*(.heap*)) + + . = ORIGIN(m55_data_secondary) + LENGTH(m55_data_secondary); + + __HeapLimit = .; + } > m55_data_secondary + + /* A section for the GPU buffer */ + .cy_gpu_buf(NOLOAD) : + { + KEEP(*(.cy_gpu_buf)) + } > gfx_mem + + .reserved_socmem(NOLOAD) : + { + . = ORIGIN(m33_m55_shared) + LENGTH(m33_m55_shared); /* reserved SOC memory */ + } > m33_m55_shared + + + /* A section for shared RAM memory where only the Cortex-M55 can allocate data but all cores can access */ + .cy_sharedmem(NOLOAD) : ALIGN(4) + { + KEEP(*(.cy_sharedmem)) + + . = ALIGN(4); + } > m55_allocatable_shared + + /* Reserve a trail space for the signature for the bootloader - do not place any code here */ + .cy_trailer(NOLOAD) : + { + } > m55_trailer_sel + +} diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/figures/1.png b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/figures/1.png new file mode 100644 index 00000000..37b145c5 Binary files /dev/null and b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/figures/1.png differ diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/mklinks.bat b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/mklinks.bat new file mode 100644 index 00000000..39e904f2 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/mklinks.bat @@ -0,0 +1,7 @@ +@echo off +cd /d "%~dp0" +@echo on +mklink /J rt-thread ..\..\..\rt-thread +mklink /J libraries ..\..\..\libraries +mklink /J libs ..\..\libs +mklink /J tools ..\..\..\tools \ No newline at end of file diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/rtconfig.h b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/rtconfig.h new file mode 100644 index 00000000..67568432 --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/rtconfig.h @@ -0,0 +1,394 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib) */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 1024 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 2048 + +/* kservice optimization */ + +#define RT_KSERVICE_USING_STDLIB +/* end of kservice optimization */ +#define RT_USING_DEBUG +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_MEMHEAP +#define RT_MEMHEAP_FAST_MODE +#define RT_USING_MEMHEAP_AS_HEAP +#define RT_USING_MEMHEAP_AUTO_BINDING +#define RT_USING_HEAP +/* end of Memory Management */ + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 1024 +#define RT_CONSOLE_DEVICE_NAME "uart2" +/* end of Kernel Device Object */ +#define RT_VER_NUM 0x50002 +/* end of RT-Thread Kernel */ + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_POSIX +#define DFS_USING_WORKDIR +#define DFS_FD_MAX 16 +#define RT_USING_DFS_V1 +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_LFN_UNICODE_0 +#define RT_DFS_ELM_LFN_UNICODE 0 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +#define RT_DFS_ELM_REENTRANT +#define RT_DFS_ELM_MUTEX_TIMEOUT 3000 +/* end of elm-chan's FatFs, Generic FAT Filesystem Module */ +#define RT_USING_DFS_DEVFS +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_RB_BUFSZ 128 +#define RT_USING_PIN + +/* Using USB */ + +/* end of Using USB */ +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Utilities */ + +/* end of Utilities */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ + +/* WCH HAL & SDK Drivers */ + +/* end of WCH HAL & SDK Drivers */ + +/* AT32 HAL & SDK Drivers */ + +/* end of AT32 HAL & SDK Drivers */ + +/* HC32 DDL Drivers */ + +/* end of HC32 DDL Drivers */ + +/* NXP HAL & SDK Drivers */ + +/* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ + +/* FT32 HAL & SDK Drivers */ + +/* end of FT32 HAL & SDK Drivers */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ + +/* Hardware Drivers Config */ + +#define SOC_SERIES_IFX_PSOCE84 +#define KIT_PROCE84_EVK_M55 + +/* Onboard Peripheral Drivers */ + +#define BSP_USING_USB_TO_UART +/* end of Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_IPC +#define BSP_USING_UART +#define BSP_USING_UART2 +/* end of On-chip Peripheral Drivers */ + +/* Board extended module Drivers */ + +/* end of Board extended module Drivers */ +/* end of Hardware Drivers Config */ + +#endif diff --git a/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/rtconfig.py b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/rtconfig.py new file mode 100644 index 00000000..bc4522bb --- /dev/null +++ b/projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC/rtconfig.py @@ -0,0 +1,103 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m7' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armclang' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m7 -mthumb -mfpu=fpv5-d16 --specs=nano.specs -mfloat-abi=hard -ffunction-sections -fdata-sections -nostartfiles -nostartfiles' + CFLAGS = DEVICE + ' -g -Wall -pipe' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -flto -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O3 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O ihex $TARGET rtthread.hex\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armclang': + # toolchains + CC = 'armclang' + CXX = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m4 ' + CFLAGS += ' -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 ' + CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' + CFLAGS += ' -gdwarf-3 -ffunction-sections ' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' + LFLAGS += ' --list rt-thread.map ' + LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" ' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' + + EXEC_PATH += '/ARM/ARMCLANG/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O1' # armclang recommend + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/.hardware-config-server.generated-files b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/.hardware-config-server.generated-files index 10c5a97b..c9c37f51 100644 --- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/.hardware-config-server.generated-files +++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/.hardware-config-server.generated-files @@ -5,8 +5,6 @@ cycfg_clocks.c cycfg_clocks.h cycfg_connectivity_bt.h cycfg_connectivity_wifi.h -cycfg_dmas.c -cycfg_dmas.h cycfg_memory.h cycfg_notices.h cycfg_peripheral_clocks.c @@ -39,4 +37,5 @@ cymem_ilinkarm_regions_CM33_0_S.icf cymem_ilinkarm_regions_CM55_0.icf cymem_memory_locations.h cymem_memory_types.h +device_mem.json edgeproctectsymbols.json diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg.c b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg.c index f8d3ee0d..7a72d5af 100644 --- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg.c +++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg.c @@ -5,9 +5,9 @@ * Simple wrapper containing all generated files and function to initialize * all generated code. * This file was automatically generated and should not be modified. - * Configurator Backend 3.60.0 - * device-db 4.34.0.9502 - * mtb-dsl-pse8xxgp 1.1.1.824 + * Configurator Backend 3.70.0 + * device-db 4.35.0.9884 + * mtb-dsl-pse8xxgp 1.4.0.994 * ******************************************************************************* * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg.h b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg.h index afc1decf..459f7db2 100644 --- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg.h +++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg.h @@ -5,9 +5,9 @@ * Simple wrapper containing all generated files and function to initialize * all generated code. * This file was automatically generated and should not be modified. - * Configurator Backend 3.60.0 - * device-db 4.34.0.9502 - * mtb-dsl-pse8xxgp 1.1.1.824 + * Configurator Backend 3.70.0 + * device-db 4.35.0.9884 + * mtb-dsl-pse8xxgp 1.4.0.994 * ******************************************************************************* * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or @@ -42,7 +42,6 @@ #include "cycfg_peripheral_clocks.h" #include "cycfg_system.h" #include "cycfg_ppc.h" -#include "cycfg_dmas.h" #include "cycfg_peripherals.h" #include "cycfg_routing.h" #include "cycfg_pins.h" diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg.timestamp b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg.timestamp index 0c9dca0e..71100924 100644 --- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg.timestamp +++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg.timestamp @@ -4,12 +4,12 @@ * Description: * Sentinel file for determining if generated source is up to date. * This file was automatically generated and should not be modified. - * Configurator Backend 3.60.0 - * device-db 4.33.0.9315 - * mtb-dsl-pse8xxgp 1.1.1.824 + * Configurator Backend 3.70.0 + * device-db 4.35.0.9884 + * mtb-dsl-pse8xxgp 1.4.0.994 * ******************************************************************************* - * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or + * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or * an affiliate of Cypress Semiconductor Corporation. * SPDX-License-Identifier: Apache-2.0 * diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_clock_types.h b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_clock_types.h index 97ce622a..98b2953d 100644 --- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_clock_types.h +++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_clock_types.h @@ -4,16 +4,23 @@ #include "cy_sysclk.h" +/** HF Clock Configuration */ typedef struct { + /** HF clock source */ cy_en_clkhf_in_sources_t source; + /** HF clock divider */ cy_en_clkhf_dividers_t divider; } cycfg_clkhf_config_t; +/** HF Clock Supervisor Configuration */ typedef struct { + /** HF Clock Supervisor reference clock */ cy_en_clkhf_csv_ref_clk_t refClk; + /** HF Clock Supervisor accuracy */ uint32_t accuracy; + /** HF Clock Supervisor action */ cy_en_clkhf_csv_action_t action; } cycfg_clkhf_csv_config_t; diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_clocks.c b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_clocks.c index 4dae0a7c..605a3cff 100644 --- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_clocks.c +++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_clocks.c @@ -4,9 +4,9 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. - * Configurator Backend 3.60.0 - * device-db 4.34.0.9502 - * mtb-dsl-pse8xxgp 1.1.1.824 + * Configurator Backend 3.70.0 + * device-db 4.35.0.9884 + * mtb-dsl-pse8xxgp 1.4.0.994 * ******************************************************************************* * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_clocks.h b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_clocks.h index 45a46285..0450bc4f 100644 --- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_clocks.h +++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_clocks.h @@ -4,9 +4,9 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. - * Configurator Backend 3.60.0 - * device-db 4.34.0.9502 - * mtb-dsl-pse8xxgp 1.1.1.824 + * Configurator Backend 3.70.0 + * device-db 4.35.0.9884 + * mtb-dsl-pse8xxgp 1.4.0.994 * ******************************************************************************* * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_connectivity_bt.h b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_connectivity_bt.h index 94aee9aa..b8cac76d 100644 --- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_connectivity_bt.h +++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_connectivity_bt.h @@ -4,9 +4,9 @@ * Description: * Connectivity BT configuration * This file was automatically generated and should not be modified. - * Configurator Backend 3.60.0 - * device-db 4.34.0.9502 - * mtb-dsl-pse8xxgp 1.1.1.824 + * Configurator Backend 3.70.0 + * device-db 4.35.0.9884 + * mtb-dsl-pse8xxgp 1.4.0.994 * ******************************************************************************* * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_connectivity_wifi.h b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_connectivity_wifi.h index 9cbe1d82..57ec25c9 100644 --- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_connectivity_wifi.h +++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_connectivity_wifi.h @@ -4,9 +4,9 @@ * Description: * Connectivity Wi-Fi configuration * This file was automatically generated and should not be modified. - * Configurator Backend 3.60.0 - * device-db 4.34.0.9502 - * mtb-dsl-pse8xxgp 1.1.1.824 + * Configurator Backend 3.70.0 + * device-db 4.35.0.9884 + * mtb-dsl-pse8xxgp 1.4.0.994 * ******************************************************************************* * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_dmas.c b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_dmas.c deleted file mode 100644 index 7c9c263a..00000000 --- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_dmas.c +++ /dev/null @@ -1,86 +0,0 @@ -/******************************************************************************* - * File Name: cycfg_dmas.c - * - * Description: - * DMA configuration - * This file was automatically generated and should not be modified. - * Configurator Backend 3.60.0 - * device-db 4.34.0.9502 - * mtb-dsl-pse8xxgp 1.1.1.824 - * - ******************************************************************************* - * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or - * an affiliate of Cypress Semiconductor Corporation. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - ******************************************************************************/ - -#include "cycfg_dmas.h" - -const cy_stc_dma_descriptor_config_t CYBSP_DMA_TX_SPI_CONTROLLER_Descriptor_0_config = -{ - .retrigger = CY_DMA_RETRIG_IM, - .interruptType = CY_DMA_DESCR, - .triggerOutType = CY_DMA_1ELEMENT, - .channelState = CY_DMA_CHANNEL_DISABLED, - .triggerInType = CY_DMA_1ELEMENT, - .dataSize = CY_DMA_BYTE, - .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .dstTransferSize = CY_DMA_TRANSFER_SIZE_WORD, - .descriptorType = CY_DMA_1D_TRANSFER, - .srcAddress = NULL, - .dstAddress = NULL, - .srcXincrement = 1, - .dstXincrement = 0, - .xCount = 12, - .srcYincrement = 0, - .dstYincrement = 0, - .yCount = 1, - .nextDescriptor = &CYBSP_DMA_TX_SPI_CONTROLLER_Descriptor_0, -}; -CY_SECTION(".cy_socmem_data") CY_ALIGN(8) cy_stc_dma_descriptor_t CYBSP_DMA_TX_SPI_CONTROLLER_Descriptor_0 = -{ - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, - .nextPtr = 0UL, -}; -const cy_stc_dma_channel_config_t CYBSP_DMA_TX_SPI_CONTROLLER_channelConfig = -{ - .descriptor = &CYBSP_DMA_TX_SPI_CONTROLLER_Descriptor_0, - .preemptable = false, - .priority = 3, - .enable = false, - .bufferable = false, -}; -const cy_stc_dma_crc_config_t CYBSP_DMA_TX_SPI_CONTROLLER_crcConfig = -{ - .dataReverse = false, - .dataXor = 0, - .reminderReverse = false, - .reminderXor = 0, - .polynomial = 79764919, -}; - -#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_DMA) -const mtb_hal_dma_configurator_t CYBSP_DMA_TX_SPI_CONTROLLER_hal_config = -{ - .dma_type = MTB_HAL_DMA_DW, - .channel = CYBSP_DMA_TX_SPI_CONTROLLER_CHANNEL, - .dw_base = CYBSP_DMA_TX_SPI_CONTROLLER_HW, - .dw_descriptor = &CYBSP_DMA_TX_SPI_CONTROLLER_Descriptor_0, -}; -#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_DMA) */ diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_dmas.h b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_dmas.h deleted file mode 100644 index 38d2e902..00000000 --- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_dmas.h +++ /dev/null @@ -1,61 +0,0 @@ -/******************************************************************************* - * File Name: cycfg_dmas.h - * - * Description: - * DMA configuration - * This file was automatically generated and should not be modified. - * Configurator Backend 3.60.0 - * device-db 4.34.0.9502 - * mtb-dsl-pse8xxgp 1.1.1.824 - * - ******************************************************************************* - * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or - * an affiliate of Cypress Semiconductor Corporation. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - ******************************************************************************/ - -#if !defined(CYCFG_DMAS_H) -#define CYCFG_DMAS_H - -#include "cycfg_notices.h" -#include "cy_dma.h" - -#if defined (COMPONENT_MTB_HAL) -#include "mtb_hal.h" -#endif /* defined (COMPONENT_MTB_HAL) */ - -#if defined(__cplusplus) -extern "C" { -#endif /* defined(__cplusplus) */ - -#define CYBSP_DMA_TX_SPI_CONTROLLER_ENABLED 1U -#define CYBSP_DMA_TX_SPI_CONTROLLER_HW DW0 -#define CYBSP_DMA_TX_SPI_CONTROLLER_CHANNEL 1U -#define CYBSP_DMA_TX_SPI_CONTROLLER_IRQ cpuss_interrupts_dw0_1_IRQn - -extern const cy_stc_dma_descriptor_config_t CYBSP_DMA_TX_SPI_CONTROLLER_Descriptor_0_config; -extern CY_SECTION(".cy_socmem_data") CY_ALIGN(8) cy_stc_dma_descriptor_t CYBSP_DMA_TX_SPI_CONTROLLER_Descriptor_0; -extern const cy_stc_dma_channel_config_t CYBSP_DMA_TX_SPI_CONTROLLER_channelConfig; -extern const cy_stc_dma_crc_config_t CYBSP_DMA_TX_SPI_CONTROLLER_crcConfig; - -#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_DMA) -extern const mtb_hal_dma_configurator_t CYBSP_DMA_TX_SPI_CONTROLLER_hal_config; -#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_DMA) */ - -#if defined(__cplusplus) -} -#endif /* defined(__cplusplus) */ - -#endif /* CYCFG_DMAS_H */ diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_memory.h b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_memory.h index e8ce87ef..84876a57 100644 --- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_memory.h +++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_memory.h @@ -4,9 +4,9 @@ * Description: * Memory configuration * This file was automatically generated and should not be modified. - * Configurator Backend 3.60.0 - * device-db 4.34.0.9502 - * mtb-dsl-pse8xxgp 1.1.1.824 + * Configurator Backend 3.70.0 + * device-db 4.35.0.9884 + * mtb-dsl-pse8xxgp 1.4.0.994 * ******************************************************************************* * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_notices.h b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_notices.h index 4412f1ae..101f6189 100644 --- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_notices.h +++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_notices.h @@ -5,9 +5,9 @@ * Contains warnings and errors that occurred while generating code for the * design. * This file was automatically generated and should not be modified. - * Configurator Backend 3.60.0 - * device-db 4.34.0.9502 - * mtb-dsl-pse8xxgp 1.1.1.824 + * Configurator Backend 3.70.0 + * device-db 4.35.0.9884 + * mtb-dsl-pse8xxgp 1.4.0.994 * ******************************************************************************* * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripheral_clocks.c b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripheral_clocks.c index 9837c660..9c29db52 100644 --- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripheral_clocks.c +++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripheral_clocks.c @@ -4,9 +4,9 @@ * Description: * Peripheral clock divider configuration * This file was automatically generated and should not be modified. - * Configurator Backend 3.60.0 - * device-db 4.34.0.9502 - * mtb-dsl-pse8xxgp 1.1.1.824 + * Configurator Backend 3.70.0 + * device-db 4.35.0.9884 + * mtb-dsl-pse8xxgp 1.4.0.994 * ******************************************************************************* * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or @@ -46,7 +46,7 @@ void init_cycfg_peripheral_clocks(void) Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)CYBSP_PWM_DT_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 3U, 249U); Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)CYBSP_PWM_DT_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 3U); Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_4_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 4U); - Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_4_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 4U, 0U); + Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_4_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 4U, 4U); Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_8_4_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 4U); Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)CYBSP_I2C_CONTROLLER_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_BIT, 0U); Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)CYBSP_I2C_CONTROLLER_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_BIT, 0U, 9U); diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripheral_clocks.h b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripheral_clocks.h index f5d18f3f..f239d195 100644 --- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripheral_clocks.h +++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripheral_clocks.h @@ -4,9 +4,9 @@ * Description: * Peripheral clock divider configuration * This file was automatically generated and should not be modified. - * Configurator Backend 3.60.0 - * device-db 4.34.0.9502 - * mtb-dsl-pse8xxgp 1.1.1.824 + * Configurator Backend 3.70.0 + * device-db 4.35.0.9884 + * mtb-dsl-pse8xxgp 1.4.0.994 * ******************************************************************************* * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripherals.c b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripherals.c index b5e74d89..697d6baf 100644 --- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripherals.c +++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripherals.c @@ -1,1607 +1,1785 @@ -/******************************************************************************* - * File Name: cycfg_peripherals.c - * - * Description: - * Analog configuration - * This file was automatically generated and should not be modified. - * Configurator Backend 3.60.0 - * device-db 4.34.0.9502 - * mtb-dsl-pse8xxgp 1.1.1.824 - * - ******************************************************************************* - * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or - * an affiliate of Cypress Semiconductor Corporation. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - ******************************************************************************/ - -#include "cycfg_peripherals.h" - -#define CYBSP_GENERAL_PURPOSE_TIMER_INPUT_DISABLED 0x7U -#define emUSB_OS_Timer_INPUT_DISABLED 0x7U -#define CYBSP_PWM_LED_CTRL_INPUT_DISABLED 0x7U -#define CYBSP_DEAD_TIME_PWM_INPUT_DISABLED 0x7U -#define CYBSP_SMARTIO_PWM_INPUT_DISABLED 0x7U -#define tcpwm_0_group_1_cnt_9_INPUT_DISABLED 0x7U - -cy_stc_autanalog_cfg_t autonomous_analog_cfg = -{ - .prb = NULL, - .ac = &CYBSP_AUTONOMOUS_CONTROLLER_cfg, - .ctb = - { - NULL, - NULL, - }, - .ptcomp = - { - NULL, - }, - .dac = - { - NULL, - NULL, - }, - .sar = - { - &CYBSP_SAR_ADC_cfg, - }, -}; -cy_stc_autanalog_stt_t autonomous_analog_stt[] = -{ - { - .ac = &CYBSP_AUTONOMOUS_CONTROLLER_stt[0U], - .prb = NULL, - .ctb = - { - NULL, - NULL, - }, - .ptcomp = - { - NULL, - }, - .dac = - { - NULL, - NULL, - }, - .sar = - { - &CYBSP_SAR_ADC_stt[0U], - }, - }, - { - .ac = &CYBSP_AUTONOMOUS_CONTROLLER_stt[1U], - .prb = NULL, - .ctb = - { - NULL, - NULL, - }, - .ptcomp = - { - NULL, - }, - .dac = - { - NULL, - NULL, - }, - .sar = - { - &CYBSP_SAR_ADC_stt[1U], - }, - }, - { - .ac = &CYBSP_AUTONOMOUS_CONTROLLER_stt[2U], - .prb = NULL, - .ctb = - { - NULL, - NULL, - }, - .ptcomp = - { - NULL, - }, - .dac = - { - NULL, - NULL, - }, - .sar = - { - &CYBSP_SAR_ADC_stt[2U], - }, - }, -}; -cy_stc_autanalog_t autonomous_analog_init = -{ - .configuration = &autonomous_analog_cfg, - .numSttEntries = sizeof(autonomous_analog_stt)/sizeof(autonomous_analog_stt[0U]), - .stateTransitionTable = &autonomous_analog_stt[0U], -}; -cy_en_autanalog_ac_out_trigger_mask_t CYBSP_AUTONOMOUS_CONTROLLER_out_trig_mask[] = -{ - CY_AUTANALOG_AC_OUT_TRIG_MASK_EMPTY, - CY_AUTANALOG_AC_OUT_TRIG_MASK_EMPTY, - CY_AUTANALOG_AC_OUT_TRIG_MASK_EMPTY, - CY_AUTANALOG_AC_OUT_TRIG_MASK_EMPTY, - CY_AUTANALOG_AC_OUT_TRIG_MASK_EMPTY, - CY_AUTANALOG_AC_OUT_TRIG_MASK_EMPTY, - CY_AUTANALOG_AC_OUT_TRIG_MASK_EMPTY, - CY_AUTANALOG_AC_OUT_TRIG_MASK_EMPTY, -}; -cy_stc_autanalog_ac_t CYBSP_AUTONOMOUS_CONTROLLER_cfg = -{ - .gpioOutEn = - CY_AUTANALOG_STT_AC_GPIO_OUT_DISABLED, - .mask = - { - &CYBSP_AUTONOMOUS_CONTROLLER_out_trig_mask[0U], - &CYBSP_AUTONOMOUS_CONTROLLER_out_trig_mask[1U], - &CYBSP_AUTONOMOUS_CONTROLLER_out_trig_mask[2U], - &CYBSP_AUTONOMOUS_CONTROLLER_out_trig_mask[3U], - &CYBSP_AUTONOMOUS_CONTROLLER_out_trig_mask[4U], - &CYBSP_AUTONOMOUS_CONTROLLER_out_trig_mask[5U], - &CYBSP_AUTONOMOUS_CONTROLLER_out_trig_mask[6U], - &CYBSP_AUTONOMOUS_CONTROLLER_out_trig_mask[7U], - }, - .timer = - { - .enable = false, - .clkSrc = CY_AUTANALOG_TIMER_CLK_LP, - .period = 0U, - }, -}; -cy_stc_autanalog_stt_ac_t CYBSP_AUTONOMOUS_CONTROLLER_stt[] = -{ - { - .unlock = true, - .lpMode = false, - .condition = CY_AUTANALOG_STT_AC_CONDITION_BLOCK_READY, - .action = CY_AUTANALOG_STT_AC_ACTION_WAIT_FOR, - .branchState = 1U, - .trigInt = false, - .count = 0U, - .unlockGpioOut = false, - .gpioOut = CY_AUTANALOG_STT_AC_GPIO_OUT_DISABLED, - }, - { - .unlock = false, - .lpMode = false, - .condition = CY_AUTANALOG_STT_AC_CONDITION_SAR_DONE, - .action = CY_AUTANALOG_STT_AC_ACTION_WAIT_FOR, - .branchState = 0U, - .trigInt = false, - .count = 0U, - .unlockGpioOut = false, - .gpioOut = CY_AUTANALOG_STT_AC_GPIO_OUT_DISABLED, - }, - { - .unlock = false, - .lpMode = false, - .condition = CY_AUTANALOG_STT_AC_CONDITION_FALSE, - .action = CY_AUTANALOG_STT_AC_ACTION_STOP, - .branchState = 0U, - .trigInt = false, - .count = 0U, - .unlockGpioOut = false, - .gpioOut = CY_AUTANALOG_STT_AC_GPIO_OUT_DISABLED, - }, -}; -cy_stc_autanalog_sar_hs_chan_t CYBSP_SAR_ADC_gpio_ch_cfg[] = -{ - { - .posPin = CY_AUTANALOG_SAR_PIN_GPIO5, - .hsDiffEn = false, - .sign = false, - .posCoeff = CY_AUTANALOG_SAR_CH_COEFF_DISABLED, - .negPin = CY_AUTANALOG_SAR_PIN_GPIO0, - .accShift = false, - .negCoeff = CY_AUTANALOG_SAR_CH_COEFF_DISABLED, - .hsLimit = CY_AUTANALOG_SAR_LIMIT_STATUS_DISABLED, - .fifoSel = CY_AUTANALOG_FIFO_DISABLED, - }, -}; -cy_stc_autanalog_sar_sta_hs_t CYBSP_SAR_ADC_sta_hs_cfg = -{ - .hsVref = CY_AUTANALOG_SAR_VREF_VDDA, - .hsSampleTime = - { - 31U, - 31U, - 31U, - 31U, - }, - .hsGpioChan = - { - &CYBSP_SAR_ADC_gpio_ch_cfg[0U], - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - }, - .hsGpioResultMask = - CY_AUTANALOG_SAR_CHAN_MASK_GPIO0, -}; -cy_stc_autanalog_sar_sta_t CYBSP_SAR_ADC_sta_cfg = -{ - .lpStaCfg = NULL, - .hsStaCfg = &CYBSP_SAR_ADC_sta_hs_cfg, - .posBufPwr = CY_AUTANALOG_SAR_BUF_PWR_OFF, - .negBufPwr = CY_AUTANALOG_SAR_BUF_PWR_OFF, - .accMode = CY_AUTANALOG_SAR_ACC_DISABLED, - .startupCal = CY_AUTANALOG_SAR_CAL_DISABLED, - .chanID = false, - .shiftMode = false, - .intMuxChan = - { - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - }, - .limitCond = - { - NULL, - NULL, - NULL, - NULL, - }, - .muxResultMask = - CY_AUTANALOG_SAR_CHAN_MASK_MUX_DISABLED, - .firResultMask = - CY_AUTANALOG_SAR_MASK_FIR_DISABLED, -}; -cy_stc_autanalog_sar_seq_tab_hs_t CYBSP_SAR_ADC_seq_hs_cfg[] = -{ - { - .chanEn = CY_AUTANALOG_SAR_CHAN_MASK_GPIO0, - .muxMode = CY_AUTANALOG_SAR_CHAN_CFG_MUX_DISABLED, - .mux0Sel = CY_AUTANALOG_SAR_CHAN_CFG_MUX0, - .mux1Sel = CY_AUTANALOG_SAR_CHAN_CFG_MUX0, - .sampleTimeEn = true, - .sampleTime = CY_AUTANALOG_SAR_SAMPLE_TIME0, - .accEn = false, - .accCount = CY_AUTANALOG_SAR_ACC_CNT2, - .calReq = CY_AUTANALOG_SAR_CAL_DISABLED, - .nextAction = CY_AUTANALOG_SAR_NEXT_ACTION_GO_TO_ENTRY_ADDR, - }, -}; -cy_stc_autanalog_sar_t CYBSP_SAR_ADC_cfg = -{ - .sarStaCfg = &CYBSP_SAR_ADC_sta_cfg, - .hsSeqTabNum = sizeof(CYBSP_SAR_ADC_seq_hs_cfg)/sizeof(CYBSP_SAR_ADC_seq_hs_cfg[0U]), - .hsSeqTabArr = &CYBSP_SAR_ADC_seq_hs_cfg[0U], - .lpSeqTabNum = 0U, - .lpSeqTabArr = NULL, - .firNum = 0U, - .firCfg = NULL, - .fifoCfg = NULL, -}; -cy_stc_autanalog_stt_sar_t CYBSP_SAR_ADC_stt[] = -{ - { - .unlock = true, - .enable = true, - .trigger = false, - .entryState = 0U, - }, - { - .unlock = true, - .enable = true, - .trigger = true, - .entryState = 0U, - }, - { - .unlock = true, - .enable = true, - .trigger = false, - .entryState = 0U, - }, -}; - -#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_ADC) -mtb_hal_adc_configurator_t CYBSP_SAR_ADC_hal_config = -{ - .config = &CYBSP_SAR_ADC_cfg, - .num_channels = sizeof(CYBSP_SAR_ADC_seq_hs_cfg)/sizeof(CYBSP_SAR_ADC_seq_hs_cfg[0U]), - .clock = NULL, - .adc_index = 0U, -}; -#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_ADC) */ - -cy_stc_gfx_layer_config_t GFXSS_graphics_layer = -{ - .layer_type = GFX_LAYER_GRAPHICS, - .buffer_address = (gctADDRESS *)CY_SOCMEM_RAM_BASE, - .uv_buffer_address = (gctADDRESS *)CY_SOCMEM_RAM_BASE, - .input_format_type = vivRGB565, - .tiling_type = vivLINEAR, - .pos_x = 0, - .pos_y = 0, - .width = 512, - .height = 800, - .zorder = 0, - .layer_enable = true, - .visibility = true, -}; -cy_stc_gfx_layer_config_t GFXSS_overlay0_layer = -{ - .layer_type = GFX_LAYER_OVERLAY0, - .buffer_address = (gctADDRESS *)CY_SOCMEM_RAM_BASE, - .uv_buffer_address = (gctADDRESS *)CY_SOCMEM_RAM_BASE, - .input_format_type = vivRGB565, - .tiling_type = vivLINEAR, - .pos_x = 0, - .pos_y = 0, - .width = 1, - .height = 1, - .zorder = 0, - .layer_enable = false, - .visibility = false, -}; -cy_stc_gfx_layer_config_t GFXSS_overlay1_layer = -{ - .layer_type = GFX_LAYER_OVERLAY1, - .buffer_address = (gctADDRESS *)CY_SOCMEM_RAM_BASE, - .uv_buffer_address = (gctADDRESS *)CY_SOCMEM_RAM_BASE, - .input_format_type = vivRGB565, - .tiling_type = vivLINEAR, - .pos_x = 0, - .pos_y = 0, - .width = 1, - .height = 1, - .zorder = 0, - .layer_enable = false, - .visibility = false, -}; -cy_stc_gfx_dc_config_t GFXSS_dc_config = -{ - .gfx_layer_config = &GFXSS_graphics_layer, - .ovl0_layer_config = &GFXSS_overlay0_layer, - .ovl1_layer_config = &GFXSS_overlay1_layer, - .display_type = GFX_DISP_TYPE_DSI_DPI, - .display_format = vivD16CFG1, - .display_size = vivDISPLAY_CUSTOMIZED, - .display_width = 512, - .display_height = 800, -}; -cy_stc_gfx_gpu_cfg_t GFXSS_gpu_config = -{ - .enable = true, -}; -cy_stc_mipidsi_display_params_t GFXSS_mipidsi_display_params = -{ - .pixel_clock = 33448, - .hdisplay = 512, - .hsync_width = 2, - .hfp = 36, - .hbp = 40, - .vdisplay = 800, - .vsync_width = 2, - .vfp = 180, - .vbp = 10, - .polarity_flags = 0, -}; -cy_stc_mipidsi_config_t GFXSS_mipi_dsi_config = -{ - .virtual_ch = 0, - .num_of_lanes = 2, - .per_lane_mbps = 1000, - .dpi_fmt = CY_MIPIDSI_FMT_RGB565, - .dsi_mode = DSI_VIDEO_MODE, - .max_phy_clk = 2500000000, - .mode_flags = VID_MODE_TYPE_NON_BURST_SYNC_PULSES | ENABLE_LOW_POWER_CMD | ENABLE_LOW_POWER, - .display_params = &GFXSS_mipidsi_display_params, -}; -cy_stc_gfx_config_t GFXSS_config = -{ - .dc_cfg = &GFXSS_dc_config, - .gpu_cfg = &GFXSS_gpu_config, - .mipi_dsi_cfg = &GFXSS_mipi_dsi_config, - .display_update_type = GFX_DOUBLE_BUFFER, - .clockHz = 399999999U, -}; -const cy_stc_i3c_config_t CYBSP_I3C_CONTROLLER_config = -{ - .i3cMode = CY_I3C_CONTROLLER, - .i3cBusMode = CY_I3C_BUS_PURE, - .useDma = false, - .manualDataRate = false, - .i3cClockHz = 12500000U, - .i3cSclRate = 12500000U, - .openDrainSclRate = 4000000U, - .txEmptyBufThld = CY_I3C_1_WORD_DEPTH, - .rxBufThld = CY_I3C_1_WORD_DEPTH, - .txBufStartThld = CY_I3C_1_WORD_DEPTH, - .rxBufStartThld = CY_I3C_1_WORD_DEPTH, - .ibaInclude = false, - .hotJoinCtrl = false, - .dynamicAddr = 8U, - .cmdQueueEmptyThld = 1U, - .respQueueThld = 0U, - .ibiQueueThld = 0U, - .ibiDataThld = 15U, - .extLowCnt1 = 11U, - .extLowCnt2 = 16U, - .extLowCnt3 = 27U, - .extLowCnt4 = 58U, - .extTerminationLowCnt = 0U, - .sdaHoldTime = 1U, - .busFreeTime = 32U, - .openDrainLowCnt = 0U, - .openDrainHighCnt = 0U, - .pushPullLowCnt = 0U, - .pushPullHighCnt = 0U, - .i2cFMLowCnt = 0U, - .i2cFMHighCnt = 0U, - .i2cFMPlusLowCnt = 0U, - .i2cFMPlusHighCnt = 0U, - .adaptiveI2CI3C = false, - .staticAddress = 0U, - .pid = 0U, - .dcr = 0U, - .speedLimit = false, - .hdrCapable = false, - .deviceRoleCap = CY_I3C_SECONDARY_CONTROLLER, - .hotjoinEnable = false, - .busAvailTime = 0U, - .busIdleTime = 0U, -}; -const cy_stc_pdm_pcm_config_v2_t CYBSP_PDM_config = -{ - .clkDiv = 7, - .clksel = CY_PDM_PCM_SEL_SRSS_CLOCK, - .halverate = CY_PDM_PCM_RATE_FULL, - .route = 4, - .fir0_coeff_user_value = false, - .fir1_coeff_user_value = false, -}; -const cy_stc_pdm_pcm_channel_config_t channel_2_config = -{ - .sampledelay = 1, - .wordSize = CY_PDM_PCM_WSIZE_16_BIT, - .signExtension = true, - .rxFifoTriggerLevel = 31, - .fir0_enable = false, - .cic_decim_code = CY_PDM_PCM_CHAN_CIC_DECIM_32, - .fir0_decim_code = CY_PDM_PCM_CHAN_FIR0_DECIM_1, - .fir0_scale = 0, - .fir1_decim_code = CY_PDM_PCM_CHAN_FIR1_DECIM_3, - .fir1_scale = 10, - .dc_block_disable = false, - .dc_block_code = CY_PDM_PCM_CHAN_DCBLOCK_CODE_16, -}; -const cy_stc_pdm_pcm_channel_config_t channel_3_config = -{ - .sampledelay = 5, - .wordSize = CY_PDM_PCM_WSIZE_16_BIT, - .signExtension = true, - .rxFifoTriggerLevel = 31, - .fir0_enable = false, - .cic_decim_code = CY_PDM_PCM_CHAN_CIC_DECIM_32, - .fir0_decim_code = CY_PDM_PCM_CHAN_FIR0_DECIM_1, - .fir0_scale = 0, - .fir1_decim_code = CY_PDM_PCM_CHAN_FIR1_DECIM_3, - .fir1_scale = 10, - .dc_block_disable = false, - .dc_block_code = CY_PDM_PCM_CHAN_DCBLOCK_CODE_16, -}; -const cy_stc_scb_i2c_config_t CYBSP_I2C_CONTROLLER_config = -{ - .i2cMode = CY_SCB_I2C_MASTER, - .useRxFifo = true, - .useTxFifo = true, - .slaveAddress = 0U, - .slaveAddressMask = 0U, - .acceptAddrInFifo = false, - .ackGeneralAddr = false, - .enableWakeFromSleep = false, - .enableDigitalFilter = false, - .lowPhaseDutyCycle = 16, - .highPhaseDutyCycle = 9, -}; - -#if defined (COMPONENT_MTB_HAL) -const mtb_hal_peri_div_t CYBSP_I2C_CONTROLLER_clock_ref = -{ - .clk_dst = (en_clk_dst_t)CYBSP_I2C_CONTROLLER_CLK_DIV_GRP_NUM, - .div_type = CYBSP_I2C_CONTROLLER_CLK_DIV_HW, - .div_num = CYBSP_I2C_CONTROLLER_CLK_DIV_NUM, -}; -const mtb_hal_clock_t CYBSP_I2C_CONTROLLER_hal_clock = -{ - .clock_ref = &CYBSP_I2C_CONTROLLER_clock_ref, - .interface = &mtb_hal_clock_peri_interface, -}; -#endif /* defined (COMPONENT_MTB_HAL) */ - -#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_I2C) -const mtb_hal_i2c_configurator_t CYBSP_I2C_CONTROLLER_hal_config = -{ - .base = CYBSP_I2C_CONTROLLER_HW, - .config = &CYBSP_I2C_CONTROLLER_config, - .clock = &CYBSP_I2C_CONTROLLER_hal_clock, -}; -#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_I2C) */ - -const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config = -{ - .uartMode = CY_SCB_UART_STANDARD, - .enableMultiProcessorMode = false, - .smartCardRetryOnNack = false, - .irdaInvertRx = false, - .irdaEnableLowPowerReceiver = false, - .oversample = 10, - .enableMsbFirst = false, - .dataWidth = 8UL, - .parity = CY_SCB_UART_PARITY_NONE, - .stopBits = CY_SCB_UART_STOP_BITS_1, - .enableInputFilter = false, - .breakWidth = 11UL, - .dropOnFrameError = false, - .dropOnParityError = false, - .breaklevel = false, - .receiverAddress = 0x0UL, - .receiverAddressMask = 0x0UL, - .acceptAddrInFifo = false, - .enableCts = false, - .ctsPolarity = CY_SCB_UART_ACTIVE_LOW, - .rtsRxFifoLevel = 0UL, - .rtsPolarity = CY_SCB_UART_ACTIVE_LOW, - .rxFifoTriggerLevel = 63UL, - .rxFifoIntEnableMask = 0UL, - .txFifoTriggerLevel = 63UL, - .txFifoIntEnableMask = 0UL, -}; - -#if defined (COMPONENT_MTB_HAL) -const mtb_hal_peri_div_t CYBSP_DEBUG_UART_clock_ref = -{ - .clk_dst = (en_clk_dst_t)CYBSP_DEBUG_UART_CLK_DIV_GRP_NUM, - .div_type = CYBSP_DEBUG_UART_CLK_DIV_HW, - .div_num = CYBSP_DEBUG_UART_CLK_DIV_NUM, -}; -const mtb_hal_clock_t CYBSP_DEBUG_UART_hal_clock = -{ - .clock_ref = &CYBSP_DEBUG_UART_clock_ref, - .interface = &mtb_hal_clock_peri_interface, -}; -#endif /* defined (COMPONENT_MTB_HAL) */ - -#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_UART) -const mtb_hal_uart_configurator_t CYBSP_DEBUG_UART_hal_config = -{ - .base = CYBSP_DEBUG_UART_HW, - .clock = &CYBSP_DEBUG_UART_hal_clock, - .tx_pin = 7, -#if defined (COMPONENT_MW_ASYNC_TRANSFER) - .rts_pin = 0xFF, -#endif /* defined (COMPONENT_MW_ASYNC_TRANSFER) */ - .tx_port = 6, -#if defined (COMPONENT_MW_ASYNC_TRANSFER) - .rts_port = 0xFF, - .rts_enable = 0UL, -#endif /* defined (COMPONENT_MW_ASYNC_TRANSFER) */ -}; -#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_UART) */ - -const cy_stc_scb_uart_config_t CYBSP_BT_UART_config = -{ - .uartMode = CY_SCB_UART_STANDARD, - .enableMultiProcessorMode = false, - .smartCardRetryOnNack = false, - .irdaInvertRx = false, - .irdaEnableLowPowerReceiver = false, - .oversample = 8, - .enableMsbFirst = false, - .dataWidth = 8UL, - .parity = CY_SCB_UART_PARITY_NONE, - .stopBits = CY_SCB_UART_STOP_BITS_1, - .enableInputFilter = false, - .breakWidth = 11UL, - .dropOnFrameError = false, - .dropOnParityError = false, - .breaklevel = false, - .receiverAddress = 0x0UL, - .receiverAddressMask = 0x0UL, - .acceptAddrInFifo = false, - .enableCts = true, - .ctsPolarity = CY_SCB_UART_ACTIVE_LOW, - .rtsRxFifoLevel = 63, - .rtsPolarity = CY_SCB_UART_ACTIVE_LOW, - .rxFifoTriggerLevel = 63UL, - .rxFifoIntEnableMask = 0UL, - .txFifoTriggerLevel = 63UL, - .txFifoIntEnableMask = 0UL, -}; - -#if defined (COMPONENT_MTB_HAL) -const mtb_hal_peri_div_t CYBSP_BT_UART_clock_ref = -{ - .clk_dst = (en_clk_dst_t)CYBSP_BT_UART_CLK_DIV_GRP_NUM, - .div_type = CYBSP_BT_UART_CLK_DIV_HW, - .div_num = CYBSP_BT_UART_CLK_DIV_NUM, -}; -const mtb_hal_clock_t CYBSP_BT_UART_hal_clock = -{ - .clock_ref = &CYBSP_BT_UART_clock_ref, - .interface = &mtb_hal_clock_peri_interface, -}; -#endif /* defined (COMPONENT_MTB_HAL) */ - -#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_UART) -const mtb_hal_uart_configurator_t CYBSP_BT_UART_hal_config = -{ - .base = CYBSP_BT_UART_HW, - .clock = &CYBSP_BT_UART_hal_clock, - .tx_pin = 1, -#if defined (COMPONENT_MW_ASYNC_TRANSFER) - .rts_pin = 3, -#endif /* defined (COMPONENT_MW_ASYNC_TRANSFER) */ - .tx_port = 10, -#if defined (COMPONENT_MW_ASYNC_TRANSFER) - .rts_port = 10, - .rts_enable = 1UL, -#endif /* defined (COMPONENT_MW_ASYNC_TRANSFER) */ -}; -#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_UART) */ - -const cy_stc_scb_uart_config_t CYBSP_UART5_config = -{ - .uartMode = CY_SCB_UART_STANDARD, - .enableMultiProcessorMode = false, - .smartCardRetryOnNack = false, - .irdaInvertRx = false, - .irdaEnableLowPowerReceiver = false, - .oversample = 10, - .enableMsbFirst = false, - .dataWidth = 8UL, - .parity = CY_SCB_UART_PARITY_NONE, - .stopBits = CY_SCB_UART_STOP_BITS_1, - .enableInputFilter = false, - .breakWidth = 11UL, - .dropOnFrameError = false, - .dropOnParityError = false, - .breaklevel = false, - .receiverAddress = 0x0UL, - .receiverAddressMask = 0x0UL, - .acceptAddrInFifo = false, - .enableCts = false, - .ctsPolarity = CY_SCB_UART_ACTIVE_LOW, - .rtsRxFifoLevel = 0UL, - .rtsPolarity = CY_SCB_UART_ACTIVE_LOW, - .rxFifoTriggerLevel = 63UL, - .rxFifoIntEnableMask = 0UL, - .txFifoTriggerLevel = 63UL, - .txFifoIntEnableMask = 0UL, -}; - -#if defined (COMPONENT_MTB_HAL) -const mtb_hal_peri_div_t CYBSP_UART5_clock_ref = -{ - .clk_dst = (en_clk_dst_t)CYBSP_EZ_I2C_TARGET_CLK_DIV_GRP_NUM, - .div_type = CYBSP_EZ_I2C_TARGET_CLK_DIV_HW, - .div_num = CYBSP_EZ_I2C_TARGET_CLK_DIV_NUM, -}; -const mtb_hal_clock_t CYBSP_UART5_hal_clock = -{ - .clock_ref = &CYBSP_UART5_clock_ref, - .interface = &mtb_hal_clock_peri_interface, -}; -#endif /* defined (COMPONENT_MTB_HAL) */ - -#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_UART) -const mtb_hal_uart_configurator_t CYBSP_UART5_hal_config = -{ - .base = CYBSP_UART5_HW, - .clock = &CYBSP_UART5_hal_clock, - .tx_pin = 1, -#if defined (COMPONENT_MW_ASYNC_TRANSFER) - .rts_pin = 0xFF, -#endif /* defined (COMPONENT_MW_ASYNC_TRANSFER) */ - .tx_port = 17, -#if defined (COMPONENT_MW_ASYNC_TRANSFER) - .rts_port = 0xFF, - .rts_enable = 0UL, -#endif /* defined (COMPONENT_MW_ASYNC_TRANSFER) */ -}; -#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_UART) */ - -const cy_stc_scb_spi_config_t CYBSP_SPI_CONTROLLER_config = -{ - .spiMode = CY_SCB_SPI_MASTER, - .subMode = CY_SCB_SPI_MOTOROLA, - .sclkMode = CY_SCB_SPI_CPHA0_CPOL0, - .parity = CY_SCB_SPI_PARITY_NONE, - .dropOnParityError = false, - .oversample = 10, - .rxDataWidth = 8UL, - .txDataWidth = 8UL, - .enableMsbFirst = true, - .enableInputFilter = false, - .enableFreeRunSclk = false, - .enableMisoLateSample = true, - .enableTransferSeparation = false, - .ssPolarity = ((CY_SCB_SPI_ACTIVE_LOW << CY_SCB_SPI_SLAVE_SELECT0) | \ - (CY_SCB_SPI_ACTIVE_LOW << CY_SCB_SPI_SLAVE_SELECT1) | \ - (CY_SCB_SPI_ACTIVE_LOW << CY_SCB_SPI_SLAVE_SELECT2) | \ - (CY_SCB_SPI_ACTIVE_LOW << CY_SCB_SPI_SLAVE_SELECT3)), - .ssSetupDelay = false, - .ssHoldDelay = false, - .ssInterFrameDelay = false, - .enableWakeFromSleep = false, - .rxFifoTriggerLevel = 63UL, - .rxFifoIntEnableMask = 0UL, - .txFifoTriggerLevel = 63UL, - .txFifoIntEnableMask = 0UL, - .masterSlaveIntEnableMask = 0UL, -}; - -#if defined (COMPONENT_MTB_HAL) -const mtb_hal_peri_div_t CYBSP_SPI_CONTROLLER_clock_ref = -{ - .clk_dst = (en_clk_dst_t)PCLK_SCB10_CLOCK_SCB_EN, - .div_type = CY_SYSCLK_DIV_8_BIT, - .div_num = 1, -}; -const mtb_hal_clock_t CYBSP_SPI_CONTROLLER_hal_clock = -{ - .clock_ref = &CYBSP_SPI_CONTROLLER_clock_ref, - .interface = &mtb_hal_clock_peri_interface, -}; -#endif /* defined (COMPONENT_MTB_HAL) */ - -#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SPI) -const mtb_hal_spi_configurator_t CYBSP_SPI_CONTROLLER_hal_config = -{ - .base = CYBSP_SPI_CONTROLLER_HW, - .clock = &CYBSP_SPI_CONTROLLER_hal_clock, - .config = &CYBSP_SPI_CONTROLLER_config, -}; -#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SPI) */ - -cy_en_sd_host_card_capacity_t CYBSP_SDHC_0_cardCapacity = CY_SD_HOST_SDSC; -cy_en_sd_host_card_type_t CYBSP_SDHC_0_cardType = CY_SD_HOST_NOT_EMMC; -uint32_t CYBSP_SDHC_0_rca = 0u; -const cy_stc_sd_host_init_config_t CYBSP_SDHC_0_config = -{ - .emmc = false, - .dmaType = CY_SD_HOST_DMA_ADMA2, - .enableLedControl = false, -}; -cy_stc_sd_host_sd_card_config_t CYBSP_SDHC_0_card_cfg = -{ - .lowVoltageSignaling = false, - .busWidth = CY_SD_HOST_BUS_WIDTH_4_BIT, - .cardType = &CYBSP_SDHC_0_cardType, - .rca = &CYBSP_SDHC_0_rca, - .cardCapacity = &CYBSP_SDHC_0_cardCapacity, -}; - -#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SDHC) -const mtb_hal_peri_div_t CYBSP_SDHC_0_clock_ref = -{ - .clk_dst = (en_clk_dst_t)CYBSP_SDHC_0_CLK_DIV_GRP_NUM, - .div_type = CYBSP_SDHC_0_CLK_DIV_HW, - .div_num = CYBSP_SDHC_0_CLK_DIV_NUM, -}; -const mtb_hal_clock_t CYBSP_SDHC_0_hal_clock = -{ - .clock_ref = &CYBSP_SDHC_0_clock_ref, - .interface = &mtb_hal_clock_peri_interface, -}; -const mtb_hal_sdhc_configurator_t CYBSP_SDHC_0_sdhc_hal_config = -{ - .base = CYBSP_SDHC_0_HW, - .host_config = &CYBSP_SDHC_0_config, - .card_config = &CYBSP_SDHC_0_card_cfg, - .clock = &CYBSP_SDHC_0_hal_clock, - .gpios = {.clk = { .pin_num = 0, .port_num = 12}, .cmd = { .pin_num = 0, .port_num = 21}, .data = {{ .pin_num = 1, .port_num = 12}, { .pin_num = 2, .port_num = 12}, { .pin_num = 4, .port_num = 12}, { .pin_num = 5, .port_num = 12}, { .pin_num = NC, .port_num = NC}, { .pin_num = NC, .port_num = NC}, { .pin_num = NC, .port_num = NC}, { .pin_num = NC, .port_num = NC}}}, -}; -#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SDHC) */ - -#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SDIO) -const mtb_hal_sdio_configurator_t CYBSP_SDHC_0_sdio_hal_config = -{ - .base = CYBSP_SDHC_0_HW, - .host_config = &CYBSP_SDHC_0_config, - .clock = &CYBSP_SDHC_0_hal_clock, - .gpios = {.clk = { .pin_num = 0, .port_num = 12}, .cmd = { .pin_num = 0, .port_num = 21}, .data = {{ .pin_num = 1, .port_num = 12}, { .pin_num = 2, .port_num = 12}, { .pin_num = 4, .port_num = 12}, { .pin_num = 5, .port_num = 12}}}, -}; -#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SDIO) */ - -cy_en_sd_host_card_capacity_t CYBSP_SDHC_1_cardCapacity = CY_SD_HOST_SDSC; -cy_en_sd_host_card_type_t CYBSP_SDHC_1_cardType = CY_SD_HOST_NOT_EMMC; -uint32_t CYBSP_SDHC_1_rca = 0u; -const cy_stc_sd_host_init_config_t CYBSP_SDHC_1_config = -{ - .emmc = false, - .dmaType = CY_SD_HOST_DMA_ADMA2, - .enableLedControl = false, -}; -cy_stc_sd_host_sd_card_config_t CYBSP_SDHC_1_card_cfg = -{ - .lowVoltageSignaling = false, - .busWidth = CY_SD_HOST_BUS_WIDTH_4_BIT, - .cardType = &CYBSP_SDHC_1_cardType, - .rca = &CYBSP_SDHC_1_rca, - .cardCapacity = &CYBSP_SDHC_1_cardCapacity, -}; - -#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SDHC) -const mtb_hal_peri_div_t CYBSP_SDHC_1_clock_ref = -{ - .clk_dst = (en_clk_dst_t)CYBSP_SDHC_1_CLK_DIV_GRP_NUM, - .div_type = CYBSP_SDHC_1_CLK_DIV_HW, - .div_num = CYBSP_SDHC_1_CLK_DIV_NUM, -}; -const mtb_hal_clock_t CYBSP_SDHC_1_hal_clock = -{ - .clock_ref = &CYBSP_SDHC_1_clock_ref, - .interface = &mtb_hal_clock_peri_interface, -}; -const mtb_hal_sdhc_configurator_t CYBSP_SDHC_1_sdhc_hal_config = -{ - .base = CYBSP_SDHC_1_HW, - .host_config = &CYBSP_SDHC_1_config, - .card_config = &CYBSP_SDHC_1_card_cfg, - .clock = &CYBSP_SDHC_1_hal_clock, - .gpios = {.clk = { .pin_num = 1, .port_num = 7}, .cmd = { .pin_num = 0, .port_num = 7}, .data = {{ .pin_num = 3, .port_num = 7}, { .pin_num = 5, .port_num = 7}, { .pin_num = 6, .port_num = 7}, { .pin_num = 7, .port_num = 7}, { .pin_num = NC, .port_num = NC}, { .pin_num = NC, .port_num = NC}, { .pin_num = NC, .port_num = NC}, { .pin_num = NC, .port_num = NC}}}, -}; -#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SDHC) */ - -#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SDIO) -const mtb_hal_sdio_configurator_t CYBSP_SDHC_1_sdio_hal_config = -{ - .base = CYBSP_SDHC_1_HW, - .host_config = &CYBSP_SDHC_1_config, - .clock = &CYBSP_SDHC_1_hal_clock, - .gpios = {.clk = { .pin_num = 1, .port_num = 7}, .cmd = { .pin_num = 0, .port_num = 7}, .data = {{ .pin_num = 3, .port_num = 7}, { .pin_num = 5, .port_num = 7}, { .pin_num = 6, .port_num = 7}, { .pin_num = 7, .port_num = 7}}}, -}; -#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SDIO) */ - -const cy_stc_smif_config_t CYBSP_SMIF_CORE_0_XSPI_FLASH_config = -{ - .mode = (uint32_t)CY_SMIF_NORMAL, - .deselectDelay = CYBSP_SMIF_CORE_0_XSPI_FLASH_DESELECT_DELAY, - .blockEvent = (uint32_t)CY_SMIF_BUS_ERROR, - .inputFrequencyMHz = 200, - .enable_internal_dll = false, - .dll_divider_value = CY_SMIF_DLL_DIVIDE_BY_2, - .rx_capture_mode = CY_SMIF_SEL_NORMAL_SPI, - .mdl_tap = CY_SMIF_MDL_8_TAP_DELAY, - .device0_sdl_tap = CY_SMIF_SDL_8_TAP_DELAY, - .device1_sdl_tap = CY_SMIF_SDL_8_TAP_DELAY, - .device2_sdl_tap = CY_SMIF_SDL_8_TAP_DELAY, - .device3_sdl_tap = CY_SMIF_SDL_8_TAP_DELAY, - .tx_sdr_extra = CY_SMIF_TX_TWO_PERIOD_AHEAD, -}; - -#if defined (COMPONENT_MTB_HAL) -const mtb_hal_hf_clock_t CYBSP_SMIF_CORE_0_XSPI_FLASH_clock_ref = -{ - .inst_num = 3U, -}; -const mtb_hal_clock_t CYBSP_SMIF_CORE_0_XSPI_FLASH_hal_clock = -{ - .clock_ref = &CYBSP_SMIF_CORE_0_XSPI_FLASH_clock_ref, - .interface = &mtb_hal_clock_hf_interface, -}; -#endif /* defined (COMPONENT_MTB_HAL) */ - -#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_MEMORYSPI) -const mtb_hal_memoryspi_configurator_t CYBSP_SMIF_CORE_0_XSPI_FLASH_hal_config = -{ - .base = SMIF0_CORE, - .clock = &CYBSP_SMIF_CORE_0_XSPI_FLASH_hal_clock, - .config = &CYBSP_SMIF_CORE_0_XSPI_FLASH_config, - .csel = {false, true, false, false}, - .irqs = CYBSP_SMIF_CORE_0_XSPI_FLASH_MEMORY_MODE_ALIGMENT_ERROR << 5 | CYBSP_SMIF_CORE_0_XSPI_FLASH_RX_DATA_FIFO_UNDERFLOW << 4 | CYBSP_SMIF_CORE_0_XSPI_FLASH_TX_COMMAND_FIFO_OVERFLOW << 3 | CYBSP_SMIF_CORE_0_XSPI_FLASH_TX_DATA_FIFO_OVERFLOW << 2 | (uint8_t)(CYBSP_SMIF_CORE_0_XSPI_FLASH_RX_FIFO_TRIGGER_LEVEL != 0) << 1 | (uint8_t)(CYBSP_SMIF_CORE_0_XSPI_FLASH_TX_FIFO_TRIGGER_LEVEL != 0) << 0, - .dmas = CYBSP_SMIF_CORE_0_XSPI_FLASH_RX_DMA_TRIGGER_OUT_USED << 1 | CYBSP_SMIF_CORE_0_XSPI_FLASH_TX_DMA_TRIGGER_OUT_USED << 0, -}; -#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_MEMORYSPI) */ - -const cy_stc_smif_config_t CYBSP_SMIF_CORE_1_PSRAM_config = -{ - .mode = (uint32_t)CY_SMIF_NORMAL, - .deselectDelay = CYBSP_SMIF_CORE_1_PSRAM_DESELECT_DELAY, - .blockEvent = (uint32_t)CY_SMIF_BUS_ERROR, - .inputFrequencyMHz = 399, - .enable_internal_dll = false, - .dll_divider_value = CY_SMIF_DLL_DIVIDE_BY_2, - .rx_capture_mode = CY_SMIF_SEL_NORMAL_SPI, - .mdl_tap = CY_SMIF_MDL_8_TAP_DELAY, - .device0_sdl_tap = CY_SMIF_SDL_8_TAP_DELAY, - .device1_sdl_tap = CY_SMIF_SDL_8_TAP_DELAY, - .device2_sdl_tap = CY_SMIF_SDL_8_TAP_DELAY, - .device3_sdl_tap = CY_SMIF_SDL_8_TAP_DELAY, - .tx_sdr_extra = CY_SMIF_TX_TWO_PERIOD_AHEAD, -}; - -#if defined (COMPONENT_MTB_HAL) -const mtb_hal_hf_clock_t CYBSP_SMIF_CORE_1_PSRAM_clock_ref = -{ - .inst_num = 4U, -}; -const mtb_hal_clock_t CYBSP_SMIF_CORE_1_PSRAM_hal_clock = -{ - .clock_ref = &CYBSP_SMIF_CORE_1_PSRAM_clock_ref, - .interface = &mtb_hal_clock_hf_interface, -}; -#endif /* defined (COMPONENT_MTB_HAL) */ - -#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_MEMORYSPI) -const mtb_hal_memoryspi_configurator_t CYBSP_SMIF_CORE_1_PSRAM_hal_config = -{ - .base = SMIF1_CORE, - .clock = &CYBSP_SMIF_CORE_1_PSRAM_hal_clock, - .config = &CYBSP_SMIF_CORE_1_PSRAM_config, - .csel = {false, false, true, false}, - .irqs = CYBSP_SMIF_CORE_1_PSRAM_MEMORY_MODE_ALIGMENT_ERROR << 5 | CYBSP_SMIF_CORE_1_PSRAM_RX_DATA_FIFO_UNDERFLOW << 4 | CYBSP_SMIF_CORE_1_PSRAM_TX_COMMAND_FIFO_OVERFLOW << 3 | CYBSP_SMIF_CORE_1_PSRAM_TX_DATA_FIFO_OVERFLOW << 2 | (uint8_t)(CYBSP_SMIF_CORE_1_PSRAM_RX_FIFO_TRIGGER_LEVEL != 0) << 1 | (uint8_t)(CYBSP_SMIF_CORE_1_PSRAM_TX_FIFO_TRIGGER_LEVEL != 0) << 0, - .dmas = CYBSP_SMIF_CORE_1_PSRAM_RX_DMA_TRIGGER_OUT_USED << 1 | CYBSP_SMIF_CORE_1_PSRAM_TX_DMA_TRIGGER_OUT_USED << 0, -}; -#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_MEMORYSPI) */ - -const cy_stc_mcwdt_config_t CYBSP_CM33_LPTIMER_0_config = -{ - .c0Match = 32768U, - .c1Match = 32768U, - .c0Mode = CY_MCWDT_MODE_INT, - .c1Mode = CY_MCWDT_MODE_INT, - .c2ToggleBit = 0U, - .c2Mode = CY_MCWDT_MODE_NONE, - .c0ClearOnMatch = false, - .c1ClearOnMatch = false, - .c0c1Cascade = true, - .c1c2Cascade = false, - .c0LowerLimitMode = CY_MCWDT_LOWER_LIMIT_MODE_NOTHING, - .c0LowerLimit = 0U, - .c1LowerLimitMode = CY_MCWDT_LOWER_LIMIT_MODE_NOTHING, - .c1LowerLimit = 0U, -}; - -#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_LPTIMER) -const mtb_hal_lptimer_configurator_t CYBSP_CM33_LPTIMER_0_hal_config = -{ - .base = CYBSP_CM33_LPTIMER_0_HW, - .lfclk_freqhz = 32768, -}; -#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_LPTIMER) */ - -const cy_stc_mcwdt_config_t CYBSP_CM55_LPTIMER_1_config = -{ - .c0Match = 32768U, - .c1Match = 32768U, - .c0Mode = CY_MCWDT_MODE_INT, - .c1Mode = CY_MCWDT_MODE_INT, - .c2ToggleBit = 0U, - .c2Mode = CY_MCWDT_MODE_NONE, - .c0ClearOnMatch = false, - .c1ClearOnMatch = false, - .c0c1Cascade = true, - .c1c2Cascade = false, - .c0LowerLimitMode = CY_MCWDT_LOWER_LIMIT_MODE_NOTHING, - .c0LowerLimit = 0U, - .c1LowerLimitMode = CY_MCWDT_LOWER_LIMIT_MODE_NOTHING, - .c1LowerLimit = 0U, -}; - -#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_LPTIMER) -const mtb_hal_lptimer_configurator_t CYBSP_CM55_LPTIMER_1_hal_config = -{ - .base = CYBSP_CM55_LPTIMER_1_HW, - .lfclk_freqhz = 32768, -}; -#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_LPTIMER) */ - -cy_stc_tdm_config_tx_t CYBSP_TDM_CONTROLLER_0_tx_config = -{ - .enable = true, - .masterMode = CY_TDM_DEVICE_MASTER, - .wordSize = CY_TDM_SIZE_16, - .format = CY_TDM_LEFT_DELAYED, - .clkDiv = 4, - .clkSel = CY_TDM_SEL_SRSS_CLK0, - .sckPolarity = CY_TDM_CLK, - .fsyncPolarity = CY_TDM_SIGN_INVERTED, - .fsyncFormat = CY_TDM_CH_PERIOD, - .channelNum = 2, - .channelSize = 16, - .fifoTriggerLevel = 64, - .chEn = 0x3, - .signalInput = 0, - .i2sMode = true, -}; -cy_stc_tdm_config_rx_t CYBSP_TDM_CONTROLLER_0_rx_config = -{ - .enable = false, - .masterMode = CY_TDM_DEVICE_SLAVE, - .wordSize = CY_TDM_SIZE_16, - .signExtend = CY_ZERO_EXTEND, - .format = CY_TDM_LEFT_DELAYED, - .clkDiv = 16, - .clkSel = CY_TDM_SEL_SRSS_CLK0, - .sckPolarity = CY_TDM_CLK, - .fsyncPolarity = CY_TDM_SIGN, - .lateSample = false, - .fsyncFormat = CY_TDM_BIT_PERIOD, - .channelNum = 2, - .channelSize = 16, - .fifoTriggerLevel = 0, - .chEn = 0x3, - .signalInput = 0, - .i2sMode = true, -}; -const cy_stc_tdm_config_t CYBSP_TDM_CONTROLLER_0_config = -{ - .tx_config = &CYBSP_TDM_CONTROLLER_0_tx_config, - .rx_config = &CYBSP_TDM_CONTROLLER_0_rx_config, -}; -const cy_stc_tcpwm_counter_config_t CYBSP_GENERAL_PURPOSE_TIMER_config = -{ - .period = 9999, - .clockPrescaler = CY_TCPWM_COUNTER_PRESCALER_DIVBY_1, - .runMode = CY_TCPWM_COUNTER_CONTINUOUS, - .countDirection = CY_TCPWM_COUNTER_COUNT_UP, - .compareOrCapture = CY_TCPWM_COUNTER_MODE_COMPARE, - .compare0 = 9999, - .compare1 = 16384, - .enableCompareSwap = false, - .interruptSources = (CY_TCPWM_INT_ON_TC ) | (CY_TCPWM_INT_ON_CC0 & 0U) | (CY_TCPWM_INT_ON_CC1 & 0U), - .captureInputMode = CYBSP_GENERAL_PURPOSE_TIMER_INPUT_DISABLED & 0x3U, - .captureInput = CY_TCPWM_INPUT_0, - .reloadInputMode = CYBSP_GENERAL_PURPOSE_TIMER_INPUT_DISABLED & 0x3U, - .reloadInput = CY_TCPWM_INPUT_0, - .startInputMode = CYBSP_GENERAL_PURPOSE_TIMER_INPUT_DISABLED & 0x3U, - .startInput = CY_TCPWM_INPUT_0, - .stopInputMode = CYBSP_GENERAL_PURPOSE_TIMER_INPUT_DISABLED & 0x3U, - .stopInput = CY_TCPWM_INPUT_0, - .countInputMode = CYBSP_GENERAL_PURPOSE_TIMER_INPUT_DISABLED & 0x3U, - .countInput = CY_TCPWM_INPUT_1, - .capture1InputMode = CYBSP_GENERAL_PURPOSE_TIMER_INPUT_DISABLED & 0x3U, - .capture1Input = CY_TCPWM_INPUT_0, - .compare2 = CY_TCPWM_GRP_CNT_CC0_DEFAULT, - .compare3 = CY_TCPWM_GRP_CNT_CC0_BUFF_DEFAULT, - .enableCompare1Swap = false, - .trigger0Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, - .trigger1Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, -#if defined (CY_IP_MXS40TCPWM) - .buffer_swap_enable = false, - .direction_mode = CY_TCPWM_COUNTER_DIRECTION_DISABLE, - .glitch_filter_enable = false, - .gf_depth = CY_GLITCH_FILTER_DEPTH_SUPPORT_VALUE_0, -#endif /* defined (CY_IP_MXS40TCPWM) */ -}; - -#if defined (COMPONENT_MTB_HAL) -const mtb_hal_peri_div_t CYBSP_GENERAL_PURPOSE_TIMER_clock_ref = -{ - .clk_dst = (en_clk_dst_t)PCLK_TCPWM0_CLOCK_COUNTER_EN0, - .div_type = CY_SYSCLK_DIV_16_BIT, - .div_num = 2, -}; -const mtb_hal_clock_t CYBSP_GENERAL_PURPOSE_TIMER_hal_clock = -{ - .clock_ref = &CYBSP_GENERAL_PURPOSE_TIMER_clock_ref, - .interface = &mtb_hal_clock_peri_interface, -}; -#endif /* defined (COMPONENT_MTB_HAL) */ - -#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_TIMER) -const mtb_hal_timer_configurator_t CYBSP_GENERAL_PURPOSE_TIMER_hal_config = -{ - .tcpwm_base = CYBSP_GENERAL_PURPOSE_TIMER_HW, - .clock = &CYBSP_GENERAL_PURPOSE_TIMER_hal_clock, - .tcpwm_cntnum = 0U, -}; -#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_TIMER) */ - -cy_stc_tcpwm_counter_config_t emUSB_OS_Timer_config = -{ - .period = 99999, - .clockPrescaler = CY_TCPWM_COUNTER_PRESCALER_DIVBY_1, - .runMode = CY_TCPWM_COUNTER_CONTINUOUS, - .countDirection = CY_TCPWM_COUNTER_COUNT_UP, - .compareOrCapture = CY_TCPWM_COUNTER_MODE_CAPTURE, - .compare0 = 16384U, - .compare1 = 16384U, - .enableCompareSwap = false, - .interruptSources = (CY_TCPWM_INT_ON_TC & 0U) | (CY_TCPWM_INT_ON_CC0) | (CY_TCPWM_INT_ON_CC1 & 0U), - .captureInputMode = emUSB_OS_Timer_INPUT_DISABLED & 0x3U, - .captureInput = CY_TCPWM_INPUT_0, - .reloadInputMode = emUSB_OS_Timer_INPUT_DISABLED & 0x3U, - .reloadInput = CY_TCPWM_INPUT_0, - .startInputMode = emUSB_OS_Timer_INPUT_DISABLED & 0x3U, - .startInput = CY_TCPWM_INPUT_0, - .stopInputMode = emUSB_OS_Timer_INPUT_DISABLED & 0x3U, - .stopInput = CY_TCPWM_INPUT_0, - .countInputMode = emUSB_OS_Timer_INPUT_DISABLED & 0x3U, - .countInput = CY_TCPWM_INPUT_1, - .capture1InputMode = emUSB_OS_Timer_INPUT_DISABLED & 0x3U, - .capture1Input = CY_TCPWM_INPUT_0, - .compare2 = CY_TCPWM_GRP_CNT_CC0_DEFAULT, - .compare3 = CY_TCPWM_GRP_CNT_CC0_BUFF_DEFAULT, - .enableCompare1Swap = false, - .trigger0Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, - .trigger1Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, -}; - -#if defined (COMPONENT_MTB_HAL) -mtb_hal_peri_div_t emUSB_OS_Timer_clock_ref = -{ - .clk_dst = (en_clk_dst_t)PCLK_TCPWM0_CLOCK_COUNTER_EN1, - .div_type = CY_SYSCLK_DIV_8_BIT, - .div_num = 2, -}; -mtb_hal_clock_t emUSB_OS_Timer_hal_clock = -{ - .clock_ref = &emUSB_OS_Timer_clock_ref, - .interface = &mtb_hal_clock_peri_interface, -}; -#endif /* defined (COMPONENT_MTB_HAL) */ - -#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_TIMER) -mtb_hal_timer_configurator_t emUSB_OS_Timer_hal_config = -{ - .tcpwm_base = emUSB_OS_Timer_HW, - .clock = &emUSB_OS_Timer_hal_clock, - .tcpwm_cntnum = 1U, -}; -#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_TIMER) */ - -const cy_stc_tcpwm_pwm_config_t CYBSP_PWM_LED_CTRL_config = -{ - .pwmMode = CY_TCPWM_PWM_MODE_PWM, - .clockPrescaler = CY_TCPWM_PWM_PRESCALER_DIVBY_1, - .pwmAlignment = CY_TCPWM_PWM_LEFT_ALIGN, - .deadTimeClocks = 0, - .runMode = CY_TCPWM_PWM_CONTINUOUS, - .period0 = 2000, - .period1 = 32768, - .enablePeriodSwap = false, - .compare0 = 1000, - .compare1 = 16384, - .enableCompareSwap = false, - .interruptSources = (CY_TCPWM_INT_ON_TC & 0U) | (CY_TCPWM_INT_ON_CC0 & 0U) | (CY_TCPWM_INT_ON_CC1 & 0U), - .invertPWMOut = CY_TCPWM_PWM_INVERT_DISABLE, - .invertPWMOutN = CY_TCPWM_PWM_INVERT_DISABLE, - .killMode = CY_TCPWM_PWM_ASYNC_KILL, - .swapInputMode = CYBSP_PWM_LED_CTRL_INPUT_DISABLED & 0x3U, - .swapInput = CY_TCPWM_INPUT_0, - .reloadInputMode = CYBSP_PWM_LED_CTRL_INPUT_DISABLED & 0x3U, - .reloadInput = CY_TCPWM_INPUT_0, - .startInputMode = CYBSP_PWM_LED_CTRL_INPUT_DISABLED & 0x3U, - .startInput = CY_TCPWM_INPUT_0, - .killInputMode = CYBSP_PWM_LED_CTRL_INPUT_DISABLED & 0x3U, - .killInput = CY_TCPWM_INPUT_0, - .countInputMode = CYBSP_PWM_LED_CTRL_INPUT_DISABLED & 0x3U, - .countInput = CY_TCPWM_INPUT_1, - .swapOverflowUnderflow = false, - .immediateKill = false, - .tapsEnabled = 45, - .compare2 = CY_TCPWM_GRP_CNT_CC0_DEFAULT, - .compare3 = CY_TCPWM_GRP_CNT_CC0_BUFF_DEFAULT, - .enableCompare1Swap = false, - .compare0MatchUp = true, - .compare0MatchDown = false, - .compare1MatchUp = true, - .compare1MatchDown = false, - .kill1InputMode = CYBSP_PWM_LED_CTRL_INPUT_DISABLED & 0x3U, - .kill1Input = CY_TCPWM_INPUT_0, - .pwmOnDisable = CY_TCPWM_PWM_OUTPUT_HIGHZ, - .trigger0Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, - .trigger1Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, - .reloadLineSelect = false, - .line_out_sel = CY_TCPWM_OUTPUT_PWM_SIGNAL, - .linecompl_out_sel = CY_TCPWM_OUTPUT_INVERTED_PWM_SIGNAL, - .line_out_sel_buff = CY_TCPWM_OUTPUT_PWM_SIGNAL, - .linecompl_out_sel_buff = CY_TCPWM_OUTPUT_INVERTED_PWM_SIGNAL, - .deadTimeClocks_linecompl_out = 0, -#if defined (CY_IP_MXS40TCPWM) - .hrpwm_enable = false, - .hrpwm_input_freq = CY_TCPWM_HRPWM_FREQ_80MHZ_OR_100MHZ, - .kill_line_polarity = CY_TCPWM_LINEOUT_AND_LINECMPOUT_IS_LOW, - .deadTimeClocksBuff = 0, - .deadTimeClocksBuff_linecompl_out = 0, - .buffer_swap_enable = false, - .glitch_filter_enable = false, - .gf_depth = CY_GLITCH_FILTER_DEPTH_SUPPORT_VALUE_0, - .dithering_mode = CY_TCPWM_DITHERING_DISABLE, - .period_dithering_value = 128, - .duty_dithering_value = 128, - .limiter = CY_TCPWM_DITHERING_LIMITER_7, - .pwm_tc_sync_kill_dt = false, - .pwm_sync_kill_dt = false, -#endif /* defined (CY_IP_MXS40TCPWM) */ -}; - -#if defined (COMPONENT_MTB_HAL) -const mtb_hal_peri_div_t CYBSP_PWM_LED_CTRL_clock_ref = -{ - .clk_dst = (en_clk_dst_t)PCLK_TCPWM0_CLOCK_COUNTER_EN5, - .div_type = CY_SYSCLK_DIV_16_BIT, - .div_num = 3, -}; -const mtb_hal_clock_t CYBSP_PWM_LED_CTRL_hal_clock = -{ - .clock_ref = &CYBSP_PWM_LED_CTRL_clock_ref, - .interface = &mtb_hal_clock_peri_interface, -}; -#endif /* defined (COMPONENT_MTB_HAL) */ - -#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) -const mtb_hal_pwm_configurator_t CYBSP_PWM_LED_CTRL_hal_config = -{ - .base = CYBSP_PWM_LED_CTRL_HW, - .clock = &CYBSP_PWM_LED_CTRL_hal_clock, - .group = 0UL, - .cntnum = 5UL, - .max_count = 2000, -}; -#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) */ - -const cy_stc_tcpwm_pwm_config_t CYBSP_DEAD_TIME_PWM_config = -{ - .pwmMode = CY_TCPWM_PWM_MODE_DEADTIME, - .clockPrescaler = CY_TCPWM_PWM_PRESCALER_DIVBY_1, - .pwmAlignment = CY_TCPWM_PWM_LEFT_ALIGN, - .deadTimeClocks = 100, - .runMode = CY_TCPWM_PWM_CONTINUOUS, - .period0 = 400, - .period1 = 32768, - .enablePeriodSwap = false, - .compare0 = 200, - .compare1 = 16384, - .enableCompareSwap = false, - .interruptSources = (CY_TCPWM_INT_ON_TC & 0U) | (CY_TCPWM_INT_ON_CC0 & 0U) | (CY_TCPWM_INT_ON_CC1 & 0U), - .invertPWMOut = CY_TCPWM_PWM_INVERT_DISABLE, - .invertPWMOutN = CY_TCPWM_PWM_INVERT_DISABLE, - .killMode = CY_TCPWM_PWM_STOP_ON_KILL, - .swapInputMode = CYBSP_DEAD_TIME_PWM_INPUT_DISABLED & 0x3U, - .swapInput = CY_TCPWM_INPUT_0, - .reloadInputMode = CYBSP_DEAD_TIME_PWM_INPUT_DISABLED & 0x3U, - .reloadInput = CY_TCPWM_INPUT_0, - .startInputMode = CYBSP_DEAD_TIME_PWM_INPUT_DISABLED & 0x3U, - .startInput = CY_TCPWM_INPUT_0, - .killInputMode = CYBSP_DEAD_TIME_PWM_INPUT_DISABLED & 0x3U, - .killInput = CY_TCPWM_INPUT_0, - .countInputMode = CYBSP_DEAD_TIME_PWM_INPUT_DISABLED & 0x3U, - .countInput = CY_TCPWM_INPUT_1, - .swapOverflowUnderflow = false, - .immediateKill = false, - .tapsEnabled = 45, - .compare2 = CY_TCPWM_GRP_CNT_CC0_DEFAULT, - .compare3 = CY_TCPWM_GRP_CNT_CC0_BUFF_DEFAULT, - .enableCompare1Swap = false, - .compare0MatchUp = true, - .compare0MatchDown = false, - .compare1MatchUp = true, - .compare1MatchDown = false, - .kill1InputMode = CYBSP_DEAD_TIME_PWM_INPUT_DISABLED & 0x3U, - .kill1Input = CY_TCPWM_INPUT_0, - .pwmOnDisable = CY_TCPWM_PWM_OUTPUT_HIGHZ, - .trigger0Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, - .trigger1Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, - .reloadLineSelect = false, - .line_out_sel = CY_TCPWM_OUTPUT_PWM_SIGNAL, - .linecompl_out_sel = CY_TCPWM_OUTPUT_INVERTED_PWM_SIGNAL, - .line_out_sel_buff = CY_TCPWM_OUTPUT_PWM_SIGNAL, - .linecompl_out_sel_buff = CY_TCPWM_OUTPUT_INVERTED_PWM_SIGNAL, - .deadTimeClocks_linecompl_out = 100, -#if defined (CY_IP_MXS40TCPWM) - .hrpwm_enable = false, - .hrpwm_input_freq = CY_TCPWM_HRPWM_FREQ_80MHZ_OR_100MHZ, - .kill_line_polarity = CY_TCPWM_LINEOUT_AND_LINECMPOUT_IS_LOW, - .deadTimeClocksBuff = 0, - .deadTimeClocksBuff_linecompl_out = 0, - .buffer_swap_enable = false, - .glitch_filter_enable = false, - .gf_depth = CY_GLITCH_FILTER_DEPTH_SUPPORT_VALUE_0, - .dithering_mode = CY_TCPWM_DITHERING_DISABLE, - .period_dithering_value = 128, - .duty_dithering_value = 128, - .limiter = CY_TCPWM_DITHERING_LIMITER_7, - .pwm_tc_sync_kill_dt = false, - .pwm_sync_kill_dt = false, -#endif /* defined (CY_IP_MXS40TCPWM) */ -}; - -#if defined (COMPONENT_MTB_HAL) -const mtb_hal_peri_div_t CYBSP_DEAD_TIME_PWM_clock_ref = -{ - .clk_dst = (en_clk_dst_t)PCLK_TCPWM0_CLOCK_COUNTER_EN7, - .div_type = CY_SYSCLK_DIV_8_BIT, - .div_num = 3, -}; -const mtb_hal_clock_t CYBSP_DEAD_TIME_PWM_hal_clock = -{ - .clock_ref = &CYBSP_DEAD_TIME_PWM_clock_ref, - .interface = &mtb_hal_clock_peri_interface, -}; -#endif /* defined (COMPONENT_MTB_HAL) */ - -#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) -const mtb_hal_pwm_configurator_t CYBSP_DEAD_TIME_PWM_hal_config = -{ - .base = CYBSP_DEAD_TIME_PWM_HW, - .clock = &CYBSP_DEAD_TIME_PWM_hal_clock, - .group = 0UL, - .cntnum = 7UL, - .max_count = 400, -}; -#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) */ - -const cy_stc_tcpwm_pwm_config_t CYBSP_SMARTIO_PWM_config = -{ - .pwmMode = CY_TCPWM_PWM_MODE_PWM, - .clockPrescaler = CY_TCPWM_PWM_PRESCALER_DIVBY_1, - .pwmAlignment = CY_TCPWM_PWM_LEFT_ALIGN, - .deadTimeClocks = 0, - .runMode = CY_TCPWM_PWM_CONTINUOUS, - .period0 = 399, - .period1 = 32768, - .enablePeriodSwap = false, - .compare0 = 200, - .compare1 = 16384, - .enableCompareSwap = false, - .interruptSources = (CY_TCPWM_INT_ON_TC & 0U) | (CY_TCPWM_INT_ON_CC0 & 0U) | (CY_TCPWM_INT_ON_CC1 & 0U), - .invertPWMOut = CY_TCPWM_PWM_INVERT_DISABLE, - .invertPWMOutN = CY_TCPWM_PWM_INVERT_DISABLE, - .killMode = CY_TCPWM_PWM_ASYNC_KILL, - .swapInputMode = CYBSP_SMARTIO_PWM_INPUT_DISABLED & 0x3U, - .swapInput = CY_TCPWM_INPUT_0, - .reloadInputMode = CYBSP_SMARTIO_PWM_INPUT_DISABLED & 0x3U, - .reloadInput = CY_TCPWM_INPUT_0, - .startInputMode = CYBSP_SMARTIO_PWM_INPUT_DISABLED & 0x3U, - .startInput = CY_TCPWM_INPUT_0, - .killInputMode = CYBSP_SMARTIO_PWM_INPUT_DISABLED & 0x3U, - .killInput = CY_TCPWM_INPUT_0, - .countInputMode = CYBSP_SMARTIO_PWM_INPUT_DISABLED & 0x3U, - .countInput = CY_TCPWM_INPUT_1, - .swapOverflowUnderflow = false, - .immediateKill = false, - .tapsEnabled = 45, - .compare2 = 200, - .compare3 = 16384, - .enableCompare1Swap = false, - .compare0MatchUp = true, - .compare0MatchDown = false, - .compare1MatchUp = true, - .compare1MatchDown = false, - .kill1InputMode = CYBSP_SMARTIO_PWM_INPUT_DISABLED & 0x3U, - .kill1Input = CY_TCPWM_INPUT_0, - .pwmOnDisable = CY_TCPWM_PWM_OUTPUT_HIGHZ, - .trigger0Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, - .trigger1Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, - .reloadLineSelect = false, - .line_out_sel = CY_TCPWM_OUTPUT_PWM_SIGNAL, - .linecompl_out_sel = CY_TCPWM_OUTPUT_INVERTED_PWM_SIGNAL, - .line_out_sel_buff = CY_TCPWM_OUTPUT_PWM_SIGNAL, - .linecompl_out_sel_buff = CY_TCPWM_OUTPUT_INVERTED_PWM_SIGNAL, - .deadTimeClocks_linecompl_out = 0, -#if defined (CY_IP_MXS40TCPWM) - .hrpwm_enable = false, - .hrpwm_input_freq = CY_TCPWM_HRPWM_FREQ_80MHZ_OR_100MHZ, - .kill_line_polarity = CY_TCPWM_LINEOUT_AND_LINECMPOUT_IS_LOW, - .deadTimeClocksBuff = 0, - .deadTimeClocksBuff_linecompl_out = 0, - .buffer_swap_enable = false, - .glitch_filter_enable = false, - .gf_depth = CY_GLITCH_FILTER_DEPTH_SUPPORT_VALUE_0, - .dithering_mode = CY_TCPWM_DITHERING_DISABLE, - .period_dithering_value = 128, - .duty_dithering_value = 128, - .limiter = CY_TCPWM_DITHERING_LIMITER_7, - .pwm_tc_sync_kill_dt = false, - .pwm_sync_kill_dt = false, -#endif /* defined (CY_IP_MXS40TCPWM) */ -}; - -#if defined (COMPONENT_MTB_HAL) -const mtb_hal_peri_div_t CYBSP_SMARTIO_PWM_clock_ref = -{ - .clk_dst = (en_clk_dst_t)PCLK_TCPWM0_CLOCK_COUNTER_EN262, - .div_type = CY_SYSCLK_DIV_16_5_BIT, - .div_num = 1, -}; -const mtb_hal_clock_t CYBSP_SMARTIO_PWM_hal_clock = -{ - .clock_ref = &CYBSP_SMARTIO_PWM_clock_ref, - .interface = &mtb_hal_clock_peri_interface, -}; -#endif /* defined (COMPONENT_MTB_HAL) */ - -#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) -const mtb_hal_pwm_configurator_t CYBSP_SMARTIO_PWM_hal_config = -{ - .base = CYBSP_SMARTIO_PWM_HW, - .clock = &CYBSP_SMARTIO_PWM_hal_clock, - .group = 1UL, - .cntnum = 262UL, - .max_count = 399, -}; -#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) */ - -const cy_stc_tcpwm_pwm_config_t tcpwm_0_group_1_cnt_9_config = -{ - .pwmMode = CY_TCPWM_PWM_MODE_PWM, - .clockPrescaler = CY_TCPWM_PWM_PRESCALER_DIVBY_2, - .pwmAlignment = CY_TCPWM_PWM_LEFT_ALIGN, - .deadTimeClocks = 0, - .runMode = CY_TCPWM_PWM_CONTINUOUS, - .period0 = 65535, - .period1 = 32768, - .enablePeriodSwap = false, - .compare0 = 52428, - .compare1 = 16384, - .enableCompareSwap = false, - .interruptSources = (CY_TCPWM_INT_ON_TC & 0U) | (CY_TCPWM_INT_ON_CC0 & 0U) | (CY_TCPWM_INT_ON_CC1 & 0U), - .invertPWMOut = CY_TCPWM_PWM_INVERT_DISABLE, - .invertPWMOutN = CY_TCPWM_PWM_INVERT_DISABLE, - .killMode = CY_TCPWM_PWM_STOP_ON_KILL, - .swapInputMode = tcpwm_0_group_1_cnt_9_INPUT_DISABLED & 0x3U, - .swapInput = CY_TCPWM_INPUT_0, - .reloadInputMode = tcpwm_0_group_1_cnt_9_INPUT_DISABLED & 0x3U, - .reloadInput = CY_TCPWM_INPUT_0, - .startInputMode = tcpwm_0_group_1_cnt_9_INPUT_DISABLED & 0x3U, - .startInput = CY_TCPWM_INPUT_0, - .killInputMode = tcpwm_0_group_1_cnt_9_INPUT_DISABLED & 0x3U, - .killInput = CY_TCPWM_INPUT_0, - .countInputMode = tcpwm_0_group_1_cnt_9_INPUT_DISABLED & 0x3U, - .countInput = CY_TCPWM_INPUT_1, - .swapOverflowUnderflow = false, - .immediateKill = false, - .tapsEnabled = 45, - .compare2 = 52428, - .compare3 = 16384, - .enableCompare1Swap = false, - .compare0MatchUp = true, - .compare0MatchDown = false, - .compare1MatchUp = true, - .compare1MatchDown = false, - .kill1InputMode = tcpwm_0_group_1_cnt_9_INPUT_DISABLED & 0x3U, - .kill1Input = CY_TCPWM_INPUT_0, - .pwmOnDisable = CY_TCPWM_PWM_OUTPUT_HIGHZ, - .trigger0Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, - .trigger1Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, - .reloadLineSelect = false, - .line_out_sel = CY_TCPWM_OUTPUT_PWM_SIGNAL, - .linecompl_out_sel = CY_TCPWM_OUTPUT_INVERTED_PWM_SIGNAL, - .line_out_sel_buff = CY_TCPWM_OUTPUT_PWM_SIGNAL, - .linecompl_out_sel_buff = CY_TCPWM_OUTPUT_INVERTED_PWM_SIGNAL, - .deadTimeClocks_linecompl_out = 0, -#if defined (CY_IP_MXS40TCPWM) - .hrpwm_enable = false, - .hrpwm_input_freq = CY_TCPWM_HRPWM_FREQ_80MHZ_OR_100MHZ, - .kill_line_polarity = CY_TCPWM_LINEOUT_AND_LINECMPOUT_IS_LOW, - .deadTimeClocksBuff = 0, - .deadTimeClocksBuff_linecompl_out = 0, - .buffer_swap_enable = false, - .glitch_filter_enable = false, - .gf_depth = CY_GLITCH_FILTER_DEPTH_SUPPORT_VALUE_0, - .dithering_mode = CY_TCPWM_DITHERING_DISABLE, - .period_dithering_value = 128, - .duty_dithering_value = 128, - .limiter = CY_TCPWM_DITHERING_LIMITER_7, - .pwm_tc_sync_kill_dt = false, - .pwm_sync_kill_dt = false, -#endif /* defined (CY_IP_MXS40TCPWM) */ -}; - -#if defined (COMPONENT_MTB_HAL) -const mtb_hal_peri_div_t tcpwm_0_group_1_cnt_9_clock_ref = -{ - .clk_dst = (en_clk_dst_t)PCLK_TCPWM0_CLOCK_COUNTER_EN265, - .div_type = CY_SYSCLK_DIV_8_BIT, - .div_num = 4, -}; -const mtb_hal_clock_t tcpwm_0_group_1_cnt_9_hal_clock = -{ - .clock_ref = &tcpwm_0_group_1_cnt_9_clock_ref, - .interface = &mtb_hal_clock_peri_interface, -}; -#endif /* defined (COMPONENT_MTB_HAL) */ - -#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) -const mtb_hal_pwm_configurator_t tcpwm_0_group_1_cnt_9_hal_config = -{ - .base = tcpwm_0_group_1_cnt_9_HW, - .clock = &tcpwm_0_group_1_cnt_9_hal_clock, - .group = 1UL, - .cntnum = 265UL, - .max_count = 65535, -}; -#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) */ - -void init_cycfg_peripherals(void) -{ - Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_PASS_PERI_NR, CY_MMIO_PASS_GROUP_NR, CY_MMIO_PASS_SLAVE_NR, CY_MMIO_PASS_CLK_HF_NR); - Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_GFXSS_GPU_PERI_NR, CY_MMIO_GFXSS_GPU_GROUP_NR, CY_MMIO_GFXSS_GPU_SLAVE_NR, CY_MMIO_GFXSS_GPU_CLK_HF_NR); - Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_GFXSS_DC_PERI_NR, CY_MMIO_GFXSS_DC_GROUP_NR, CY_MMIO_GFXSS_DC_SLAVE_NR, CY_MMIO_GFXSS_DC_CLK_HF_NR); - Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_GFXSS_MIPIDSI_PERI_NR, CY_MMIO_GFXSS_MIPIDSI_GROUP_NR, CY_MMIO_GFXSS_MIPIDSI_SLAVE_NR, CY_MMIO_GFXSS_MIPIDSI_CLK_HF_NR); - Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_I3C_PERI_NR, CY_MMIO_I3C_GROUP_NR, CY_MMIO_I3C_SLAVE_NR, CY_MMIO_I3C_CLK_HF_NR); - Cy_SysClk_PeriphAssignDivider(PCLK_I3C_CLOCK_I3C_EN, CY_SYSCLK_DIV_8_BIT, 0U); -#if defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) - Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_PDM0_PERI_NR, CY_MMIO_PDM0_GROUP_NR, CY_MMIO_PDM0_SLAVE_NR, CY_MMIO_PDM0_CLK_HF_NR); -#endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */ - Cy_SysClk_PeriPclkAssignDivider(PCLK_PDM0_CLK_IF_SRSS, CY_SYSCLK_DIV_16_5_BIT, 1U); - Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SCB0_PERI_NR, CY_MMIO_SCB0_GROUP_NR, CY_MMIO_SCB0_SLAVE_NR, CY_MMIO_SCB0_CLK_HF_NR); - Cy_SysClk_PeriPclkAssignDivider(PCLK_SCB0_CLOCK_SCB_EN, CY_SYSCLK_DIV_16_BIT, 0U); - Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SCB2_PERI_NR, CY_MMIO_SCB2_GROUP_NR, CY_MMIO_SCB2_SLAVE_NR, CY_MMIO_SCB2_CLK_HF_NR); - Cy_SysClk_PeriPclkAssignDivider(PCLK_SCB2_CLOCK_SCB_EN, CY_SYSCLK_DIV_16_BIT, 1U); - Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SCB4_PERI_NR, CY_MMIO_SCB4_GROUP_NR, CY_MMIO_SCB4_SLAVE_NR, CY_MMIO_SCB4_CLK_HF_NR); - Cy_SysClk_PeriPclkAssignDivider(PCLK_SCB4_CLOCK_SCB_EN, CY_SYSCLK_DIV_16_5_BIT, 0U); - Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SCB5_PERI_NR, CY_MMIO_SCB5_GROUP_NR, CY_MMIO_SCB5_SLAVE_NR, CY_MMIO_SCB5_CLK_HF_NR); - Cy_SysClk_PeriPclkAssignDivider(PCLK_SCB5_CLOCK_SCB_EN, CY_SYSCLK_DIV_8_BIT, 0U); - Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SCB10_PERI_NR, CY_MMIO_SCB10_GROUP_NR, CY_MMIO_SCB10_SLAVE_NR, CY_MMIO_SCB10_CLK_HF_NR); - Cy_SysClk_PeriPclkAssignDivider(PCLK_SCB10_CLOCK_SCB_EN, CY_SYSCLK_DIV_8_BIT, 1U); -#if defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) - Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SDHC0_PERI_NR, CY_MMIO_SDHC0_GROUP_NR, CY_MMIO_SDHC0_SLAVE_NR, CY_MMIO_SDHC0_CLK_HF_NR); -#endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */ - Cy_SysClk_PeriPclkAssignDivider(PCLK_SDHC0_CLK_HF, CY_SYSCLK_DIV_8_BIT, 0U); -#if defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) - Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SDHC1_PERI_NR, CY_MMIO_SDHC1_GROUP_NR, CY_MMIO_SDHC1_SLAVE_NR, CY_MMIO_SDHC1_CLK_HF_NR); -#endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */ - Cy_SysClk_PeriPclkAssignDivider(PCLK_SDHC1_CLK_HF, CY_SYSCLK_DIV_8_BIT, 0U); - Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_USBHS_PERI_NR, CY_MMIO_USBHS_GROUP_NR, CY_MMIO_USBHS_SLAVE_NR, CY_MMIO_USBHS_CLK_HF_NR); - Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SMIF0_PERI_NR, CY_MMIO_SMIF0_GROUP_NR, CY_MMIO_SMIF0_SLAVE_NR, CY_MMIO_SMIF0_CLK_HF_NR); - Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SMIF01_PERI_NR, CY_MMIO_SMIF01_GROUP_NR, CY_MMIO_SMIF01_SLAVE_NR, CY_MMIO_SMIF01_CLK_HF_NR); -#if defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) - Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_TDM0_PERI_NR, CY_MMIO_TDM0_GROUP_NR, CY_MMIO_TDM0_SLAVE_NR, CY_MMIO_TDM0_CLK_HF_NR); -#endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */ - Cy_SysClk_PeriPclkAssignDivider(PCLK_TDM0_CLK_IF_SRSS0, CY_SYSCLK_DIV_16_5_BIT, 0U); -#if defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) - Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_TCPWM0_PERI_NR, CY_MMIO_TCPWM0_GROUP_NR, CY_MMIO_TCPWM0_SLAVE_NR, CY_MMIO_TCPWM0_CLK_HF_NR); -#endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */ - Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCK_COUNTER_EN0, CY_SYSCLK_DIV_16_BIT, 2U); -#if defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) - Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_TCPWM0_PERI_NR, CY_MMIO_TCPWM0_GROUP_NR, CY_MMIO_TCPWM0_SLAVE_NR, CY_MMIO_TCPWM0_CLK_HF_NR); -#endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */ - Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCK_COUNTER_EN1, CY_SYSCLK_DIV_8_BIT, 2U); -#if defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) - Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_TCPWM0_PERI_NR, CY_MMIO_TCPWM0_GROUP_NR, CY_MMIO_TCPWM0_SLAVE_NR, CY_MMIO_TCPWM0_CLK_HF_NR); -#endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */ - Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCK_COUNTER_EN5, CY_SYSCLK_DIV_16_BIT, 3U); -#if defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) - Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_TCPWM0_PERI_NR, CY_MMIO_TCPWM0_GROUP_NR, CY_MMIO_TCPWM0_SLAVE_NR, CY_MMIO_TCPWM0_CLK_HF_NR); -#endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */ - Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCK_COUNTER_EN7, CY_SYSCLK_DIV_8_BIT, 3U); -#if defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) - Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_TCPWM0_PERI_NR, CY_MMIO_TCPWM0_GROUP_NR, CY_MMIO_TCPWM0_SLAVE_NR, CY_MMIO_TCPWM0_CLK_HF_NR); -#endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */ - Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCK_COUNTER_EN262, CY_SYSCLK_DIV_16_5_BIT, 1U); -#if defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) - Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_TCPWM0_PERI_NR, CY_MMIO_TCPWM0_GROUP_NR, CY_MMIO_TCPWM0_SLAVE_NR, CY_MMIO_TCPWM0_CLK_HF_NR); -#endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */ - Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCK_COUNTER_EN265, CY_SYSCLK_DIV_8_BIT, 4U); -} +/******************************************************************************* + * File Name: cycfg_peripherals.c + * + * Description: + * Analog configuration + * This file was automatically generated and should not be modified. + * Configurator Backend 3.70.0 + * device-db 4.35.0.9884 + * mtb-dsl-pse8xxgp 1.4.0.994 + * + ******************************************************************************* + * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************/ + +#include "cycfg_peripherals.h" + +#define CYBSP_CAN_FD_CH_0_STD_ID_FILTER_0 \ +{\ + .sfid2 = 0xFFU, \ + .sfid1 = 0x10U, \ + .sfec = CY_CANFD_SFEC_DISABLE, \ + .sft = CY_CANFD_SFT_RANGE_SFID1_SFID2, \ + } +#define CYBSP_CAN_FD_CH_0_EXT_ID_FILTER_0 \ +{\ + .f0_f = &CYBSP_CAN_FD_CH_0_extIdFilterF0Config_0, \ + .f1_f = &CYBSP_CAN_FD_CH_0_extIdFilterF1Config_0, \ + } +#define CYBSP_GENERAL_PURPOSE_TIMER_INPUT_DISABLED 0x7U +#define emUSB_OS_Timer_INPUT_DISABLED 0x7U +#define CYBSP_PWM_LED_CTRL_INPUT_DISABLED 0x7U +#define CYBSP_DEAD_TIME_PWM_INPUT_DISABLED 0x7U +#define CYBSP_SMARTIO_PWM_INPUT_DISABLED 0x7U +#define tcpwm_0_group_1_cnt_9_INPUT_DISABLED 0x7U + +cy_stc_autanalog_cfg_t autonomous_analog_cfg = +{ + .prb = NULL, + .ac = &CYBSP_AUTONOMOUS_CONTROLLER_cfg, + .ctb = + { + NULL, + NULL, + }, + .ptcomp = + { + NULL, + }, + .dac = + { + NULL, + NULL, + }, + .sar = + { + &CYBSP_SAR_ADC_cfg, + }, +}; +cy_stc_autanalog_stt_t autonomous_analog_stt[] = +{ + { + .ac = &CYBSP_AUTONOMOUS_CONTROLLER_stt[0U], + .prb = NULL, + .ctb = + { + NULL, + NULL, + }, + .ptcomp = + { + NULL, + }, + .dac = + { + NULL, + NULL, + }, + .sar = + { + &CYBSP_SAR_ADC_stt[0U], + }, + }, + { + .ac = &CYBSP_AUTONOMOUS_CONTROLLER_stt[1U], + .prb = NULL, + .ctb = + { + NULL, + NULL, + }, + .ptcomp = + { + NULL, + }, + .dac = + { + NULL, + NULL, + }, + .sar = + { + &CYBSP_SAR_ADC_stt[1U], + }, + }, + { + .ac = &CYBSP_AUTONOMOUS_CONTROLLER_stt[2U], + .prb = NULL, + .ctb = + { + NULL, + NULL, + }, + .ptcomp = + { + NULL, + }, + .dac = + { + NULL, + NULL, + }, + .sar = + { + &CYBSP_SAR_ADC_stt[2U], + }, + }, +}; +cy_stc_autanalog_t autonomous_analog_init = +{ + .configuration = &autonomous_analog_cfg, + .numSttEntries = sizeof(autonomous_analog_stt)/sizeof(autonomous_analog_stt[0U]), + .stateTransitionTable = &autonomous_analog_stt[0U], +}; +cy_en_autanalog_ac_out_trigger_mask_t CYBSP_AUTONOMOUS_CONTROLLER_out_trig_mask[] = +{ + CY_AUTANALOG_AC_OUT_TRIG_MASK_EMPTY, + CY_AUTANALOG_AC_OUT_TRIG_MASK_EMPTY, + CY_AUTANALOG_AC_OUT_TRIG_MASK_EMPTY, + CY_AUTANALOG_AC_OUT_TRIG_MASK_EMPTY, + CY_AUTANALOG_AC_OUT_TRIG_MASK_EMPTY, + CY_AUTANALOG_AC_OUT_TRIG_MASK_EMPTY, + CY_AUTANALOG_AC_OUT_TRIG_MASK_EMPTY, + CY_AUTANALOG_AC_OUT_TRIG_MASK_EMPTY, +}; +cy_stc_autanalog_ac_t CYBSP_AUTONOMOUS_CONTROLLER_cfg = +{ + .gpioOutEn = CY_AUTANALOG_STT_AC_GPIO_OUT_DISABLED, + .mask = + { + &CYBSP_AUTONOMOUS_CONTROLLER_out_trig_mask[0U], + &CYBSP_AUTONOMOUS_CONTROLLER_out_trig_mask[1U], + &CYBSP_AUTONOMOUS_CONTROLLER_out_trig_mask[2U], + &CYBSP_AUTONOMOUS_CONTROLLER_out_trig_mask[3U], + &CYBSP_AUTONOMOUS_CONTROLLER_out_trig_mask[4U], + &CYBSP_AUTONOMOUS_CONTROLLER_out_trig_mask[5U], + &CYBSP_AUTONOMOUS_CONTROLLER_out_trig_mask[6U], + &CYBSP_AUTONOMOUS_CONTROLLER_out_trig_mask[7U], + }, + .timer = + { + .enable = false, + .clkSrc = CY_AUTANALOG_TIMER_CLK_LP, + .period = 0U, + }, +}; +cy_stc_autanalog_stt_ac_t CYBSP_AUTONOMOUS_CONTROLLER_stt[] = +{ + { + .unlock = true, + .lpMode = false, + .condition = CY_AUTANALOG_STT_AC_CONDITION_BLOCK_READY, + .action = CY_AUTANALOG_STT_AC_ACTION_WAIT_FOR, + .branchState = 1U, + .trigInt = false, + .count = 0U, + .unlockGpioOut = false, + .gpioOut = CY_AUTANALOG_STT_AC_GPIO_OUT_DISABLED, + }, + { + .unlock = false, + .lpMode = false, + .condition = CY_AUTANALOG_STT_AC_CONDITION_SAR_DONE, + .action = CY_AUTANALOG_STT_AC_ACTION_WAIT_FOR, + .branchState = 0U, + .trigInt = false, + .count = 0U, + .unlockGpioOut = false, + .gpioOut = CY_AUTANALOG_STT_AC_GPIO_OUT_DISABLED, + }, + { + .unlock = false, + .lpMode = false, + .condition = CY_AUTANALOG_STT_AC_CONDITION_FALSE, + .action = CY_AUTANALOG_STT_AC_ACTION_STOP, + .branchState = 0U, + .trigInt = false, + .count = 0U, + .unlockGpioOut = false, + .gpioOut = CY_AUTANALOG_STT_AC_GPIO_OUT_DISABLED, + }, +}; +cy_stc_autanalog_sar_hs_chan_t CYBSP_SAR_ADC_gpio_ch_cfg[] = +{ + { + .posPin = CY_AUTANALOG_SAR_PIN_GPIO5, + .hsDiffEn = false, + .sign = false, + .posCoeff = CY_AUTANALOG_SAR_CH_COEFF_DISABLED, + .negPin = CY_AUTANALOG_SAR_PIN_GPIO0, + .accShift = false, + .negCoeff = CY_AUTANALOG_SAR_CH_COEFF_DISABLED, + .hsLimit = CY_AUTANALOG_SAR_LIMIT_STATUS_DISABLED, + .fifoSel = CY_AUTANALOG_FIFO_DISABLED, + }, +}; +cy_stc_autanalog_sar_sta_hs_t CYBSP_SAR_ADC_sta_hs_cfg = +{ + .hsVref = CY_AUTANALOG_SAR_VREF_VDDA, + .hsSampleTime = + { + 31U, + 31U, + 31U, + 31U, + }, + .hsGpioChan = + { + &CYBSP_SAR_ADC_gpio_ch_cfg[0U], + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + }, + .hsGpioResultMask = CY_AUTANALOG_SAR_CHAN_MASK_GPIO0, +}; +cy_stc_autanalog_sar_sta_t CYBSP_SAR_ADC_sta_cfg = +{ + .lpStaCfg = NULL, + .hsStaCfg = &CYBSP_SAR_ADC_sta_hs_cfg, + .posBufPwr = CY_AUTANALOG_SAR_BUF_PWR_OFF, + .negBufPwr = CY_AUTANALOG_SAR_BUF_PWR_OFF, + .accMode = CY_AUTANALOG_SAR_ACC_DISABLED, + .startupCal = CY_AUTANALOG_SAR_CAL_DISABLED, + .chanID = false, + .shiftMode = false, + .intMuxChan = + { + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + }, + .limitCond = + { + NULL, + NULL, + NULL, + NULL, + }, + .muxResultMask = CY_AUTANALOG_SAR_CHAN_MASK_MUX_DISABLED, + .firResultMask = CY_AUTANALOG_SAR_MASK_FIR_DISABLED, +}; +cy_stc_autanalog_sar_seq_tab_hs_t CYBSP_SAR_ADC_seq_hs_cfg[] = +{ + { + .chanEn = CY_AUTANALOG_SAR_CHAN_MASK_GPIO0, + .muxMode = CY_AUTANALOG_SAR_CHAN_CFG_MUX_DISABLED, + .mux0Sel = CY_AUTANALOG_SAR_CHAN_CFG_MUX0, + .mux1Sel = CY_AUTANALOG_SAR_CHAN_CFG_MUX0, + .sampleTimeEn = true, + .sampleTime = CY_AUTANALOG_SAR_SAMPLE_TIME0, + .accEn = false, + .accCount = CY_AUTANALOG_SAR_ACC_CNT2, + .calReq = CY_AUTANALOG_SAR_CAL_DISABLED, + .nextAction = CY_AUTANALOG_SAR_NEXT_ACTION_GO_TO_ENTRY_ADDR, + }, +}; +cy_stc_autanalog_sar_t CYBSP_SAR_ADC_cfg = +{ + .sarStaCfg = &CYBSP_SAR_ADC_sta_cfg, + .hsSeqTabNum = sizeof(CYBSP_SAR_ADC_seq_hs_cfg)/sizeof(CYBSP_SAR_ADC_seq_hs_cfg[0U]), + .hsSeqTabArr = &CYBSP_SAR_ADC_seq_hs_cfg[0U], + .lpSeqTabNum = 0U, + .lpSeqTabArr = NULL, + .firNum = 0U, + .firCfg = NULL, + .fifoCfg = NULL, +}; +cy_stc_autanalog_stt_sar_t CYBSP_SAR_ADC_stt[] = +{ + { + .unlock = true, + .enable = true, + .trigger = false, + .entryState = 0U, + }, + { + .unlock = true, + .enable = true, + .trigger = true, + .entryState = 0U, + }, + { + .unlock = true, + .enable = true, + .trigger = false, + .entryState = 0U, + }, +}; + +#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_ADC) +mtb_hal_adc_configurator_t CYBSP_SAR_ADC_hal_config = +{ + .config = &CYBSP_SAR_ADC_cfg, + .num_channels = sizeof(CYBSP_SAR_ADC_seq_hs_cfg)/sizeof(CYBSP_SAR_ADC_seq_hs_cfg[0U]), + .clock = NULL, + .adc_index = 0U, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_ADC) */ + +cy_stc_gfx_layer_config_t GFXSS_graphics_layer = +{ + .layer_type = GFX_LAYER_GRAPHICS, + .buffer_address = (gctADDRESS *)CY_SOCMEM_RAM_BASE, + .uv_buffer_address = (gctADDRESS *)CY_SOCMEM_RAM_BASE, + .input_format_type = vivRGB565, + .tiling_type = vivLINEAR, + .pos_x = 0, + .pos_y = 0, + .width = 512, + .height = 768, + .zorder = 0, + .layer_enable = true, + .visibility = true, +}; +cy_stc_gfx_layer_config_t GFXSS_overlay0_layer = +{ + .layer_type = GFX_LAYER_OVERLAY0, + .buffer_address = (gctADDRESS *)CY_SOCMEM_RAM_BASE, + .uv_buffer_address = (gctADDRESS *)CY_SOCMEM_RAM_BASE, + .input_format_type = vivRGB565, + .tiling_type = vivLINEAR, + .pos_x = 0, + .pos_y = 0, + .width = 1, + .height = 1, + .zorder = 0, + .layer_enable = false, + .visibility = false, +}; +cy_stc_gfx_layer_config_t GFXSS_overlay1_layer = +{ + .layer_type = GFX_LAYER_OVERLAY1, + .buffer_address = (gctADDRESS *)CY_SOCMEM_RAM_BASE, + .uv_buffer_address = (gctADDRESS *)CY_SOCMEM_RAM_BASE, + .input_format_type = vivRGB565, + .tiling_type = vivLINEAR, + .pos_x = 0, + .pos_y = 0, + .width = 1, + .height = 1, + .zorder = 0, + .layer_enable = false, + .visibility = false, +}; +cy_stc_gfx_dc_config_t GFXSS_dc_config = +{ + .gfx_layer_config = &GFXSS_graphics_layer, + .ovl0_layer_config = &GFXSS_overlay0_layer, + .ovl1_layer_config = &GFXSS_overlay1_layer, + .display_type = GFX_DISP_TYPE_DSI_DPI, + .display_format = vivD24, + .display_size = vivDISPLAY_CUSTOMIZED, + .display_width = 512, + .display_height = 768, +}; +cy_stc_gfx_gpu_cfg_t GFXSS_gpu_config = +{ + .enable = true, +}; +cy_stc_mipidsi_display_params_t GFXSS_mipidsi_display_params = +{ + .pixel_clock = 27212, + .hdisplay = 512, + .hsync_width = 10, + .hfp = 20, + .hbp = 20, + .vdisplay = 768, + .vsync_width = 30, + .vfp = 4, + .vbp = 5, + .polarity_flags = 0, +}; +cy_stc_mipidsi_config_t GFXSS_mipi_dsi_config = +{ + .virtual_ch = 0, + .num_of_lanes = 2, + .per_lane_mbps = 500, + .dpi_fmt = CY_MIPIDSI_FMT_RGB888, + .dsi_mode = DSI_VIDEO_MODE, + .max_phy_clk = 2500000000, + .mode_flags = VID_MODE_TYPE_NON_BURST_SYNC_PULSES | ENABLE_LOW_POWER_CMD | ENABLE_LOW_POWER, + .display_params = &GFXSS_mipidsi_display_params, +}; +cy_stc_gfx_config_t GFXSS_config = +{ + .dc_cfg = &GFXSS_dc_config, + .gpu_cfg = &GFXSS_gpu_config, + .mipi_dsi_cfg = &GFXSS_mipi_dsi_config, + .display_update_type = GFX_DOUBLE_BUFFER, + .clockHz = 399999999U, +}; +const cy_stc_i3c_config_t CYBSP_I3C_CONTROLLER_config = +{ + .i3cMode = CY_I3C_CONTROLLER, + .i3cBusMode = CY_I3C_BUS_PURE, + .useDma = false, + .manualDataRate = false, + .i3cClockHz = 12500000U, + .i3cSclRate = 12500000U, + .openDrainSclRate = 4000000U, + .txEmptyBufThld = CY_I3C_1_WORD_DEPTH, + .rxBufThld = CY_I3C_1_WORD_DEPTH, + .txBufStartThld = CY_I3C_1_WORD_DEPTH, + .rxBufStartThld = CY_I3C_1_WORD_DEPTH, + .ibaInclude = false, + .hotJoinCtrl = false, + .dynamicAddr = 8U, + .cmdQueueEmptyThld = 1U, + .respQueueThld = 0U, + .ibiQueueThld = 0U, + .ibiDataThld = 15U, + .extLowCnt1 = 11U, + .extLowCnt2 = 16U, + .extLowCnt3 = 27U, + .extLowCnt4 = 58U, + .extTerminationLowCnt = 0U, + .sdaHoldTime = 1U, + .busFreeTime = 32U, + .openDrainLowCnt = 0U, + .openDrainHighCnt = 0U, + .pushPullLowCnt = 0U, + .pushPullHighCnt = 0U, + .i2cFMLowCnt = 0U, + .i2cFMHighCnt = 0U, + .i2cFMPlusLowCnt = 0U, + .i2cFMPlusHighCnt = 0U, + .adaptiveI2CI3C = false, + .staticAddress = 0U, + .pid = 0U, + .dcr = 0U, + .speedLimit = false, + .hdrCapable = false, + .deviceRoleCap = CY_I3C_SECONDARY_CONTROLLER, + .hotjoinEnable = false, + .busAvailTime = 0U, + .busIdleTime = 0U, +}; +const cy_stc_pdm_pcm_config_v2_t CYBSP_PDM_config = +{ + .clkDiv = 7, + .clksel = CY_PDM_PCM_SEL_SRSS_CLOCK, + .halverate = CY_PDM_PCM_RATE_FULL, + .route = 4, + .fir0_coeff_user_value = false, + .fir1_coeff_user_value = false, +}; +const cy_stc_pdm_pcm_channel_config_t channel_2_config = +{ + .sampledelay = 1, + .wordSize = CY_PDM_PCM_WSIZE_16_BIT, + .signExtension = true, + .rxFifoTriggerLevel = 31, + .fir0_enable = false, + .cic_decim_code = CY_PDM_PCM_CHAN_CIC_DECIM_32, + .fir0_decim_code = CY_PDM_PCM_CHAN_FIR0_DECIM_1, + .fir0_scale = 0, + .fir1_decim_code = CY_PDM_PCM_CHAN_FIR1_DECIM_3, + .fir1_scale = 10, + .dc_block_disable = false, + .dc_block_code = CY_PDM_PCM_CHAN_DCBLOCK_CODE_16, +}; +const cy_stc_pdm_pcm_channel_config_t channel_3_config = +{ + .sampledelay = 5, + .wordSize = CY_PDM_PCM_WSIZE_16_BIT, + .signExtension = true, + .rxFifoTriggerLevel = 31, + .fir0_enable = false, + .cic_decim_code = CY_PDM_PCM_CHAN_CIC_DECIM_32, + .fir0_decim_code = CY_PDM_PCM_CHAN_FIR0_DECIM_1, + .fir0_scale = 0, + .fir1_decim_code = CY_PDM_PCM_CHAN_FIR1_DECIM_3, + .fir1_scale = 10, + .dc_block_disable = false, + .dc_block_code = CY_PDM_PCM_CHAN_DCBLOCK_CODE_16, +}; +const cy_stc_scb_i2c_config_t CYBSP_I2C_CONTROLLER_config = +{ + .i2cMode = CY_SCB_I2C_MASTER, + .useRxFifo = true, + .useTxFifo = true, + .slaveAddress = 0U, + .slaveAddressMask = 0U, + .acceptAddrInFifo = false, + .ackGeneralAddr = false, + .enableWakeFromSleep = false, + .enableDigitalFilter = false, + .lowPhaseDutyCycle = 16, + .highPhaseDutyCycle = 9, +}; + +#if defined (COMPONENT_MTB_HAL) +const mtb_hal_peri_div_t CYBSP_I2C_CONTROLLER_clock_ref = +{ + .clk_dst = (en_clk_dst_t)CYBSP_I2C_CONTROLLER_CLK_DIV_GRP_NUM, + .div_type = CYBSP_I2C_CONTROLLER_CLK_DIV_HW, + .div_num = CYBSP_I2C_CONTROLLER_CLK_DIV_NUM, +}; +const mtb_hal_clock_t CYBSP_I2C_CONTROLLER_hal_clock = +{ + .clock_ref = &CYBSP_I2C_CONTROLLER_clock_ref, + .interface = &mtb_hal_clock_peri_interface, +}; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_I2C) +const mtb_hal_i2c_configurator_t CYBSP_I2C_CONTROLLER_hal_config = +{ + .base = CYBSP_I2C_CONTROLLER_HW, + .config = &CYBSP_I2C_CONTROLLER_config, + .clock = &CYBSP_I2C_CONTROLLER_hal_clock, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_I2C) */ + +const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config = +{ + .uartMode = CY_SCB_UART_STANDARD, + .enableMultiProcessorMode = false, + .smartCardRetryOnNack = false, + .irdaInvertRx = false, + .irdaEnableLowPowerReceiver = false, + .oversample = 10, + .enableMsbFirst = false, + .dataWidth = 8UL, + .parity = CY_SCB_UART_PARITY_NONE, + .stopBits = CY_SCB_UART_STOP_BITS_1, + .enableInputFilter = false, + .breakWidth = 11UL, + .dropOnFrameError = false, + .dropOnParityError = false, + .breaklevel = false, + .receiverAddress = 0x0UL, + .receiverAddressMask = 0x0UL, + .acceptAddrInFifo = false, + .enableCts = false, + .ctsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rtsRxFifoLevel = 0UL, + .rtsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rxFifoTriggerLevel = 63UL, + .rxFifoIntEnableMask = 0UL, + .txFifoTriggerLevel = 63UL, + .txFifoIntEnableMask = 0UL, +}; + +#if defined (COMPONENT_MTB_HAL) +const mtb_hal_peri_div_t CYBSP_DEBUG_UART_clock_ref = +{ + .clk_dst = (en_clk_dst_t)CYBSP_DEBUG_UART_CLK_DIV_GRP_NUM, + .div_type = CYBSP_DEBUG_UART_CLK_DIV_HW, + .div_num = CYBSP_DEBUG_UART_CLK_DIV_NUM, +}; +const mtb_hal_clock_t CYBSP_DEBUG_UART_hal_clock = +{ + .clock_ref = &CYBSP_DEBUG_UART_clock_ref, + .interface = &mtb_hal_clock_peri_interface, +}; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_UART) +const mtb_hal_uart_configurator_t CYBSP_DEBUG_UART_hal_config = +{ + .base = CYBSP_DEBUG_UART_HW, + .clock = &CYBSP_DEBUG_UART_hal_clock, + .tx_pin = 7, +#if defined (COMPONENT_MW_ASYNC_TRANSFER) + .rts_pin = 0xFF, +#endif /* defined (COMPONENT_MW_ASYNC_TRANSFER) */ + .tx_port = 6, +#if defined (COMPONENT_MW_ASYNC_TRANSFER) + .rts_port = 0xFF, + .rts_enable = 0UL, +#endif /* defined (COMPONENT_MW_ASYNC_TRANSFER) */ +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_UART) */ + +const cy_stc_scb_uart_config_t CYBSP_BT_UART_config = +{ + .uartMode = CY_SCB_UART_STANDARD, + .enableMultiProcessorMode = false, + .smartCardRetryOnNack = false, + .irdaInvertRx = false, + .irdaEnableLowPowerReceiver = false, + .oversample = 8, + .enableMsbFirst = false, + .dataWidth = 8UL, + .parity = CY_SCB_UART_PARITY_NONE, + .stopBits = CY_SCB_UART_STOP_BITS_1, + .enableInputFilter = false, + .breakWidth = 11UL, + .dropOnFrameError = false, + .dropOnParityError = false, + .breaklevel = false, + .receiverAddress = 0x0UL, + .receiverAddressMask = 0x0UL, + .acceptAddrInFifo = false, + .enableCts = true, + .ctsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rtsRxFifoLevel = 63, + .rtsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rxFifoTriggerLevel = 63UL, + .rxFifoIntEnableMask = 0UL, + .txFifoTriggerLevel = 63UL, + .txFifoIntEnableMask = 0UL, +}; + +#if defined (COMPONENT_MTB_HAL) +const mtb_hal_peri_div_t CYBSP_BT_UART_clock_ref = +{ + .clk_dst = (en_clk_dst_t)CYBSP_BT_UART_CLK_DIV_GRP_NUM, + .div_type = CYBSP_BT_UART_CLK_DIV_HW, + .div_num = CYBSP_BT_UART_CLK_DIV_NUM, +}; +const mtb_hal_clock_t CYBSP_BT_UART_hal_clock = +{ + .clock_ref = &CYBSP_BT_UART_clock_ref, + .interface = &mtb_hal_clock_peri_interface, +}; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_UART) +const mtb_hal_uart_configurator_t CYBSP_BT_UART_hal_config = +{ + .base = CYBSP_BT_UART_HW, + .clock = &CYBSP_BT_UART_hal_clock, + .tx_pin = 1, +#if defined (COMPONENT_MW_ASYNC_TRANSFER) + .rts_pin = 3, +#endif /* defined (COMPONENT_MW_ASYNC_TRANSFER) */ + .tx_port = 10, +#if defined (COMPONENT_MW_ASYNC_TRANSFER) + .rts_port = 10, + .rts_enable = 1UL, +#endif /* defined (COMPONENT_MW_ASYNC_TRANSFER) */ +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_UART) */ + +const cy_stc_scb_uart_config_t CYBSP_UART5_config = +{ + .uartMode = CY_SCB_UART_STANDARD, + .enableMultiProcessorMode = false, + .smartCardRetryOnNack = false, + .irdaInvertRx = false, + .irdaEnableLowPowerReceiver = false, + .oversample = 10, + .enableMsbFirst = false, + .dataWidth = 8UL, + .parity = CY_SCB_UART_PARITY_NONE, + .stopBits = CY_SCB_UART_STOP_BITS_1, + .enableInputFilter = false, + .breakWidth = 11UL, + .dropOnFrameError = false, + .dropOnParityError = false, + .breaklevel = false, + .receiverAddress = 0x0UL, + .receiverAddressMask = 0x0UL, + .acceptAddrInFifo = false, + .enableCts = false, + .ctsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rtsRxFifoLevel = 0UL, + .rtsPolarity = CY_SCB_UART_ACTIVE_LOW, + .rxFifoTriggerLevel = 63UL, + .rxFifoIntEnableMask = 0UL, + .txFifoTriggerLevel = 63UL, + .txFifoIntEnableMask = 0UL, +}; + +#if defined (COMPONENT_MTB_HAL) +const mtb_hal_peri_div_t CYBSP_UART5_clock_ref = +{ + .clk_dst = (en_clk_dst_t)CYBSP_EZ_I2C_TARGET_CLK_DIV_GRP_NUM, + .div_type = CYBSP_EZ_I2C_TARGET_CLK_DIV_HW, + .div_num = CYBSP_EZ_I2C_TARGET_CLK_DIV_NUM, +}; +const mtb_hal_clock_t CYBSP_UART5_hal_clock = +{ + .clock_ref = &CYBSP_UART5_clock_ref, + .interface = &mtb_hal_clock_peri_interface, +}; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_UART) +const mtb_hal_uart_configurator_t CYBSP_UART5_hal_config = +{ + .base = CYBSP_UART5_HW, + .clock = &CYBSP_UART5_hal_clock, + .tx_pin = 1, +#if defined (COMPONENT_MW_ASYNC_TRANSFER) + .rts_pin = 0xFF, +#endif /* defined (COMPONENT_MW_ASYNC_TRANSFER) */ + .tx_port = 17, +#if defined (COMPONENT_MW_ASYNC_TRANSFER) + .rts_port = 0xFF, + .rts_enable = 0UL, +#endif /* defined (COMPONENT_MW_ASYNC_TRANSFER) */ +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_UART) */ + +const cy_stc_scb_spi_config_t CYBSP_SPI_9_config = +{ + .spiMode = CY_SCB_SPI_MASTER, + .subMode = CY_SCB_SPI_MOTOROLA, + .sclkMode = CY_SCB_SPI_CPHA0_CPOL0, + .parity = CY_SCB_SPI_PARITY_NONE, + .dropOnParityError = false, + .oversample = 10, + .rxDataWidth = 8UL, + .txDataWidth = 8UL, + .enableMsbFirst = true, + .enableInputFilter = false, + .enableFreeRunSclk = false, + .enableMisoLateSample = true, + .enableTransferSeparation = false, + .ssPolarity = ((CY_SCB_SPI_ACTIVE_LOW << CY_SCB_SPI_SLAVE_SELECT0) | \ + (CY_SCB_SPI_ACTIVE_LOW << CY_SCB_SPI_SLAVE_SELECT1) | \ + (CY_SCB_SPI_ACTIVE_LOW << CY_SCB_SPI_SLAVE_SELECT2) | \ + (CY_SCB_SPI_ACTIVE_LOW << CY_SCB_SPI_SLAVE_SELECT3)), + .ssSetupDelay = false, + .ssHoldDelay = false, + .ssInterFrameDelay = false, + .enableWakeFromSleep = false, + .rxFifoTriggerLevel = 63UL, + .rxFifoIntEnableMask = 0UL, + .txFifoTriggerLevel = 63UL, + .txFifoIntEnableMask = 0UL, + .masterSlaveIntEnableMask = 0UL, +}; + +#if defined (COMPONENT_MTB_HAL) +const mtb_hal_peri_div_t CYBSP_SPI_9_clock_ref = +{ + .clk_dst = (en_clk_dst_t)PCLK_SCB9_CLOCK_SCB_EN, + .div_type = CY_SYSCLK_DIV_8_BIT, + .div_num = 1, +}; +const mtb_hal_clock_t CYBSP_SPI_9_hal_clock = +{ + .clock_ref = &CYBSP_SPI_9_clock_ref, + .interface = &mtb_hal_clock_peri_interface, +}; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SPI) +const mtb_hal_spi_configurator_t CYBSP_SPI_9_hal_config = +{ + .base = CYBSP_SPI_9_HW, + .clock = &CYBSP_SPI_9_hal_clock, + .config = &CYBSP_SPI_9_config, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SPI) */ + +cy_en_sd_host_card_capacity_t CYBSP_SDHC_0_cardCapacity = CY_SD_HOST_SDSC; +cy_en_sd_host_card_type_t CYBSP_SDHC_0_cardType = CY_SD_HOST_NOT_EMMC; +uint32_t CYBSP_SDHC_0_rca = 0u; +const cy_stc_sd_host_init_config_t CYBSP_SDHC_0_config = +{ + .emmc = false, + .dmaType = CY_SD_HOST_DMA_ADMA2, + .enableLedControl = false, +}; +cy_stc_sd_host_sd_card_config_t CYBSP_SDHC_0_card_cfg = +{ + .lowVoltageSignaling = false, + .busWidth = CY_SD_HOST_BUS_WIDTH_4_BIT, + .cardType = &CYBSP_SDHC_0_cardType, + .rca = &CYBSP_SDHC_0_rca, + .cardCapacity = &CYBSP_SDHC_0_cardCapacity, +}; + +#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SDHC) +const mtb_hal_peri_div_t CYBSP_SDHC_0_clock_ref = +{ + .clk_dst = (en_clk_dst_t)CYBSP_SDHC_0_CLK_DIV_GRP_NUM, + .div_type = CYBSP_SDHC_0_CLK_DIV_HW, + .div_num = CYBSP_SDHC_0_CLK_DIV_NUM, +}; +const mtb_hal_clock_t CYBSP_SDHC_0_hal_clock = +{ + .clock_ref = &CYBSP_SDHC_0_clock_ref, + .interface = &mtb_hal_clock_peri_interface, +}; +const mtb_hal_sdhc_configurator_t CYBSP_SDHC_0_sdhc_hal_config = +{ + .base = CYBSP_SDHC_0_HW, + .host_config = &CYBSP_SDHC_0_config, + .card_config = &CYBSP_SDHC_0_card_cfg, + .clock = &CYBSP_SDHC_0_hal_clock, + .gpios = {.clk = { .pin_num = 0, .port_num = 12}, .cmd = { .pin_num = 0, .port_num = 21}, .data = {{ .pin_num = 1, .port_num = 12}, { .pin_num = 2, .port_num = 12}, { .pin_num = 4, .port_num = 12}, { .pin_num = 5, .port_num = 12}, { .pin_num = NC, .port_num = NC}, { .pin_num = NC, .port_num = NC}, { .pin_num = NC, .port_num = NC}, { .pin_num = NC, .port_num = NC}}}, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SDHC) */ + +#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SDIO) +const mtb_hal_sdio_configurator_t CYBSP_SDHC_0_sdio_hal_config = +{ + .base = CYBSP_SDHC_0_HW, + .host_config = &CYBSP_SDHC_0_config, + .clock = &CYBSP_SDHC_0_hal_clock, + .gpios = {.clk = { .pin_num = 0, .port_num = 12}, .cmd = { .pin_num = 0, .port_num = 21}, .data = {{ .pin_num = 1, .port_num = 12}, { .pin_num = 2, .port_num = 12}, { .pin_num = 4, .port_num = 12}, { .pin_num = 5, .port_num = 12}}}, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SDIO) */ + +cy_en_sd_host_card_capacity_t CYBSP_SDHC_1_cardCapacity = CY_SD_HOST_SDSC; +cy_en_sd_host_card_type_t CYBSP_SDHC_1_cardType = CY_SD_HOST_NOT_EMMC; +uint32_t CYBSP_SDHC_1_rca = 0u; +const cy_stc_sd_host_init_config_t CYBSP_SDHC_1_config = +{ + .emmc = false, + .dmaType = CY_SD_HOST_DMA_ADMA2, + .enableLedControl = false, +}; +cy_stc_sd_host_sd_card_config_t CYBSP_SDHC_1_card_cfg = +{ + .lowVoltageSignaling = false, + .busWidth = CY_SD_HOST_BUS_WIDTH_4_BIT, + .cardType = &CYBSP_SDHC_1_cardType, + .rca = &CYBSP_SDHC_1_rca, + .cardCapacity = &CYBSP_SDHC_1_cardCapacity, +}; + +#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SDHC) +const mtb_hal_peri_div_t CYBSP_SDHC_1_clock_ref = +{ + .clk_dst = (en_clk_dst_t)CYBSP_SDHC_1_CLK_DIV_GRP_NUM, + .div_type = CYBSP_SDHC_1_CLK_DIV_HW, + .div_num = CYBSP_SDHC_1_CLK_DIV_NUM, +}; +const mtb_hal_clock_t CYBSP_SDHC_1_hal_clock = +{ + .clock_ref = &CYBSP_SDHC_1_clock_ref, + .interface = &mtb_hal_clock_peri_interface, +}; +const mtb_hal_sdhc_configurator_t CYBSP_SDHC_1_sdhc_hal_config = +{ + .base = CYBSP_SDHC_1_HW, + .host_config = &CYBSP_SDHC_1_config, + .card_config = &CYBSP_SDHC_1_card_cfg, + .clock = &CYBSP_SDHC_1_hal_clock, + .gpios = {.clk = { .pin_num = 1, .port_num = 7}, .cmd = { .pin_num = 0, .port_num = 7}, .data = {{ .pin_num = 3, .port_num = 7}, { .pin_num = 5, .port_num = 7}, { .pin_num = 6, .port_num = 7}, { .pin_num = 7, .port_num = 7}, { .pin_num = NC, .port_num = NC}, { .pin_num = NC, .port_num = NC}, { .pin_num = NC, .port_num = NC}, { .pin_num = NC, .port_num = NC}}}, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SDHC) */ + +#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SDIO) +const mtb_hal_sdio_configurator_t CYBSP_SDHC_1_sdio_hal_config = +{ + .base = CYBSP_SDHC_1_HW, + .host_config = &CYBSP_SDHC_1_config, + .clock = &CYBSP_SDHC_1_hal_clock, + .gpios = {.clk = { .pin_num = 1, .port_num = 7}, .cmd = { .pin_num = 0, .port_num = 7}, .data = {{ .pin_num = 3, .port_num = 7}, { .pin_num = 5, .port_num = 7}, { .pin_num = 6, .port_num = 7}, { .pin_num = 7, .port_num = 7}}}, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SDIO) */ + +void canfd0_rx_callback(bool rxFIFOMsg, uint8_t msgBufOrRxFIFONum, cy_stc_canfd_rx_buffer_t* basemsg); +const cy_stc_canfd_bitrate_t CYBSP_CAN_FD_CH_0_nominalBitrateConfig = +{ + .prescaler = 1U - 1U, + .timeSegment1 = 59U - 1U, + .timeSegment2 = 20U - 1U, + .syncJumpWidth = 1U - 1U, +}; +const cy_stc_canfd_bitrate_t CYBSP_CAN_FD_CH_0_dataBitrateConfig = +{ + .prescaler = 1U - 1U, + .timeSegment1 = 29U - 1U, + .timeSegment2 = 10U - 1U, + .syncJumpWidth = 1U - 1U, +}; +const cy_stc_canfd_transceiver_delay_compensation_t CYBSP_CAN_FD_CH_0_tdcConfig = +{ + .tdcEnabled = false, + .tdcOffset = 0U, + .tdcFilterWindow = 0U, +}; +const cy_stc_id_filter_t CYBSP_CAN_FD_CH_0_stdIdFilter_0 = +{ + .sfid2 = 0xFFU, + .sfid1 = 0x10U, + .sfec = CY_CANFD_SFEC_DISABLE, + .sft = CY_CANFD_SFT_RANGE_SFID1_SFID2, +}; +const cy_stc_id_filter_t CYBSP_CAN_FD_CH_0_stdIdFilters[] = +{ + [0] = CYBSP_CAN_FD_CH_0_STD_ID_FILTER_0, +}; +const cy_stc_canfd_sid_filter_config_t CYBSP_CAN_FD_CH_0_sidFiltersConfig = +{ + .numberOfSIDFilters = 1U, + .sidFilter = CYBSP_CAN_FD_CH_0_stdIdFilters, +}; +const cy_stc_canfd_f0_t CYBSP_CAN_FD_CH_0_extIdFilterF0Config_0 = +{ + .efid1 = 0U, + .efec = CY_CANFD_EFEC_DISABLE, +}; +const cy_stc_canfd_f1_t CYBSP_CAN_FD_CH_0_extIdFilterF1Config_0 = +{ + .efid2 = 0U, + .eft = CY_CANFD_EFT_RANGE_EFID1_EFID2, +}; +const cy_stc_extid_filter_t CYBSP_CAN_FD_CH_0_extIdFilter_0 = +{ + .f0_f = &CYBSP_CAN_FD_CH_0_extIdFilterF0Config_0, + .f1_f = &CYBSP_CAN_FD_CH_0_extIdFilterF1Config_0, +}; +const cy_stc_extid_filter_t CYBSP_CAN_FD_CH_0_extIdFilters[] = +{ + [0] = CYBSP_CAN_FD_CH_0_EXT_ID_FILTER_0, +}; +const cy_stc_canfd_extid_filter_config_t CYBSP_CAN_FD_CH_0_extIdFiltersConfig = +{ + .numberOfEXTIDFilters = 1U, + .extidFilter = (cy_stc_extid_filter_t*)&CYBSP_CAN_FD_CH_0_extIdFilters, + .extIDANDMask = 536870911UL, +}; +const cy_stc_canfd_global_filter_config_t CYBSP_CAN_FD_CH_0_globalFilterConfig = +{ + .nonMatchingFramesStandard = CY_CANFD_ACCEPT_IN_RXFIFO_0, + .nonMatchingFramesExtended = CY_CANFD_ACCEPT_IN_RXFIFO_0, + .rejectRemoteFramesStandard = false, + .rejectRemoteFramesExtended = false, +}; +const cy_en_canfd_fifo_config_t CYBSP_CAN_FD_CH_0_rxFifo0Config = +{ + .mode = CY_CANFD_FIFO_MODE_BLOCKING, + .watermark = 0U, + .numberOfFIFOElements = 8U, + .topPointerLogicEnabled = false, +}; +const cy_en_canfd_fifo_config_t CYBSP_CAN_FD_CH_0_rxFifo1Config = +{ + .mode = CY_CANFD_FIFO_MODE_BLOCKING, + .watermark = 0U, + .numberOfFIFOElements = 8U, + .topPointerLogicEnabled = false, +}; +const cy_stc_canfd_config_t CYBSP_CAN_FD_CH_0_config = +{ + .txCallback = NULL, + .rxCallback = canfd0_rx_callback, + .errorCallback = NULL, + .canFDMode = true, + .bitrate = &CYBSP_CAN_FD_CH_0_nominalBitrateConfig, + .fastBitrate = &CYBSP_CAN_FD_CH_0_dataBitrateConfig, + .tdcConfig = &CYBSP_CAN_FD_CH_0_tdcConfig, + .sidFilterConfig = &CYBSP_CAN_FD_CH_0_sidFiltersConfig, + .extidFilterConfig = &CYBSP_CAN_FD_CH_0_extIdFiltersConfig, + .globalFilterConfig = &CYBSP_CAN_FD_CH_0_globalFilterConfig, + .rxBufferDataSize = CY_CANFD_BUFFER_DATA_SIZE_8, + .rxFIFO1DataSize = CY_CANFD_BUFFER_DATA_SIZE_8, + .rxFIFO0DataSize = CY_CANFD_BUFFER_DATA_SIZE_8, + .txBufferDataSize = CY_CANFD_BUFFER_DATA_SIZE_8, + .rxFIFO0Config = &CYBSP_CAN_FD_CH_0_rxFifo0Config, + .rxFIFO1Config = &CYBSP_CAN_FD_CH_0_rxFifo1Config, + .noOfRxBuffers = 4U, + .noOfTxBuffers = 2U, + .messageRAMaddress = CY_CAN0MRAM_BASE + 0U, + .messageRAMsize = 8192U, +}; +cy_stc_canfd_t0_t CYBSP_CAN_FD_CH_0_T0RegisterBuffer_0 = +{ + .id = 0x22U, + .rtr = CY_CANFD_RTR_DATA_FRAME, + .xtd = CY_CANFD_XTD_STANDARD_ID, + .esi = CY_CANFD_ESI_ERROR_ACTIVE, +}; +cy_stc_canfd_t0_t CYBSP_CAN_FD_CH_0_T0RegisterBuffer_1 = +{ + .id = 0U, + .rtr = CY_CANFD_RTR_DATA_FRAME, + .xtd = CY_CANFD_XTD_STANDARD_ID, + .esi = CY_CANFD_ESI_ERROR_ACTIVE, +}; +cy_stc_canfd_t1_t CYBSP_CAN_FD_CH_0_T1RegisterBuffer_0 = +{ + .dlc = 8U, + .brs = true, + .fdf = CY_CANFD_FDF_CAN_FD_FRAME, + .efc = false, + .mm = 0U, +}; +cy_stc_canfd_t1_t CYBSP_CAN_FD_CH_0_T1RegisterBuffer_1 = +{ + .dlc = 0U, + .brs = false, + .fdf = CY_CANFD_FDF_STANDARD_FRAME, + .efc = false, + .mm = 0U, +}; +uint32_t CYBSP_CAN_FD_CH_0_dataBuffer_0[] = +{ + [CYBSP_CAN_FD_CH_0_DATA_0] = 0x04030201U, + [CYBSP_CAN_FD_CH_0_DATA_1] = 0x08070605U, +}; +uint32_t CYBSP_CAN_FD_CH_0_dataBuffer_1[] = +{ + [CYBSP_CAN_FD_CH_0_DATA_0] = 0U, + [CYBSP_CAN_FD_CH_0_DATA_1] = 0U, +}; +cy_stc_canfd_tx_buffer_t CYBSP_CAN_FD_CH_0_txBuffer_0 = +{ + .t0_f = &CYBSP_CAN_FD_CH_0_T0RegisterBuffer_0, + .t1_f = &CYBSP_CAN_FD_CH_0_T1RegisterBuffer_0, + .data_area_f = CYBSP_CAN_FD_CH_0_dataBuffer_0, +}; +cy_stc_canfd_tx_buffer_t CYBSP_CAN_FD_CH_0_txBuffer_1 = +{ + .t0_f = &CYBSP_CAN_FD_CH_0_T0RegisterBuffer_1, + .t1_f = &CYBSP_CAN_FD_CH_0_T1RegisterBuffer_1, + .data_area_f = CYBSP_CAN_FD_CH_0_dataBuffer_1, +}; +const cy_stc_smif_config_t CYBSP_SMIF_CORE_0_XSPI_FLASH_config = +{ + .mode = (uint32_t)CY_SMIF_NORMAL, + .deselectDelay = CYBSP_SMIF_CORE_0_XSPI_FLASH_DESELECT_DELAY, + .blockEvent = (uint32_t)CY_SMIF_BUS_ERROR, + .inputFrequencyMHz = 200, + .enable_internal_dll = false, + .dll_divider_value = CY_SMIF_DLL_DIVIDE_BY_2, + .rx_capture_mode = CY_SMIF_SEL_NORMAL_SPI, + .mdl_tap = CY_SMIF_MDL_8_TAP_DELAY, + .device0_sdl_tap = CY_SMIF_SDL_8_TAP_DELAY, + .device1_sdl_tap = CY_SMIF_SDL_8_TAP_DELAY, + .device2_sdl_tap = CY_SMIF_SDL_8_TAP_DELAY, + .device3_sdl_tap = CY_SMIF_SDL_8_TAP_DELAY, + .tx_sdr_extra = CY_SMIF_TX_TWO_PERIOD_AHEAD, +}; + +#if defined (COMPONENT_MTB_HAL) +const mtb_hal_hf_clock_t CYBSP_SMIF_CORE_0_XSPI_FLASH_clock_ref = +{ + .inst_num = 3U, +}; +const mtb_hal_clock_t CYBSP_SMIF_CORE_0_XSPI_FLASH_hal_clock = +{ + .clock_ref = &CYBSP_SMIF_CORE_0_XSPI_FLASH_clock_ref, + .interface = &mtb_hal_clock_hf_interface, +}; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_MEMORYSPI) +const mtb_hal_memoryspi_configurator_t CYBSP_SMIF_CORE_0_XSPI_FLASH_hal_config = +{ + .base = SMIF0_CORE, + .clock = &CYBSP_SMIF_CORE_0_XSPI_FLASH_hal_clock, + .config = &CYBSP_SMIF_CORE_0_XSPI_FLASH_config, + .csel = {false, true, false, false}, + .irqs = CYBSP_SMIF_CORE_0_XSPI_FLASH_MEMORY_MODE_ALIGMENT_ERROR << 5 | CYBSP_SMIF_CORE_0_XSPI_FLASH_RX_DATA_FIFO_UNDERFLOW << 4 | CYBSP_SMIF_CORE_0_XSPI_FLASH_TX_COMMAND_FIFO_OVERFLOW << 3 | CYBSP_SMIF_CORE_0_XSPI_FLASH_TX_DATA_FIFO_OVERFLOW << 2 | (uint8_t)(CYBSP_SMIF_CORE_0_XSPI_FLASH_RX_FIFO_TRIGGER_LEVEL != 0) << 1 | (uint8_t)(CYBSP_SMIF_CORE_0_XSPI_FLASH_TX_FIFO_TRIGGER_LEVEL != 0) << 0, + .dmas = CYBSP_SMIF_CORE_0_XSPI_FLASH_RX_DMA_TRIGGER_OUT_USED << 1 | CYBSP_SMIF_CORE_0_XSPI_FLASH_TX_DMA_TRIGGER_OUT_USED << 0, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_MEMORYSPI) */ + +const cy_stc_smif_config_t CYBSP_SMIF_CORE_1_PSRAM_config = +{ + .mode = (uint32_t)CY_SMIF_NORMAL, + .deselectDelay = CYBSP_SMIF_CORE_1_PSRAM_DESELECT_DELAY, + .blockEvent = (uint32_t)CY_SMIF_BUS_ERROR, + .inputFrequencyMHz = 399, + .enable_internal_dll = false, + .dll_divider_value = CY_SMIF_DLL_DIVIDE_BY_2, + .rx_capture_mode = CY_SMIF_SEL_NORMAL_SPI, + .mdl_tap = CY_SMIF_MDL_8_TAP_DELAY, + .device0_sdl_tap = CY_SMIF_SDL_8_TAP_DELAY, + .device1_sdl_tap = CY_SMIF_SDL_8_TAP_DELAY, + .device2_sdl_tap = CY_SMIF_SDL_8_TAP_DELAY, + .device3_sdl_tap = CY_SMIF_SDL_8_TAP_DELAY, + .tx_sdr_extra = CY_SMIF_TX_TWO_PERIOD_AHEAD, +}; + +#if defined (COMPONENT_MTB_HAL) +const mtb_hal_hf_clock_t CYBSP_SMIF_CORE_1_PSRAM_clock_ref = +{ + .inst_num = 4U, +}; +const mtb_hal_clock_t CYBSP_SMIF_CORE_1_PSRAM_hal_clock = +{ + .clock_ref = &CYBSP_SMIF_CORE_1_PSRAM_clock_ref, + .interface = &mtb_hal_clock_hf_interface, +}; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_MEMORYSPI) +const mtb_hal_memoryspi_configurator_t CYBSP_SMIF_CORE_1_PSRAM_hal_config = +{ + .base = SMIF1_CORE, + .clock = &CYBSP_SMIF_CORE_1_PSRAM_hal_clock, + .config = &CYBSP_SMIF_CORE_1_PSRAM_config, + .csel = {false, false, true, false}, + .irqs = CYBSP_SMIF_CORE_1_PSRAM_MEMORY_MODE_ALIGMENT_ERROR << 5 | CYBSP_SMIF_CORE_1_PSRAM_RX_DATA_FIFO_UNDERFLOW << 4 | CYBSP_SMIF_CORE_1_PSRAM_TX_COMMAND_FIFO_OVERFLOW << 3 | CYBSP_SMIF_CORE_1_PSRAM_TX_DATA_FIFO_OVERFLOW << 2 | (uint8_t)(CYBSP_SMIF_CORE_1_PSRAM_RX_FIFO_TRIGGER_LEVEL != 0) << 1 | (uint8_t)(CYBSP_SMIF_CORE_1_PSRAM_TX_FIFO_TRIGGER_LEVEL != 0) << 0, + .dmas = CYBSP_SMIF_CORE_1_PSRAM_RX_DMA_TRIGGER_OUT_USED << 1 | CYBSP_SMIF_CORE_1_PSRAM_TX_DMA_TRIGGER_OUT_USED << 0, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_MEMORYSPI) */ + +const cy_stc_mcwdt_config_t CYBSP_CM33_LPTIMER_0_config = +{ + .c0Match = 32768U, + .c1Match = 32768U, + .c0Mode = CY_MCWDT_MODE_INT, + .c1Mode = CY_MCWDT_MODE_INT, + .c2ToggleBit = 0U, + .c2Mode = CY_MCWDT_MODE_NONE, + .c0ClearOnMatch = false, + .c1ClearOnMatch = false, + .c0c1Cascade = true, + .c1c2Cascade = false, + .c0LowerLimitMode = CY_MCWDT_LOWER_LIMIT_MODE_NOTHING, + .c0LowerLimit = 0U, + .c1LowerLimitMode = CY_MCWDT_LOWER_LIMIT_MODE_NOTHING, + .c1LowerLimit = 0U, +}; + +#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_LPTIMER) +const mtb_hal_lptimer_configurator_t CYBSP_CM33_LPTIMER_0_hal_config = +{ + .base = CYBSP_CM33_LPTIMER_0_HW, + .lfclk_freqhz = 32768, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_LPTIMER) */ + +const cy_stc_mcwdt_config_t CYBSP_CM55_LPTIMER_1_config = +{ + .c0Match = 32768U, + .c1Match = 32768U, + .c0Mode = CY_MCWDT_MODE_INT, + .c1Mode = CY_MCWDT_MODE_INT, + .c2ToggleBit = 0U, + .c2Mode = CY_MCWDT_MODE_NONE, + .c0ClearOnMatch = false, + .c1ClearOnMatch = false, + .c0c1Cascade = true, + .c1c2Cascade = false, + .c0LowerLimitMode = CY_MCWDT_LOWER_LIMIT_MODE_NOTHING, + .c0LowerLimit = 0U, + .c1LowerLimitMode = CY_MCWDT_LOWER_LIMIT_MODE_NOTHING, + .c1LowerLimit = 0U, +}; + +#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_LPTIMER) +const mtb_hal_lptimer_configurator_t CYBSP_CM55_LPTIMER_1_hal_config = +{ + .base = CYBSP_CM55_LPTIMER_1_HW, + .lfclk_freqhz = 32768, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_LPTIMER) */ + +cy_stc_tdm_config_tx_t CYBSP_TDM_CONTROLLER_0_tx_config = +{ + .enable = true, + .masterMode = CY_TDM_DEVICE_MASTER, + .wordSize = CY_TDM_SIZE_16, + .format = CY_TDM_LEFT_DELAYED, + .clkDiv = 4, + .clkSel = CY_TDM_SEL_SRSS_CLK0, + .sckPolarity = CY_TDM_CLK, + .fsyncPolarity = CY_TDM_SIGN_INVERTED, + .fsyncFormat = CY_TDM_CH_PERIOD, + .channelNum = 2, + .channelSize = 16, + .fifoTriggerLevel = 64, + .chEn = 0x3, + .signalInput = 0, + .i2sMode = true, +}; +cy_stc_tdm_config_rx_t CYBSP_TDM_CONTROLLER_0_rx_config = +{ + .enable = false, + .masterMode = CY_TDM_DEVICE_SLAVE, + .wordSize = CY_TDM_SIZE_16, + .signExtend = CY_ZERO_EXTEND, + .format = CY_TDM_LEFT_DELAYED, + .clkDiv = 16, + .clkSel = CY_TDM_SEL_SRSS_CLK0, + .sckPolarity = CY_TDM_CLK, + .fsyncPolarity = CY_TDM_SIGN, + .lateSample = false, + .fsyncFormat = CY_TDM_BIT_PERIOD, + .channelNum = 2, + .channelSize = 16, + .fifoTriggerLevel = 0, + .chEn = 0x3, + .signalInput = 0, + .i2sMode = true, +}; +const cy_stc_tdm_config_t CYBSP_TDM_CONTROLLER_0_config = +{ + .tx_config = &CYBSP_TDM_CONTROLLER_0_tx_config, + .rx_config = &CYBSP_TDM_CONTROLLER_0_rx_config, +}; +const cy_stc_tcpwm_counter_config_t CYBSP_GENERAL_PURPOSE_TIMER_config = +{ + .period = 9999, + .clockPrescaler = CY_TCPWM_COUNTER_PRESCALER_DIVBY_1, + .runMode = CY_TCPWM_COUNTER_CONTINUOUS, + .countDirection = CY_TCPWM_COUNTER_COUNT_UP, + .compareOrCapture = CY_TCPWM_COUNTER_MODE_COMPARE, + .compare0 = 9999, + .compare1 = 16384, + .enableCompareSwap = false, + .interruptSources = (CY_TCPWM_INT_ON_TC ) | (CY_TCPWM_INT_ON_CC0 & 0U) | (CY_TCPWM_INT_ON_CC1 & 0U), + .captureInputMode = CYBSP_GENERAL_PURPOSE_TIMER_INPUT_DISABLED & 0x3U, + .captureInput = CY_TCPWM_INPUT_0, + .reloadInputMode = CYBSP_GENERAL_PURPOSE_TIMER_INPUT_DISABLED & 0x3U, + .reloadInput = CY_TCPWM_INPUT_0, + .startInputMode = CYBSP_GENERAL_PURPOSE_TIMER_INPUT_DISABLED & 0x3U, + .startInput = CY_TCPWM_INPUT_0, + .stopInputMode = CYBSP_GENERAL_PURPOSE_TIMER_INPUT_DISABLED & 0x3U, + .stopInput = CY_TCPWM_INPUT_0, + .countInputMode = CYBSP_GENERAL_PURPOSE_TIMER_INPUT_DISABLED & 0x3U, + .countInput = CY_TCPWM_INPUT_1, + .capture1InputMode = CYBSP_GENERAL_PURPOSE_TIMER_INPUT_DISABLED & 0x3U, + .capture1Input = CY_TCPWM_INPUT_0, + .compare2 = CY_TCPWM_GRP_CNT_CC0_DEFAULT, + .compare3 = CY_TCPWM_GRP_CNT_CC0_BUFF_DEFAULT, + .enableCompare1Swap = false, + .trigger0Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, + .trigger1Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, +#if defined (CY_IP_MXS40TCPWM) + .buffer_swap_enable = false, + .direction_mode = CY_TCPWM_COUNTER_DIRECTION_DISABLE, + .glitch_filter_enable = false, + .gf_depth = CY_GLITCH_FILTER_DEPTH_SUPPORT_VALUE_0, +#endif /* defined (CY_IP_MXS40TCPWM) */ +}; + +#if defined (COMPONENT_MTB_HAL) +const mtb_hal_peri_div_t CYBSP_GENERAL_PURPOSE_TIMER_clock_ref = +{ + .clk_dst = (en_clk_dst_t)PCLK_TCPWM0_CLOCK_COUNTER_EN0, + .div_type = CY_SYSCLK_DIV_16_BIT, + .div_num = 2, +}; +const mtb_hal_clock_t CYBSP_GENERAL_PURPOSE_TIMER_hal_clock = +{ + .clock_ref = &CYBSP_GENERAL_PURPOSE_TIMER_clock_ref, + .interface = &mtb_hal_clock_peri_interface, +}; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_TIMER) +const mtb_hal_timer_configurator_t CYBSP_GENERAL_PURPOSE_TIMER_hal_config = +{ + .tcpwm_base = CYBSP_GENERAL_PURPOSE_TIMER_HW, + .clock = &CYBSP_GENERAL_PURPOSE_TIMER_hal_clock, + .tcpwm_cntnum = 0U, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_TIMER) */ + +cy_stc_tcpwm_counter_config_t emUSB_OS_Timer_config = +{ + .period = 99999, + .clockPrescaler = CY_TCPWM_COUNTER_PRESCALER_DIVBY_1, + .runMode = CY_TCPWM_COUNTER_CONTINUOUS, + .countDirection = CY_TCPWM_COUNTER_COUNT_UP, + .compareOrCapture = CY_TCPWM_COUNTER_MODE_CAPTURE, + .compare0 = 16384U, + .compare1 = 16384U, + .enableCompareSwap = false, + .interruptSources = (CY_TCPWM_INT_ON_TC & 0U) | (CY_TCPWM_INT_ON_CC0) | (CY_TCPWM_INT_ON_CC1 & 0U), + .captureInputMode = emUSB_OS_Timer_INPUT_DISABLED & 0x3U, + .captureInput = CY_TCPWM_INPUT_0, + .reloadInputMode = emUSB_OS_Timer_INPUT_DISABLED & 0x3U, + .reloadInput = CY_TCPWM_INPUT_0, + .startInputMode = emUSB_OS_Timer_INPUT_DISABLED & 0x3U, + .startInput = CY_TCPWM_INPUT_0, + .stopInputMode = emUSB_OS_Timer_INPUT_DISABLED & 0x3U, + .stopInput = CY_TCPWM_INPUT_0, + .countInputMode = emUSB_OS_Timer_INPUT_DISABLED & 0x3U, + .countInput = CY_TCPWM_INPUT_1, + .capture1InputMode = emUSB_OS_Timer_INPUT_DISABLED & 0x3U, + .capture1Input = CY_TCPWM_INPUT_0, + .compare2 = CY_TCPWM_GRP_CNT_CC0_DEFAULT, + .compare3 = CY_TCPWM_GRP_CNT_CC0_BUFF_DEFAULT, + .enableCompare1Swap = false, + .trigger0Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, + .trigger1Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, +}; + +#if defined (COMPONENT_MTB_HAL) +mtb_hal_peri_div_t emUSB_OS_Timer_clock_ref = +{ + .clk_dst = (en_clk_dst_t)PCLK_TCPWM0_CLOCK_COUNTER_EN1, + .div_type = CY_SYSCLK_DIV_8_BIT, + .div_num = 2, +}; +mtb_hal_clock_t emUSB_OS_Timer_hal_clock = +{ + .clock_ref = &emUSB_OS_Timer_clock_ref, + .interface = &mtb_hal_clock_peri_interface, +}; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_TIMER) +mtb_hal_timer_configurator_t emUSB_OS_Timer_hal_config = +{ + .tcpwm_base = emUSB_OS_Timer_HW, + .clock = &emUSB_OS_Timer_hal_clock, + .tcpwm_cntnum = 1U, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_TIMER) */ + +const cy_stc_tcpwm_pwm_config_t CYBSP_PWM_LED_CTRL_config = +{ + .pwmMode = CY_TCPWM_PWM_MODE_PWM, + .clockPrescaler = CY_TCPWM_PWM_PRESCALER_DIVBY_1, + .pwmAlignment = CY_TCPWM_PWM_LEFT_ALIGN, + .deadTimeClocks = 0, + .runMode = CY_TCPWM_PWM_CONTINUOUS, + .period0 = 2000, + .period1 = 32768, + .enablePeriodSwap = false, + .compare0 = 1000, + .compare1 = 16384, + .enableCompareSwap = false, + .interruptSources = (CY_TCPWM_INT_ON_TC & 0U) | (CY_TCPWM_INT_ON_CC0 & 0U) | (CY_TCPWM_INT_ON_CC1 & 0U), + .invertPWMOut = CY_TCPWM_PWM_INVERT_DISABLE, + .invertPWMOutN = CY_TCPWM_PWM_INVERT_DISABLE, + .killMode = CY_TCPWM_PWM_ASYNC_KILL, + .swapInputMode = CYBSP_PWM_LED_CTRL_INPUT_DISABLED & 0x3U, + .swapInput = CY_TCPWM_INPUT_0, + .reloadInputMode = CYBSP_PWM_LED_CTRL_INPUT_DISABLED & 0x3U, + .reloadInput = CY_TCPWM_INPUT_0, + .startInputMode = CYBSP_PWM_LED_CTRL_INPUT_DISABLED & 0x3U, + .startInput = CY_TCPWM_INPUT_0, + .killInputMode = CYBSP_PWM_LED_CTRL_INPUT_DISABLED & 0x3U, + .killInput = CY_TCPWM_INPUT_0, + .countInputMode = CYBSP_PWM_LED_CTRL_INPUT_DISABLED & 0x3U, + .countInput = CY_TCPWM_INPUT_1, + .swapOverflowUnderflow = false, + .immediateKill = false, + .tapsEnabled = 45, + .compare2 = CY_TCPWM_GRP_CNT_CC0_DEFAULT, + .compare3 = CY_TCPWM_GRP_CNT_CC0_BUFF_DEFAULT, + .enableCompare1Swap = false, + .compare0MatchUp = true, + .compare0MatchDown = false, + .compare1MatchUp = true, + .compare1MatchDown = false, + .kill1InputMode = CYBSP_PWM_LED_CTRL_INPUT_DISABLED & 0x3U, + .kill1Input = CY_TCPWM_INPUT_0, + .pwmOnDisable = CY_TCPWM_PWM_OUTPUT_HIGHZ, + .trigger0Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, + .trigger1Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, + .reloadLineSelect = false, + .line_out_sel = CY_TCPWM_OUTPUT_PWM_SIGNAL, + .linecompl_out_sel = CY_TCPWM_OUTPUT_INVERTED_PWM_SIGNAL, + .line_out_sel_buff = CY_TCPWM_OUTPUT_PWM_SIGNAL, + .linecompl_out_sel_buff = CY_TCPWM_OUTPUT_INVERTED_PWM_SIGNAL, + .deadTimeClocks_linecompl_out = 0, +#if defined (CY_IP_MXS40TCPWM) + .hrpwm_enable = false, + .hrpwm_input_freq = CY_TCPWM_HRPWM_FREQ_80MHZ_OR_100MHZ, + .kill_line_polarity = CY_TCPWM_LINEOUT_AND_LINECMPOUT_IS_LOW, + .deadTimeClocksBuff = 0, + .deadTimeClocksBuff_linecompl_out = 0, + .buffer_swap_enable = false, + .glitch_filter_enable = false, + .gf_depth = CY_GLITCH_FILTER_DEPTH_SUPPORT_VALUE_0, + .dithering_mode = CY_TCPWM_DITHERING_DISABLE, + .period_dithering_value = 128, + .duty_dithering_value = 128, + .limiter = CY_TCPWM_DITHERING_LIMITER_7, + .pwm_tc_sync_kill_dt = false, + .pwm_sync_kill_dt = false, +#endif /* defined (CY_IP_MXS40TCPWM) */ +}; + +#if defined (COMPONENT_MTB_HAL) +const mtb_hal_peri_div_t CYBSP_PWM_LED_CTRL_clock_ref = +{ + .clk_dst = (en_clk_dst_t)PCLK_TCPWM0_CLOCK_COUNTER_EN5, + .div_type = CY_SYSCLK_DIV_16_BIT, + .div_num = 3, +}; +const mtb_hal_clock_t CYBSP_PWM_LED_CTRL_hal_clock = +{ + .clock_ref = &CYBSP_PWM_LED_CTRL_clock_ref, + .interface = &mtb_hal_clock_peri_interface, +}; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) +const mtb_hal_pwm_configurator_t CYBSP_PWM_LED_CTRL_hal_config = +{ + .base = CYBSP_PWM_LED_CTRL_HW, + .clock = &CYBSP_PWM_LED_CTRL_hal_clock, + .group = 0UL, + .cntnum = 5UL, + .max_count = 2000, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) */ + +const cy_stc_tcpwm_pwm_config_t CYBSP_DEAD_TIME_PWM_config = +{ + .pwmMode = CY_TCPWM_PWM_MODE_DEADTIME, + .clockPrescaler = CY_TCPWM_PWM_PRESCALER_DIVBY_1, + .pwmAlignment = CY_TCPWM_PWM_LEFT_ALIGN, + .deadTimeClocks = 100, + .runMode = CY_TCPWM_PWM_CONTINUOUS, + .period0 = 400, + .period1 = 32768, + .enablePeriodSwap = false, + .compare0 = 200, + .compare1 = 16384, + .enableCompareSwap = false, + .interruptSources = (CY_TCPWM_INT_ON_TC & 0U) | (CY_TCPWM_INT_ON_CC0 & 0U) | (CY_TCPWM_INT_ON_CC1 & 0U), + .invertPWMOut = CY_TCPWM_PWM_INVERT_DISABLE, + .invertPWMOutN = CY_TCPWM_PWM_INVERT_DISABLE, + .killMode = CY_TCPWM_PWM_STOP_ON_KILL, + .swapInputMode = CYBSP_DEAD_TIME_PWM_INPUT_DISABLED & 0x3U, + .swapInput = CY_TCPWM_INPUT_0, + .reloadInputMode = CYBSP_DEAD_TIME_PWM_INPUT_DISABLED & 0x3U, + .reloadInput = CY_TCPWM_INPUT_0, + .startInputMode = CYBSP_DEAD_TIME_PWM_INPUT_DISABLED & 0x3U, + .startInput = CY_TCPWM_INPUT_0, + .killInputMode = CYBSP_DEAD_TIME_PWM_INPUT_DISABLED & 0x3U, + .killInput = CY_TCPWM_INPUT_0, + .countInputMode = CYBSP_DEAD_TIME_PWM_INPUT_DISABLED & 0x3U, + .countInput = CY_TCPWM_INPUT_1, + .swapOverflowUnderflow = false, + .immediateKill = false, + .tapsEnabled = 45, + .compare2 = CY_TCPWM_GRP_CNT_CC0_DEFAULT, + .compare3 = CY_TCPWM_GRP_CNT_CC0_BUFF_DEFAULT, + .enableCompare1Swap = false, + .compare0MatchUp = true, + .compare0MatchDown = false, + .compare1MatchUp = true, + .compare1MatchDown = false, + .kill1InputMode = CYBSP_DEAD_TIME_PWM_INPUT_DISABLED & 0x3U, + .kill1Input = CY_TCPWM_INPUT_0, + .pwmOnDisable = CY_TCPWM_PWM_OUTPUT_HIGHZ, + .trigger0Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, + .trigger1Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, + .reloadLineSelect = false, + .line_out_sel = CY_TCPWM_OUTPUT_PWM_SIGNAL, + .linecompl_out_sel = CY_TCPWM_OUTPUT_INVERTED_PWM_SIGNAL, + .line_out_sel_buff = CY_TCPWM_OUTPUT_PWM_SIGNAL, + .linecompl_out_sel_buff = CY_TCPWM_OUTPUT_INVERTED_PWM_SIGNAL, + .deadTimeClocks_linecompl_out = 100, +#if defined (CY_IP_MXS40TCPWM) + .hrpwm_enable = false, + .hrpwm_input_freq = CY_TCPWM_HRPWM_FREQ_80MHZ_OR_100MHZ, + .kill_line_polarity = CY_TCPWM_LINEOUT_AND_LINECMPOUT_IS_LOW, + .deadTimeClocksBuff = 0, + .deadTimeClocksBuff_linecompl_out = 0, + .buffer_swap_enable = false, + .glitch_filter_enable = false, + .gf_depth = CY_GLITCH_FILTER_DEPTH_SUPPORT_VALUE_0, + .dithering_mode = CY_TCPWM_DITHERING_DISABLE, + .period_dithering_value = 128, + .duty_dithering_value = 128, + .limiter = CY_TCPWM_DITHERING_LIMITER_7, + .pwm_tc_sync_kill_dt = false, + .pwm_sync_kill_dt = false, +#endif /* defined (CY_IP_MXS40TCPWM) */ +}; + +#if defined (COMPONENT_MTB_HAL) +const mtb_hal_peri_div_t CYBSP_DEAD_TIME_PWM_clock_ref = +{ + .clk_dst = (en_clk_dst_t)PCLK_TCPWM0_CLOCK_COUNTER_EN7, + .div_type = CY_SYSCLK_DIV_8_BIT, + .div_num = 3, +}; +const mtb_hal_clock_t CYBSP_DEAD_TIME_PWM_hal_clock = +{ + .clock_ref = &CYBSP_DEAD_TIME_PWM_clock_ref, + .interface = &mtb_hal_clock_peri_interface, +}; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) +const mtb_hal_pwm_configurator_t CYBSP_DEAD_TIME_PWM_hal_config = +{ + .base = CYBSP_DEAD_TIME_PWM_HW, + .clock = &CYBSP_DEAD_TIME_PWM_hal_clock, + .group = 0UL, + .cntnum = 7UL, + .max_count = 400, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) */ + +const cy_stc_tcpwm_pwm_config_t CYBSP_SMARTIO_PWM_config = +{ + .pwmMode = CY_TCPWM_PWM_MODE_PWM, + .clockPrescaler = CY_TCPWM_PWM_PRESCALER_DIVBY_1, + .pwmAlignment = CY_TCPWM_PWM_LEFT_ALIGN, + .deadTimeClocks = 0, + .runMode = CY_TCPWM_PWM_CONTINUOUS, + .period0 = 399, + .period1 = 32768, + .enablePeriodSwap = false, + .compare0 = 200, + .compare1 = 16384, + .enableCompareSwap = false, + .interruptSources = (CY_TCPWM_INT_ON_TC & 0U) | (CY_TCPWM_INT_ON_CC0 & 0U) | (CY_TCPWM_INT_ON_CC1 & 0U), + .invertPWMOut = CY_TCPWM_PWM_INVERT_DISABLE, + .invertPWMOutN = CY_TCPWM_PWM_INVERT_DISABLE, + .killMode = CY_TCPWM_PWM_ASYNC_KILL, + .swapInputMode = CYBSP_SMARTIO_PWM_INPUT_DISABLED & 0x3U, + .swapInput = CY_TCPWM_INPUT_0, + .reloadInputMode = CYBSP_SMARTIO_PWM_INPUT_DISABLED & 0x3U, + .reloadInput = CY_TCPWM_INPUT_0, + .startInputMode = CYBSP_SMARTIO_PWM_INPUT_DISABLED & 0x3U, + .startInput = CY_TCPWM_INPUT_0, + .killInputMode = CYBSP_SMARTIO_PWM_INPUT_DISABLED & 0x3U, + .killInput = CY_TCPWM_INPUT_0, + .countInputMode = CYBSP_SMARTIO_PWM_INPUT_DISABLED & 0x3U, + .countInput = CY_TCPWM_INPUT_1, + .swapOverflowUnderflow = false, + .immediateKill = false, + .tapsEnabled = 45, + .compare2 = 200, + .compare3 = 16384, + .enableCompare1Swap = false, + .compare0MatchUp = true, + .compare0MatchDown = false, + .compare1MatchUp = true, + .compare1MatchDown = false, + .kill1InputMode = CYBSP_SMARTIO_PWM_INPUT_DISABLED & 0x3U, + .kill1Input = CY_TCPWM_INPUT_0, + .pwmOnDisable = CY_TCPWM_PWM_OUTPUT_HIGHZ, + .trigger0Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, + .trigger1Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, + .reloadLineSelect = false, + .line_out_sel = CY_TCPWM_OUTPUT_PWM_SIGNAL, + .linecompl_out_sel = CY_TCPWM_OUTPUT_INVERTED_PWM_SIGNAL, + .line_out_sel_buff = CY_TCPWM_OUTPUT_PWM_SIGNAL, + .linecompl_out_sel_buff = CY_TCPWM_OUTPUT_INVERTED_PWM_SIGNAL, + .deadTimeClocks_linecompl_out = 0, +#if defined (CY_IP_MXS40TCPWM) + .hrpwm_enable = false, + .hrpwm_input_freq = CY_TCPWM_HRPWM_FREQ_80MHZ_OR_100MHZ, + .kill_line_polarity = CY_TCPWM_LINEOUT_AND_LINECMPOUT_IS_LOW, + .deadTimeClocksBuff = 0, + .deadTimeClocksBuff_linecompl_out = 0, + .buffer_swap_enable = false, + .glitch_filter_enable = false, + .gf_depth = CY_GLITCH_FILTER_DEPTH_SUPPORT_VALUE_0, + .dithering_mode = CY_TCPWM_DITHERING_DISABLE, + .period_dithering_value = 128, + .duty_dithering_value = 128, + .limiter = CY_TCPWM_DITHERING_LIMITER_7, + .pwm_tc_sync_kill_dt = false, + .pwm_sync_kill_dt = false, +#endif /* defined (CY_IP_MXS40TCPWM) */ +}; + +#if defined (COMPONENT_MTB_HAL) +const mtb_hal_peri_div_t CYBSP_SMARTIO_PWM_clock_ref = +{ + .clk_dst = (en_clk_dst_t)PCLK_TCPWM0_CLOCK_COUNTER_EN262, + .div_type = CY_SYSCLK_DIV_16_5_BIT, + .div_num = 1, +}; +const mtb_hal_clock_t CYBSP_SMARTIO_PWM_hal_clock = +{ + .clock_ref = &CYBSP_SMARTIO_PWM_clock_ref, + .interface = &mtb_hal_clock_peri_interface, +}; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) +const mtb_hal_pwm_configurator_t CYBSP_SMARTIO_PWM_hal_config = +{ + .base = CYBSP_SMARTIO_PWM_HW, + .clock = &CYBSP_SMARTIO_PWM_hal_clock, + .group = 1UL, + .cntnum = 262UL, + .max_count = 399, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) */ + +const cy_stc_tcpwm_pwm_config_t tcpwm_0_group_1_cnt_9_config = +{ + .pwmMode = CY_TCPWM_PWM_MODE_PWM, + .clockPrescaler = CY_TCPWM_PWM_PRESCALER_DIVBY_2, + .pwmAlignment = CY_TCPWM_PWM_LEFT_ALIGN, + .deadTimeClocks = 0, + .runMode = CY_TCPWM_PWM_CONTINUOUS, + .period0 = 65535, + .period1 = 32768, + .enablePeriodSwap = false, + .compare0 = 52428, + .compare1 = 16384, + .enableCompareSwap = false, + .interruptSources = (CY_TCPWM_INT_ON_TC & 0U) | (CY_TCPWM_INT_ON_CC0 & 0U) | (CY_TCPWM_INT_ON_CC1 & 0U), + .invertPWMOut = CY_TCPWM_PWM_INVERT_DISABLE, + .invertPWMOutN = CY_TCPWM_PWM_INVERT_DISABLE, + .killMode = CY_TCPWM_PWM_STOP_ON_KILL, + .swapInputMode = tcpwm_0_group_1_cnt_9_INPUT_DISABLED & 0x3U, + .swapInput = CY_TCPWM_INPUT_0, + .reloadInputMode = tcpwm_0_group_1_cnt_9_INPUT_DISABLED & 0x3U, + .reloadInput = CY_TCPWM_INPUT_0, + .startInputMode = tcpwm_0_group_1_cnt_9_INPUT_DISABLED & 0x3U, + .startInput = CY_TCPWM_INPUT_0, + .killInputMode = tcpwm_0_group_1_cnt_9_INPUT_DISABLED & 0x3U, + .killInput = CY_TCPWM_INPUT_0, + .countInputMode = tcpwm_0_group_1_cnt_9_INPUT_DISABLED & 0x3U, + .countInput = CY_TCPWM_INPUT_1, + .swapOverflowUnderflow = false, + .immediateKill = false, + .tapsEnabled = 45, + .compare2 = 52428, + .compare3 = 16384, + .enableCompare1Swap = false, + .compare0MatchUp = true, + .compare0MatchDown = false, + .compare1MatchUp = true, + .compare1MatchDown = false, + .kill1InputMode = tcpwm_0_group_1_cnt_9_INPUT_DISABLED & 0x3U, + .kill1Input = CY_TCPWM_INPUT_0, + .pwmOnDisable = CY_TCPWM_PWM_OUTPUT_HIGHZ, + .trigger0Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, + .trigger1Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED, + .reloadLineSelect = false, + .line_out_sel = CY_TCPWM_OUTPUT_PWM_SIGNAL, + .linecompl_out_sel = CY_TCPWM_OUTPUT_INVERTED_PWM_SIGNAL, + .line_out_sel_buff = CY_TCPWM_OUTPUT_PWM_SIGNAL, + .linecompl_out_sel_buff = CY_TCPWM_OUTPUT_INVERTED_PWM_SIGNAL, + .deadTimeClocks_linecompl_out = 0, +#if defined (CY_IP_MXS40TCPWM) + .hrpwm_enable = false, + .hrpwm_input_freq = CY_TCPWM_HRPWM_FREQ_80MHZ_OR_100MHZ, + .kill_line_polarity = CY_TCPWM_LINEOUT_AND_LINECMPOUT_IS_LOW, + .deadTimeClocksBuff = 0, + .deadTimeClocksBuff_linecompl_out = 0, + .buffer_swap_enable = false, + .glitch_filter_enable = false, + .gf_depth = CY_GLITCH_FILTER_DEPTH_SUPPORT_VALUE_0, + .dithering_mode = CY_TCPWM_DITHERING_DISABLE, + .period_dithering_value = 128, + .duty_dithering_value = 128, + .limiter = CY_TCPWM_DITHERING_LIMITER_7, + .pwm_tc_sync_kill_dt = false, + .pwm_sync_kill_dt = false, +#endif /* defined (CY_IP_MXS40TCPWM) */ +}; + +#if defined (COMPONENT_MTB_HAL) +const mtb_hal_peri_div_t tcpwm_0_group_1_cnt_9_clock_ref = +{ + .clk_dst = (en_clk_dst_t)PCLK_TCPWM0_CLOCK_COUNTER_EN265, + .div_type = CY_SYSCLK_DIV_8_BIT, + .div_num = 4, +}; +const mtb_hal_clock_t tcpwm_0_group_1_cnt_9_hal_clock = +{ + .clock_ref = &tcpwm_0_group_1_cnt_9_clock_ref, + .interface = &mtb_hal_clock_peri_interface, +}; +#endif /* defined (COMPONENT_MTB_HAL) */ + +#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) +const mtb_hal_pwm_configurator_t tcpwm_0_group_1_cnt_9_hal_config = +{ + .base = tcpwm_0_group_1_cnt_9_HW, + .clock = &tcpwm_0_group_1_cnt_9_hal_clock, + .group = 1UL, + .cntnum = 265UL, + .max_count = 65535, +}; +#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) */ + +__WEAK void canfd0_rx_callback(bool rxFIFOMsg, uint8_t msgBufOrRxFIFONum, cy_stc_canfd_rx_buffer_t* basemsg); + +__WEAK void canfd0_rx_callback(bool rxFIFOMsg, uint8_t msgBufOrRxFIFONum, cy_stc_canfd_rx_buffer_t* basemsg) +{ + (void)rxFIFOMsg; + (void)msgBufOrRxFIFONum; + (void)basemsg; +} +void init_cycfg_peripherals(void) +{ + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_PASS_PERI_NR, CY_MMIO_PASS_GROUP_NR, CY_MMIO_PASS_SLAVE_NR, CY_MMIO_PASS_CLK_HF_NR); + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_GFXSS_GPU_PERI_NR, CY_MMIO_GFXSS_GPU_GROUP_NR, CY_MMIO_GFXSS_GPU_SLAVE_NR, CY_MMIO_GFXSS_GPU_CLK_HF_NR); + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_GFXSS_DC_PERI_NR, CY_MMIO_GFXSS_DC_GROUP_NR, CY_MMIO_GFXSS_DC_SLAVE_NR, CY_MMIO_GFXSS_DC_CLK_HF_NR); + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_GFXSS_MIPIDSI_PERI_NR, CY_MMIO_GFXSS_MIPIDSI_GROUP_NR, CY_MMIO_GFXSS_MIPIDSI_SLAVE_NR, CY_MMIO_GFXSS_MIPIDSI_CLK_HF_NR); + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_I3C_PERI_NR, CY_MMIO_I3C_GROUP_NR, CY_MMIO_I3C_SLAVE_NR, CY_MMIO_I3C_CLK_HF_NR); + Cy_SysClk_PeriphAssignDivider(PCLK_I3C_CLOCK_I3C_EN, CY_SYSCLK_DIV_8_BIT, 0U); +#if defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_PDM0_PERI_NR, CY_MMIO_PDM0_GROUP_NR, CY_MMIO_PDM0_SLAVE_NR, CY_MMIO_PDM0_CLK_HF_NR); +#endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */ + Cy_SysClk_PeriPclkAssignDivider(PCLK_PDM0_CLK_IF_SRSS, CY_SYSCLK_DIV_16_5_BIT, 1U); + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SCB0_PERI_NR, CY_MMIO_SCB0_GROUP_NR, CY_MMIO_SCB0_SLAVE_NR, CY_MMIO_SCB0_CLK_HF_NR); + Cy_SysClk_PeriPclkAssignDivider(PCLK_SCB0_CLOCK_SCB_EN, CY_SYSCLK_DIV_16_BIT, 0U); + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SCB2_PERI_NR, CY_MMIO_SCB2_GROUP_NR, CY_MMIO_SCB2_SLAVE_NR, CY_MMIO_SCB2_CLK_HF_NR); + Cy_SysClk_PeriPclkAssignDivider(PCLK_SCB2_CLOCK_SCB_EN, CY_SYSCLK_DIV_16_BIT, 1U); + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SCB4_PERI_NR, CY_MMIO_SCB4_GROUP_NR, CY_MMIO_SCB4_SLAVE_NR, CY_MMIO_SCB4_CLK_HF_NR); + Cy_SysClk_PeriPclkAssignDivider(PCLK_SCB4_CLOCK_SCB_EN, CY_SYSCLK_DIV_16_5_BIT, 0U); + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SCB5_PERI_NR, CY_MMIO_SCB5_GROUP_NR, CY_MMIO_SCB5_SLAVE_NR, CY_MMIO_SCB5_CLK_HF_NR); + Cy_SysClk_PeriPclkAssignDivider(PCLK_SCB5_CLOCK_SCB_EN, CY_SYSCLK_DIV_8_BIT, 0U); + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SCB9_PERI_NR, CY_MMIO_SCB9_GROUP_NR, CY_MMIO_SCB9_SLAVE_NR, CY_MMIO_SCB9_CLK_HF_NR); + Cy_SysClk_PeriPclkAssignDivider(PCLK_SCB9_CLOCK_SCB_EN, CY_SYSCLK_DIV_8_BIT, 1U); +#if defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SDHC0_PERI_NR, CY_MMIO_SDHC0_GROUP_NR, CY_MMIO_SDHC0_SLAVE_NR, CY_MMIO_SDHC0_CLK_HF_NR); +#endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */ + Cy_SysClk_PeriPclkAssignDivider(PCLK_SDHC0_CLK_HF, CY_SYSCLK_DIV_8_BIT, 0U); +#if defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SDHC1_PERI_NR, CY_MMIO_SDHC1_GROUP_NR, CY_MMIO_SDHC1_SLAVE_NR, CY_MMIO_SDHC1_CLK_HF_NR); +#endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */ + Cy_SysClk_PeriPclkAssignDivider(PCLK_SDHC1_CLK_HF, CY_SYSCLK_DIV_8_BIT, 0U); + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_USBHS_PERI_NR, CY_MMIO_USBHS_GROUP_NR, CY_MMIO_USBHS_SLAVE_NR, CY_MMIO_USBHS_CLK_HF_NR); +#if defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_CANFD0_PERI_NR , CY_MMIO_CANFD0_GROUP_NR, CY_MMIO_CANFD0_SLAVE_NR, CY_MMIO_CANFD0_CLK_HF_NR); +#endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */ + Cy_SysClk_PeriPclkAssignDivider(PCLK_CANFD0_CLOCK_CAN_EN0, CY_SYSCLK_DIV_8_BIT, 4U); + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SMIF0_PERI_NR, CY_MMIO_SMIF0_GROUP_NR, CY_MMIO_SMIF0_SLAVE_NR, CY_MMIO_SMIF0_CLK_HF_NR); + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SMIF01_PERI_NR, CY_MMIO_SMIF01_GROUP_NR, CY_MMIO_SMIF01_SLAVE_NR, CY_MMIO_SMIF01_CLK_HF_NR); +#if defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_TDM0_PERI_NR, CY_MMIO_TDM0_GROUP_NR, CY_MMIO_TDM0_SLAVE_NR, CY_MMIO_TDM0_CLK_HF_NR); +#endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */ + Cy_SysClk_PeriPclkAssignDivider(PCLK_TDM0_CLK_IF_SRSS0, CY_SYSCLK_DIV_16_5_BIT, 0U); +#if defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_TCPWM0_PERI_NR, CY_MMIO_TCPWM0_GROUP_NR, CY_MMIO_TCPWM0_SLAVE_NR, CY_MMIO_TCPWM0_CLK_HF_NR); +#endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */ + Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCK_COUNTER_EN0, CY_SYSCLK_DIV_16_BIT, 2U); +#if defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_TCPWM0_PERI_NR, CY_MMIO_TCPWM0_GROUP_NR, CY_MMIO_TCPWM0_SLAVE_NR, CY_MMIO_TCPWM0_CLK_HF_NR); +#endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */ + Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCK_COUNTER_EN1, CY_SYSCLK_DIV_8_BIT, 2U); +#if defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_TCPWM0_PERI_NR, CY_MMIO_TCPWM0_GROUP_NR, CY_MMIO_TCPWM0_SLAVE_NR, CY_MMIO_TCPWM0_CLK_HF_NR); +#endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */ + Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCK_COUNTER_EN5, CY_SYSCLK_DIV_16_BIT, 3U); +#if defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_TCPWM0_PERI_NR, CY_MMIO_TCPWM0_GROUP_NR, CY_MMIO_TCPWM0_SLAVE_NR, CY_MMIO_TCPWM0_CLK_HF_NR); +#endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */ + Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCK_COUNTER_EN7, CY_SYSCLK_DIV_8_BIT, 3U); +#if defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_TCPWM0_PERI_NR, CY_MMIO_TCPWM0_GROUP_NR, CY_MMIO_TCPWM0_SLAVE_NR, CY_MMIO_TCPWM0_CLK_HF_NR); +#endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */ + Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCK_COUNTER_EN262, CY_SYSCLK_DIV_16_5_BIT, 1U); +#if defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) + Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_TCPWM0_PERI_NR, CY_MMIO_TCPWM0_GROUP_NR, CY_MMIO_TCPWM0_SLAVE_NR, CY_MMIO_TCPWM0_CLK_HF_NR); +#endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */ + Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCK_COUNTER_EN265, CY_SYSCLK_DIV_8_BIT, 4U); +} diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripherals.h b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripherals.h index 4ccadc40..bcb4fdfd 100644 --- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripherals.h +++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripherals.h @@ -4,9 +4,9 @@ * Description: * Analog configuration * This file was automatically generated and should not be modified. - * Configurator Backend 3.60.0 - * device-db 4.34.0.9502 - * mtb-dsl-pse8xxgp 1.1.1.824 + * Configurator Backend 3.70.0 + * device-db 4.35.0.9884 + * mtb-dsl-pse8xxgp 1.4.0.994 * ******************************************************************************* * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or @@ -39,6 +39,7 @@ #include "cy_scb_uart.h" #include "cy_scb_spi.h" #include "cy_sd_host.h" +#include "cy_canfd.h" #include "cy_smif.h" #include "cycfg_qspi_memslot.h" #include "cy_mcwdt.h" @@ -98,9 +99,9 @@ extern "C" { #define CYBSP_UART5_ENABLED 1U #define CYBSP_UART5_HW SCB5 #define CYBSP_UART5_IRQ scb_5_interrupt_IRQn -#define CYBSP_SPI_CONTROLLER_ENABLED 1U -#define CYBSP_SPI_CONTROLLER_HW SCB10 -#define CYBSP_SPI_CONTROLLER_IRQ scb_10_interrupt_IRQn +#define CYBSP_SPI_9_ENABLED 1U +#define CYBSP_SPI_9_HW SCB9 +#define CYBSP_SPI_9_IRQ scb_9_interrupt_IRQn #define CYBSP_SDHC_0_ENABLED 1U #define CYBSP_SDHC_0_HW SDHC0 #define CYBSP_SDHC_0_IRQ sdhc_0_interrupt_general_IRQn @@ -108,6 +109,30 @@ extern "C" { #define CYBSP_SDHC_1_HW SDHC1 #define CYBSP_SDHC_1_IRQ sdhc_1_interrupt_general_IRQn #define CYBSP_USB_DEVICE_0_ENABLED 1U +#define CYBSP_CAN_FD_CH_0_ENABLED 1U +#define CYBSP_CAN_FD_CH_0_HW CANFD0 +#define CYBSP_CAN_FD_CH_0_CHANNEL CANFD0_CH0 +#define CYBSP_CAN_FD_CH_0_STD_ID_FILTER_ID_0 0 +#define CYBSP_CAN_FD_CH_0_EXT_ID_FILTER_ID_0 0 +#define CYBSP_CAN_FD_CH_0_DATA_0 0 +#define CYBSP_CAN_FD_CH_0_DATA_1 1 +#define CYBSP_CAN_FD_CH_0_DATA_2 2 +#define CYBSP_CAN_FD_CH_0_DATA_3 3 +#define CYBSP_CAN_FD_CH_0_DATA_4 4 +#define CYBSP_CAN_FD_CH_0_DATA_5 5 +#define CYBSP_CAN_FD_CH_0_DATA_6 6 +#define CYBSP_CAN_FD_CH_0_DATA_7 7 +#define CYBSP_CAN_FD_CH_0_DATA_8 8 +#define CYBSP_CAN_FD_CH_0_DATA_9 9 +#define CYBSP_CAN_FD_CH_0_DATA_10 10 +#define CYBSP_CAN_FD_CH_0_DATA_11 11 +#define CYBSP_CAN_FD_CH_0_DATA_12 12 +#define CYBSP_CAN_FD_CH_0_DATA_13 13 +#define CYBSP_CAN_FD_CH_0_DATA_14 14 +#define CYBSP_CAN_FD_CH_0_DATA_15 15 +#define CYBSP_CAN_FD_CH_0_IRQ_0 canfd_0_interrupts0_0_IRQn +#define CYBSP_CAN_FD_CH_0_IRQ_1 canfd_0_interrupts1_0_IRQn +#define CYBSP_CAN_FD_CH_0_CHANNEL_NUM 0U #define CYBSP_SMIF_CORE_0_XSPI_FLASH_ENABLED 1U #define CYBSP_SMIF_CORE_0_XSPI_FLASH_HW SMIF0_CORE #define CYBSP_SMIF_CORE_0_XSPI_FLASH_IRQ smif_0_smif0_interrupt_nsec_IRQn @@ -254,15 +279,15 @@ extern const mtb_hal_clock_t CYBSP_UART5_hal_clock; extern const mtb_hal_uart_configurator_t CYBSP_UART5_hal_config; #endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_UART) */ -extern const cy_stc_scb_spi_config_t CYBSP_SPI_CONTROLLER_config; +extern const cy_stc_scb_spi_config_t CYBSP_SPI_9_config; #if defined (COMPONENT_MTB_HAL) -extern const mtb_hal_peri_div_t CYBSP_SPI_CONTROLLER_clock_ref; -extern const mtb_hal_clock_t CYBSP_SPI_CONTROLLER_hal_clock; +extern const mtb_hal_peri_div_t CYBSP_SPI_9_clock_ref; +extern const mtb_hal_clock_t CYBSP_SPI_9_hal_clock; #endif /* defined (COMPONENT_MTB_HAL) */ #if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SPI) -extern const mtb_hal_spi_configurator_t CYBSP_SPI_CONTROLLER_hal_config; +extern const mtb_hal_spi_configurator_t CYBSP_SPI_9_hal_config; #endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SPI) */ extern cy_en_sd_host_card_capacity_t CYBSP_SDHC_0_cardCapacity; @@ -297,6 +322,30 @@ extern const mtb_hal_sdhc_configurator_t CYBSP_SDHC_1_sdhc_hal_config; extern const mtb_hal_sdio_configurator_t CYBSP_SDHC_1_sdio_hal_config; #endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_SDIO) */ +extern void canfd0_rx_callback(bool rxFIFOMsg, uint8_t msgBufOrRxFIFONum, cy_stc_canfd_rx_buffer_t* basemsg); +extern const cy_stc_canfd_bitrate_t CYBSP_CAN_FD_CH_0_nominalBitrateConfig; +extern const cy_stc_canfd_bitrate_t CYBSP_CAN_FD_CH_0_dataBitrateConfig; +extern const cy_stc_canfd_transceiver_delay_compensation_t CYBSP_CAN_FD_CH_0_tdcConfig; +extern const cy_stc_id_filter_t CYBSP_CAN_FD_CH_0_stdIdFilter_0; +extern const cy_stc_id_filter_t CYBSP_CAN_FD_CH_0_stdIdFilters[]; +extern const cy_stc_canfd_sid_filter_config_t CYBSP_CAN_FD_CH_0_sidFiltersConfig; +extern const cy_stc_canfd_f0_t CYBSP_CAN_FD_CH_0_extIdFilterF0Config_0; +extern const cy_stc_canfd_f1_t CYBSP_CAN_FD_CH_0_extIdFilterF1Config_0; +extern const cy_stc_extid_filter_t CYBSP_CAN_FD_CH_0_extIdFilter_0; +extern const cy_stc_extid_filter_t CYBSP_CAN_FD_CH_0_extIdFilters[]; +extern const cy_stc_canfd_extid_filter_config_t CYBSP_CAN_FD_CH_0_extIdFiltersConfig; +extern const cy_stc_canfd_global_filter_config_t CYBSP_CAN_FD_CH_0_globalFilterConfig; +extern const cy_en_canfd_fifo_config_t CYBSP_CAN_FD_CH_0_rxFifo0Config; +extern const cy_en_canfd_fifo_config_t CYBSP_CAN_FD_CH_0_rxFifo1Config; +extern const cy_stc_canfd_config_t CYBSP_CAN_FD_CH_0_config; +extern cy_stc_canfd_t0_t CYBSP_CAN_FD_CH_0_T0RegisterBuffer_0; +extern cy_stc_canfd_t0_t CYBSP_CAN_FD_CH_0_T0RegisterBuffer_1; +extern cy_stc_canfd_t1_t CYBSP_CAN_FD_CH_0_T1RegisterBuffer_0; +extern cy_stc_canfd_t1_t CYBSP_CAN_FD_CH_0_T1RegisterBuffer_1; +extern uint32_t CYBSP_CAN_FD_CH_0_dataBuffer_0[]; +extern uint32_t CYBSP_CAN_FD_CH_0_dataBuffer_1[]; +extern cy_stc_canfd_tx_buffer_t CYBSP_CAN_FD_CH_0_txBuffer_0; +extern cy_stc_canfd_tx_buffer_t CYBSP_CAN_FD_CH_0_txBuffer_1; extern const cy_stc_smif_config_t CYBSP_SMIF_CORE_0_XSPI_FLASH_config; #if defined (COMPONENT_MTB_HAL) diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_pins.c b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_pins.c index 41132045..6e470baf 100644 --- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_pins.c +++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_pins.c @@ -4,9 +4,9 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. - * Configurator Backend 3.60.0 - * device-db 4.34.0.9502 - * mtb-dsl-pse8xxgp 1.1.1.824 + * Configurator Backend 3.70.0 + * device-db 4.35.0.9884 + * mtb-dsl-pse8xxgp 1.4.0.994 * ******************************************************************************* * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or @@ -771,8 +771,8 @@ const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config = .outVal = 1, .driveMode = CY_GPIO_DM_OD_DRIVESLOW, .hsiom = CYBSP_WIFI_HOST_WAKE_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, + .intEdge = CY_GPIO_INTR_RISING, + .intMask = 1UL, .vtrip = CY_GPIO_VTRIP_CMOS, .slewRate = CY_GPIO_SLEW_FAST, .driveSel = CY_GPIO_DRIVE_1_2, @@ -951,11 +951,11 @@ const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D3_config = .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, .nonSec = 1, }; -const cy_stc_gpio_pin_config_t CYBSP_ADC_6_POT_config = +const cy_stc_gpio_pin_config_t CYBSP_SPI_9_CLK_config = { .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_ADC_6_POT_HSIOM, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_SPI_9_CLK_HSIOM, .intEdge = CY_GPIO_INTR_DISABLE, .intMask = 0UL, .vtrip = CY_GPIO_VTRIP_CMOS, @@ -969,11 +969,11 @@ const cy_stc_gpio_pin_config_t CYBSP_ADC_6_POT_config = .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, .nonSec = 1, }; -const cy_stc_gpio_pin_config_t CYBSP_ARD_ADC_4_config = +const cy_stc_gpio_pin_config_t CYBSP_SPI_9_MOSI_config = { .outVal = 1, .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_ARD_ADC_4_HSIOM, + .hsiom = CYBSP_SPI_9_MOSI_HSIOM, .intEdge = CY_GPIO_INTR_DISABLE, .intMask = 0UL, .vtrip = CY_GPIO_VTRIP_CMOS, @@ -987,11 +987,11 @@ const cy_stc_gpio_pin_config_t CYBSP_ARD_ADC_4_config = .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, .nonSec = 1, }; -const cy_stc_gpio_pin_config_t CYBSP_ARD_ADC_5_config = +const cy_stc_gpio_pin_config_t CYBSP_SPI_9_MISO_config = { .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_ARD_ADC_5_HSIOM, + .driveMode = CY_GPIO_DM_HIGHZ, + .hsiom = CYBSP_SPI_9_MISO_HSIOM, .intEdge = CY_GPIO_INTR_DISABLE, .intMask = 0UL, .vtrip = CY_GPIO_VTRIP_CMOS, @@ -1005,11 +1005,11 @@ const cy_stc_gpio_pin_config_t CYBSP_ARD_ADC_5_config = .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, .nonSec = 1, }; -const cy_stc_gpio_pin_config_t CYBSP_SPI_CLK_config = +const cy_stc_gpio_pin_config_t CYBSP_ARD_ADC_4_config = { .outVal = 1, .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_SPI_CLK_HSIOM, + .hsiom = CYBSP_ARD_ADC_4_HSIOM, .intEdge = CY_GPIO_INTR_DISABLE, .intMask = 0UL, .vtrip = CY_GPIO_VTRIP_CMOS, @@ -1023,11 +1023,11 @@ const cy_stc_gpio_pin_config_t CYBSP_SPI_CLK_config = .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, .nonSec = 1, }; -const cy_stc_gpio_pin_config_t CYBSP_SPI_MOSI_config = +const cy_stc_gpio_pin_config_t CYBSP_ARD_ADC_5_config = { .outVal = 1, .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_SPI_MOSI_HSIOM, + .hsiom = CYBSP_ARD_ADC_5_HSIOM, .intEdge = CY_GPIO_INTR_DISABLE, .intMask = 0UL, .vtrip = CY_GPIO_VTRIP_CMOS, @@ -1041,11 +1041,11 @@ const cy_stc_gpio_pin_config_t CYBSP_SPI_MOSI_config = .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, .nonSec = 1, }; -const cy_stc_gpio_pin_config_t CYBSP_SPI_MISO_config = +const cy_stc_gpio_pin_config_t CYBSP_SPI_CLK_config = { .outVal = 1, .driveMode = CY_GPIO_DM_HIGHZ, - .hsiom = CYBSP_SPI_MISO_HSIOM, + .hsiom = CYBSP_SPI_CLK_HSIOM, .intEdge = CY_GPIO_INTR_DISABLE, .intMask = 0UL, .vtrip = CY_GPIO_VTRIP_CMOS, @@ -1059,11 +1059,11 @@ const cy_stc_gpio_pin_config_t CYBSP_SPI_MISO_config = .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE, .nonSec = 1, }; -const cy_stc_gpio_pin_config_t CYBSP_SPI_CS_config = +const cy_stc_gpio_pin_config_t CYBSP_SPI_MOSI_config = { .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_SPI_CS_HSIOM, + .driveMode = CY_GPIO_DM_STRONG, + .hsiom = CYBSP_SPI_MOSI_HSIOM, .intEdge = CY_GPIO_INTR_DISABLE, .intMask = 0UL, .vtrip = CY_GPIO_VTRIP_CMOS, @@ -1419,13 +1419,13 @@ void init_cycfg_pins(void) Cy_GPIO_Pin_Init(CYBSP_I2S_TX_FSYNC_PORT, CYBSP_I2S_TX_FSYNC_PIN, &CYBSP_I2S_TX_FSYNC_config); Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_D2_PORT, CYBSP_WIFI_SDIO_D2_PIN, &CYBSP_WIFI_SDIO_D2_config); Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_D3_PORT, CYBSP_WIFI_SDIO_D3_PIN, &CYBSP_WIFI_SDIO_D3_config); - Cy_GPIO_Pin_Init(CYBSP_ADC_6_POT_PORT, CYBSP_ADC_6_POT_PIN, &CYBSP_ADC_6_POT_config); + Cy_GPIO_Pin_Init(CYBSP_SPI_9_CLK_PORT, CYBSP_SPI_9_CLK_PIN, &CYBSP_SPI_9_CLK_config); + Cy_GPIO_Pin_Init(CYBSP_SPI_9_MOSI_PORT, CYBSP_SPI_9_MOSI_PIN, &CYBSP_SPI_9_MOSI_config); + Cy_GPIO_Pin_Init(CYBSP_SPI_9_MISO_PORT, CYBSP_SPI_9_MISO_PIN, &CYBSP_SPI_9_MISO_config); Cy_GPIO_Pin_Init(CYBSP_ARD_ADC_4_PORT, CYBSP_ARD_ADC_4_PIN, &CYBSP_ARD_ADC_4_config); Cy_GPIO_Pin_Init(CYBSP_ARD_ADC_5_PORT, CYBSP_ARD_ADC_5_PIN, &CYBSP_ARD_ADC_5_config); Cy_GPIO_Pin_Init(CYBSP_SPI_CLK_PORT, CYBSP_SPI_CLK_PIN, &CYBSP_SPI_CLK_config); Cy_GPIO_Pin_Init(CYBSP_SPI_MOSI_PORT, CYBSP_SPI_MOSI_PIN, &CYBSP_SPI_MOSI_config); - Cy_GPIO_Pin_Init(CYBSP_SPI_MISO_PORT, CYBSP_SPI_MISO_PIN, &CYBSP_SPI_MISO_config); - Cy_GPIO_Pin_Init(CYBSP_SPI_CS_PORT, CYBSP_SPI_CS_PIN, &CYBSP_SPI_CS_config); Cy_GPIO_Pin_Init(CYBSP_USER_LED3_PORT, CYBSP_USER_LED3_PIN, &CYBSP_USER_LED3_config); Cy_GPIO_Pin_Init(CYBSP_USER_LED2_PORT, CYBSP_USER_LED2_PIN, &CYBSP_USER_LED2_config); Cy_GPIO_Pin_Init(CYBSP_USER_LED1_PORT, CYBSP_USER_LED1_PIN, &CYBSP_USER_LED1_config); diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_pins.h b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_pins.h index e3a07a34..d4a7cad3 100644 --- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_pins.h +++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_pins.h @@ -4,9 +4,9 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. - * Configurator Backend 3.60.0 - * device-db 4.34.0.9502 - * mtb-dsl-pse8xxgp 1.1.1.824 + * Configurator Backend 3.70.0 + * device-db 4.35.0.9884 + * mtb-dsl-pse8xxgp 1.4.0.994 * ******************************************************************************* * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or @@ -782,18 +782,42 @@ extern "C" { #endif #define CYBSP_WIFI_SDIO_D3_HSIOM ioss_0_port_12_pin_5_HSIOM #define CYBSP_WIFI_SDIO_D3_IRQ ioss_interrupts_gpio_12_IRQn -#define CYBSP_ADC_6_POT_ENABLED 1U -#define CYBSP_ADC_6_POT_PORT GPIO_PRT15 -#define CYBSP_ADC_6_POT_PORT_NUM 15U -#define CYBSP_ADC_6_POT_PIN 1U -#define CYBSP_ADC_6_POT_NUM 1U -#define CYBSP_ADC_6_POT_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_ADC_6_POT_INIT_DRIVESTATE 1 +#define CYBSP_SPI_9_CLK_ENABLED 1U +#define CYBSP_SPI_9_CLK_PORT GPIO_PRT15 +#define CYBSP_SPI_9_CLK_PORT_NUM 15U +#define CYBSP_SPI_9_CLK_PIN 0U +#define CYBSP_SPI_9_CLK_NUM 0U +#define CYBSP_SPI_9_CLK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_SPI_9_CLK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_15_pin_0_HSIOM + #define ioss_0_port_15_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SPI_9_CLK_HSIOM ioss_0_port_15_pin_0_HSIOM +#define CYBSP_SPI_9_CLK_IRQ ioss_interrupts_gpio_15_IRQn +#define CYBSP_SPI_9_MOSI_ENABLED 1U +#define CYBSP_SPI_9_MOSI_PORT GPIO_PRT15 +#define CYBSP_SPI_9_MOSI_PORT_NUM 15U +#define CYBSP_SPI_9_MOSI_PIN 1U +#define CYBSP_SPI_9_MOSI_NUM 1U +#define CYBSP_SPI_9_MOSI_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_SPI_9_MOSI_INIT_DRIVESTATE 1 #ifndef ioss_0_port_15_pin_1_HSIOM #define ioss_0_port_15_pin_1_HSIOM HSIOM_SEL_GPIO #endif -#define CYBSP_ADC_6_POT_HSIOM ioss_0_port_15_pin_1_HSIOM -#define CYBSP_ADC_6_POT_IRQ ioss_interrupts_gpio_15_IRQn +#define CYBSP_SPI_9_MOSI_HSIOM ioss_0_port_15_pin_1_HSIOM +#define CYBSP_SPI_9_MOSI_IRQ ioss_interrupts_gpio_15_IRQn +#define CYBSP_SPI_9_MISO_ENABLED 1U +#define CYBSP_SPI_9_MISO_PORT GPIO_PRT15 +#define CYBSP_SPI_9_MISO_PORT_NUM 15U +#define CYBSP_SPI_9_MISO_PIN 2U +#define CYBSP_SPI_9_MISO_NUM 2U +#define CYBSP_SPI_9_MISO_DRIVEMODE CY_GPIO_DM_HIGHZ +#define CYBSP_SPI_9_MISO_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_15_pin_2_HSIOM + #define ioss_0_port_15_pin_2_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SPI_9_MISO_HSIOM ioss_0_port_15_pin_2_HSIOM +#define CYBSP_SPI_9_MISO_IRQ ioss_interrupts_gpio_15_IRQn #define CYBSP_ARD_ADC_4_ENABLED 1U #define CYBSP_ARD_ADC_4_PORT GPIO_PRT15 #define CYBSP_ARD_ADC_4_PORT_NUM 15U @@ -823,7 +847,7 @@ extern "C" { #define CYBSP_SPI_CLK_PORT_NUM 16U #define CYBSP_SPI_CLK_PIN 0U #define CYBSP_SPI_CLK_NUM 0U -#define CYBSP_SPI_CLK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_SPI_CLK_DRIVEMODE CY_GPIO_DM_HIGHZ #define CYBSP_SPI_CLK_INIT_DRIVESTATE 1 #ifndef ioss_0_port_16_pin_0_HSIOM #define ioss_0_port_16_pin_0_HSIOM HSIOM_SEL_GPIO @@ -835,37 +859,13 @@ extern "C" { #define CYBSP_SPI_MOSI_PORT_NUM 16U #define CYBSP_SPI_MOSI_PIN 1U #define CYBSP_SPI_MOSI_NUM 1U -#define CYBSP_SPI_MOSI_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_SPI_MOSI_DRIVEMODE CY_GPIO_DM_STRONG #define CYBSP_SPI_MOSI_INIT_DRIVESTATE 1 #ifndef ioss_0_port_16_pin_1_HSIOM #define ioss_0_port_16_pin_1_HSIOM HSIOM_SEL_GPIO #endif #define CYBSP_SPI_MOSI_HSIOM ioss_0_port_16_pin_1_HSIOM #define CYBSP_SPI_MOSI_IRQ ioss_interrupts_gpio_16_IRQn -#define CYBSP_SPI_MISO_ENABLED 1U -#define CYBSP_SPI_MISO_PORT GPIO_PRT16 -#define CYBSP_SPI_MISO_PORT_NUM 16U -#define CYBSP_SPI_MISO_PIN 2U -#define CYBSP_SPI_MISO_NUM 2U -#define CYBSP_SPI_MISO_DRIVEMODE CY_GPIO_DM_HIGHZ -#define CYBSP_SPI_MISO_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_16_pin_2_HSIOM - #define ioss_0_port_16_pin_2_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_SPI_MISO_HSIOM ioss_0_port_16_pin_2_HSIOM -#define CYBSP_SPI_MISO_IRQ ioss_interrupts_gpio_16_IRQn -#define CYBSP_SPI_CS_ENABLED 1U -#define CYBSP_SPI_CS_PORT GPIO_PRT16 -#define CYBSP_SPI_CS_PORT_NUM 16U -#define CYBSP_SPI_CS_PIN 3U -#define CYBSP_SPI_CS_NUM 3U -#define CYBSP_SPI_CS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_SPI_CS_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_16_pin_3_HSIOM - #define ioss_0_port_16_pin_3_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_SPI_CS_HSIOM ioss_0_port_16_pin_3_HSIOM -#define CYBSP_SPI_CS_IRQ ioss_interrupts_gpio_16_IRQn #define CYBSP_USER_LED3_ENABLED 1U #define CYBSP_LED_BLUE_ENABLED CYBSP_USER_LED3_ENABLED #define CYBSP_USER_LED3_PORT GPIO_PRT16 @@ -1195,13 +1195,13 @@ extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D1_config; extern const cy_stc_gpio_pin_config_t CYBSP_I2S_TX_FSYNC_config; extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D2_config; extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D3_config; -extern const cy_stc_gpio_pin_config_t CYBSP_ADC_6_POT_config; +extern const cy_stc_gpio_pin_config_t CYBSP_SPI_9_CLK_config; +extern const cy_stc_gpio_pin_config_t CYBSP_SPI_9_MOSI_config; +extern const cy_stc_gpio_pin_config_t CYBSP_SPI_9_MISO_config; extern const cy_stc_gpio_pin_config_t CYBSP_ARD_ADC_4_config; extern const cy_stc_gpio_pin_config_t CYBSP_ARD_ADC_5_config; extern const cy_stc_gpio_pin_config_t CYBSP_SPI_CLK_config; extern const cy_stc_gpio_pin_config_t CYBSP_SPI_MOSI_config; -extern const cy_stc_gpio_pin_config_t CYBSP_SPI_MISO_config; -extern const cy_stc_gpio_pin_config_t CYBSP_SPI_CS_config; extern const cy_stc_gpio_pin_config_t CYBSP_USER_LED3_config; #define CYBSP_LED_BLUE_config CYBSP_USER_LED3_config diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_protection.c b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_protection.c index 83a35889..45e6b0ea 100644 --- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_protection.c +++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_protection.c @@ -4,9 +4,9 @@ * Description: * System configuration * This file was automatically generated and should not be modified. - * Configurator Backend 3.60.0 - * device-db 4.34.0.9502 - * mtb-dsl-pse8xxgp 1.1.1.824 + * Configurator Backend 3.70.0 + * device-db 4.35.0.9884 + * mtb-dsl-pse8xxgp 1.4.0.994 * ******************************************************************************* * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or @@ -29,6 +29,11 @@ #include "cycfg_protection.h" #include "cycfg_system.h" +#if (CY_SYSTEM_CPU_M33) && defined(COMPONENT_SECURE_DEVICE) && defined(CY_PDL_TZ_ENABLED) +#include "cycfg_ppc.h" +#include "ifx_se_platform.h" +#endif /* (CY_SYSTEM_CPU_M33) && defined(COMPONENT_SECURE_DEVICE) && defined(CY_PDL_TZ_ENABLED) */ + void init_cycfg_protection(void) { #if (CY_SYSTEM_CPU_M33) && defined(COMPONENT_SECURE_DEVICE) && !defined(CYBSP_SKIP_SAU_INIT) @@ -37,6 +42,9 @@ void init_cycfg_protection(void) #if (CY_SYSTEM_CPU_M33) && defined(COMPONENT_SECURE_DEVICE) && defined(CY_PDL_TZ_ENABLED) && !defined(CYBSP_SKIP_MPC_INIT) init_cycfg_mpc(); #endif /* (CY_SYSTEM_CPU_M33) && defined(COMPONENT_SECURE_DEVICE) && defined(CY_PDL_TZ_ENABLED) && !defined(CYBSP_SKIP_MPC_INIT) */ +#if (CY_SYSTEM_CPU_M33) && defined(COMPONENT_SECURE_DEVICE) && defined(CY_PDL_TZ_ENABLED) && !defined(CYCFG_PROTECTION_SE_ENABLE) && !defined(CYBSP_SKIP_PPC_INIT) + ifx_se_disable(NULL); +#endif /* (CY_SYSTEM_CPU_M33) && defined(COMPONENT_SECURE_DEVICE) && defined(CY_PDL_TZ_ENABLED) && !defined(CYCFG_PROTECTION_SE_ENABLE) && !defined(CYBSP_SKIP_PPC_INIT) */ #if (CY_SYSTEM_CPU_M33) && defined(COMPONENT_SECURE_DEVICE) && defined(CY_PDL_TZ_ENABLED) && !defined(CYBSP_SKIP_PPC_INIT) init_cycfg_ppc0(); init_cycfg_ppc1(); diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_protection.h b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_protection.h index 4aea91aa..8a16edca 100644 --- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_protection.h +++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_protection.h @@ -4,9 +4,9 @@ * Description: * System configuration * This file was automatically generated and should not be modified. - * Configurator Backend 3.60.0 - * device-db 4.34.0.9502 - * mtb-dsl-pse8xxgp 1.1.1.824 + * Configurator Backend 3.70.0 + * device-db 4.35.0.9884 + * mtb-dsl-pse8xxgp 1.4.0.994 * ******************************************************************************* * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_qspi_memslot.c b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_qspi_memslot.c index c19390f2..23f3ec70 100644 --- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_qspi_memslot.c +++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_qspi_memslot.c @@ -4,7 +4,7 @@ * Description: * Provides definitions of the SMIF-driver memory configuration. * This file was automatically generated and should not be modified. - * QSPI Configurator 4.60.0.2742 + * QSPI Configurator 4.70.0.2834 * ******************************************************************************* * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_qspi_memslot.h b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_qspi_memslot.h index 3d8e8f9b..d9e92565 100644 --- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_qspi_memslot.h +++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_qspi_memslot.h @@ -4,7 +4,7 @@ * Description: * Provides declarations of the SMIF-driver memory configuration. * This file was automatically generated and should not be modified. - * QSPI Configurator 4.60.0.2742 + * QSPI Configurator 4.70.0.2834 * ******************************************************************************* * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or @@ -28,7 +28,7 @@ #define CYCFG_QSPI_MEMSLOT_H #include "cy_smif_memslot.h" -#define CY_SMIF_CFG_TOOL_VERSION (460) +#define CY_SMIF_CFG_TOOL_VERSION (470) /* Supported QSPI Driver version */ #define CY_SMIF_DRV_VERSION_REQUIRED (100) diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_qspi_memslot.timestamp b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_qspi_memslot.timestamp index 8d7d13aa..b006ed11 100644 --- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_qspi_memslot.timestamp +++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_qspi_memslot.timestamp @@ -4,7 +4,7 @@ * Description: * Sentinel file for determining if generated source is up to date. * This file was automatically generated and should not be modified. - * QSPI Configurator 4.60.0.2742 + * QSPI Configurator 4.70.0.2834 * ******************************************************************************* * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_routing.c b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_routing.c deleted file mode 100644 index 163308e3..00000000 --- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_routing.c +++ /dev/null @@ -1,37 +0,0 @@ -/******************************************************************************* - * File Name: cycfg_routing.c - * - * Description: - * Establishes all necessary connections between hardware elements. - * This file was automatically generated and should not be modified. - * Configurator Backend 3.60.0 - * device-db 4.34.0.9502 - * mtb-dsl-pse8xxgp 1.1.1.824 - * - ******************************************************************************* - * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or - * an affiliate of Cypress Semiconductor Corporation. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - ******************************************************************************/ - -#include "cycfg_routing.h" -#include "cy_trigmux.h" -#include "stdbool.h" -#include "cy_device_headers.h" - -void init_cycfg_routing(void) -{ - Cy_TrigMux_Connect(PERI_0_TRIG_IN_MUX_0_SCB_TX_TR_OUT10, PERI_0_TRIG_OUT_MUX_0_PDMA0_TR_IN1, false, TRIGGER_TYPE_LEVEL); -} diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_routing.h b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_routing.h index 7921e5a1..0e35ecfb 100644 --- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_routing.h +++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_routing.h @@ -4,9 +4,9 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. - * Configurator Backend 3.60.0 - * device-db 4.34.0.9502 - * mtb-dsl-pse8xxgp 1.1.1.824 + * Configurator Backend 3.70.0 + * device-db 4.35.0.9884 + * mtb-dsl-pse8xxgp 1.4.0.994 * ******************************************************************************* * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or @@ -64,10 +64,11 @@ extern "C" { #define ioss_0_port_12_pin_3_HSIOM P12_3_TDM_TDM_TX_FSYNC0 #define ioss_0_port_12_pin_4_HSIOM P12_4_SDHC0_CARD_DAT_3TO02 #define ioss_0_port_12_pin_5_HSIOM P12_5_SDHC0_CARD_DAT_3TO03 -#define ioss_0_port_16_pin_0_HSIOM P16_0_SCB10_SPI_CLK -#define ioss_0_port_16_pin_1_HSIOM P16_1_SCB10_SPI_MOSI -#define ioss_0_port_16_pin_2_HSIOM P16_2_SCB10_SPI_MISO -#define ioss_0_port_16_pin_3_HSIOM P16_3_SCB10_SPI_SELECT0 +#define ioss_0_port_15_pin_0_HSIOM P15_0_SCB9_SPI_CLK +#define ioss_0_port_15_pin_1_HSIOM P15_1_SCB9_SPI_MOSI +#define ioss_0_port_15_pin_2_HSIOM P15_2_SCB9_SPI_MISO +#define ioss_0_port_16_pin_0_HSIOM P16_0_CANFD0_TTCAN_RX0 +#define ioss_0_port_16_pin_1_HSIOM P16_1_CANFD0_TTCAN_TX0 #define ioss_0_port_16_pin_5_HSIOM P16_5_TCPWM0_LINE5 #define ioss_0_port_17_pin_0_HSIOM P17_0_SCB5_UART_RX #define ioss_0_port_17_pin_1_HSIOM P17_1_SCB5_UART_TX @@ -76,10 +77,8 @@ extern "C" { #define ioss_0_port_21_pin_1_HSIOM P21_1_TDM_TDM_TX_SD0 #define ioss_0_port_21_pin_2_HSIOM P21_2_TDM_TDM_TX_SCK0 #define ioss_0_port_21_pin_3_HSIOM P21_3_TDM_TDM_TX_MCK0 -#define CYBSP_DMA_TX_SPI_CONTROLLER_tr_in_0_TRIGGER_OUT PERI_0_TRIG_OUT_MUX_0_PDMA0_TR_IN1 -#define CYBSP_SPI_CONTROLLER_tr_tx_req_0_TRIGGER_IN PERI_0_TRIG_IN_MUX_0_SCB_TX_TR_OUT10 -void init_cycfg_routing(void); +static inline void init_cycfg_routing(void) {} #if defined(__cplusplus) } diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_system.c b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_system.c index eac5cb5a..b3ec03ea 100644 --- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_system.c +++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_system.c @@ -4,9 +4,9 @@ * Description: * System configuration * This file was automatically generated and should not be modified. - * Configurator Backend 3.60.0 - * device-db 4.34.0.9502 - * mtb-dsl-pse8xxgp 1.1.1.824 + * Configurator Backend 3.70.0 + * device-db 4.35.0.9884 + * mtb-dsl-pse8xxgp 1.4.0.994 * ******************************************************************************* * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or @@ -1261,11 +1261,13 @@ cy_rslt_t cycfg_ppc_init_unsecure(PPC_Type* base, const cy_en_prot_region_t regi } cy_rslt_t init_cycfg_ppc0(void) { - return cycfg_ppc_init_unsecure(PPC0, cycfg_unused_ppc_0_regions, cycfg_unused_ppc_0_regions_count); + cy_rslt_t ret = cycfg_ppc_init_unsecure(PPC0, cycfg_unused_ppc_0_regions, cycfg_unused_ppc_0_regions_count); + return ret; } cy_rslt_t init_cycfg_ppc1(void) { - return cycfg_ppc_init_unsecure(PPC1, cycfg_unused_ppc_1_regions, cycfg_unused_ppc_1_regions_count); + cy_rslt_t ret = cycfg_ppc_init_unsecure(PPC1, cycfg_unused_ppc_1_regions, cycfg_unused_ppc_1_regions_count); + return ret; } void init_cycfg_system(void) { diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_system.h b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_system.h index 72f8daa9..f8b2c52b 100644 --- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_system.h +++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_system.h @@ -4,9 +4,9 @@ * Description: * System configuration * This file was automatically generated and should not be modified. - * Configurator Backend 3.60.0 - * device-db 4.34.0.9502 - * mtb-dsl-pse8xxgp 1.1.1.824 + * Configurator Backend 3.70.0 + * device-db 4.35.0.9884 + * mtb-dsl-pse8xxgp 1.4.0.994 * ******************************************************************************* * Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/device_mem.json b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/device_mem.json new file mode 100644 index 00000000..1e747eb9 --- /dev/null +++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/device_mem.json @@ -0,0 +1,47 @@ +{ + "version" : 1.0, + "memoryData" : + { + "physical" : + [ + { "name" : "CM55_DTCM_INTERNAL", "size" : "0x00040000", "start" : [ "0x48040000", "0x58040000", "0x20000000" ] }, + { "name" : "CM55_ITCM_INTERNAL", "size" : "0x00040000", "start" : [ "0x48000000", "0x58000000", "0x00000000" ] }, + { "name" : "RRAM", "size" : "0x00080000", "start" : [ "0x22000000", "0x02000000", "0x12000000", "0x32000000" ] }, + { "name" : "SMIF0MEM1", "size" : "0x01000000", "start" : [ "0x60000000", "0x08000000", "0x18000000", "0x70000000" ] }, + { "name" : "SMIF1MEM2", "size" : "0x01000000", "start" : [ "0x64000000", "0x0C000000", "0x1C000000", "0x74000000" ] }, + { "name" : "SOCMEM_RAM", "size" : "0x00500000", "start" : [ "0x26000000", "0x06000000", "0x16000000", "0x36000000" ] }, + { "name" : "SRAM", "size" : "0x00100000", "start" : [ "0x24000000", "0x04000000", "0x14000000", "0x34000000" ] } + ], + "region" : + [ + { "name" : "m55_data", "size" : "0x00040000", "start" : [ "0x48040000", "0x58040000", "0x20000000" ] }, + { "name" : "m55_code", "size" : "0x00040000", "start" : [ "0x48000000", "0x58000000", "0x00000000" ] }, + { "name" : "extended_boot_reserved", "size" : "0x00011000", "start" : [ "0x22000000", "0x02000000", "0x12000000", "0x32000000" ], "reserved" : true }, + { "name" : "user_programmable", "size" : "0x0004A000", "start" : [ "0x22011000", "0x02011000", "0x12011000", "0x32011000" ] }, + { "name" : "user_nvm", "size" : "0x00008000", "start" : [ "0x2205B000", "0x0205B000", "0x1205B000", "0x3205B000" ] }, + { "name" : "reserved_region", "size" : "0x00016000", "start" : [ "0x2206A000", "0x0206A000", "0x1206A000", "0x3206A000" ], "reserved" : true }, + { "name" : "m33s_nvm", "size" : "0x00200000", "start" : [ "0x60100000", "0x08100000", "0x18100000", "0x70100000" ] }, + { "name" : "m33s_trailer", "size" : "0x00040000", "start" : [ "0x60300000", "0x08300000", "0x18300000", "0x70300000" ] }, + { "name" : "m33_nvm", "size" : "0x00200000", "start" : [ "0x60340000", "0x08340000", "0x18340000", "0x70340000" ] }, + { "name" : "m33_trailer", "size" : "0x00040000", "start" : [ "0x60540000", "0x08540000", "0x18540000", "0x70540000" ] }, + { "name" : "m55_nvm", "size" : "0x00A00000", "start" : [ "0x60580000", "0x08580000", "0x18580000", "0x70580000" ] }, + { "name" : "m55_trailer", "size" : "0x00040000", "start" : [ "0x60F80000", "0x08F80000", "0x18F80000", "0x70F80000" ] }, + { "name" : "m33_hyerram", "size" : "0x00200000", "start" : [ "0x64000000", "0x0C000000", "0x1C000000", "0x74000000" ] }, + { "name" : "m55_hyperram", "size" : "0x00200000", "start" : [ "0x64200000", "0x0C200000", "0x1C200000", "0x74200000" ] }, + { "name" : "m33_m55_shared_hyperram", "size" : "0x00C00000", "start" : [ "0x64400000", "0x0C400000", "0x1C400000", "0x74400000" ] }, + { "name" : "m55_code_secondary", "size" : "0x00060000", "start" : [ "0x26000000", "0x06000000", "0x16000000", "0x36000000" ] }, + { "name" : "m55_data_secondary", "size" : "0x00160000", "start" : [ "0x26060000", "0x06060000", "0x16060000", "0x36060000" ] }, + { "name" : "m33_m55_shared", "size" : "0x00040000", "start" : [ "0x261C0000", "0x061C0000", "0x161C0000", "0x361C0000" ] }, + { "name" : "gfx_mem", "size" : "0x00300000", "start" : [ "0x26200000", "0x06200000", "0x16200000", "0x36200000" ] }, + { "name" : "extended_boot_sram_reserved", "size" : "0x00001000", "start" : [ "0x24000000", "0x04000000", "0x14000000", "0x34000000" ], "reserved" : true }, + { "name" : "m33s_shared", "size" : "0x00001000", "start" : [ "0x24001000", "0x04001000", "0x14001000", "0x34001000" ] }, + { "name" : "m33s_code", "size" : "0x00035000", "start" : [ "0x24002000", "0x04002000", "0x14002000", "0x34002000" ] }, + { "name" : "m33s_data", "size" : "0x00021000", "start" : [ "0x24037000", "0x04037000", "0x14037000", "0x34037000" ] }, + { "name" : "m33_code", "size" : "0x00065000", "start" : [ "0x24058000", "0x04058000", "0x14058000", "0x34058000" ] }, + { "name" : "m33_data", "size" : "0x00040000", "start" : [ "0x240BD000", "0x040BD000", "0x140BD000", "0x340BD000" ] }, + { "name" : "m33s_allocatable_shared", "size" : "0x00001000", "start" : [ "0x240FD000", "0x040FD000", "0x140FD000", "0x340FD000" ] }, + { "name" : "m33_allocatable_shared", "size" : "0x00001000", "start" : [ "0x240FE000", "0x040FE000", "0x140FE000", "0x340FE000" ] }, + { "name" : "m55_allocatable_shared", "size" : "0x00001000", "start" : [ "0x240FF000", "0x040FF000", "0x140FF000", "0x340FF000" ] } + ] + } +} diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/qspi_config.cfg b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/qspi_config.cfg index dca59607..288637d5 100644 --- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/qspi_config.cfg +++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/qspi_config.cfg @@ -4,7 +4,7 @@ # Description: # This file contains a SMIF Bank layout for use with OpenOCD. # This file was automatically generated and should not be modified. -# QSPI Configurator: 4.60.0.2742 +# QSPI Configurator: 4.70.0.2834 # ################################################################################ # Copyright 2026 Cypress Semiconductor Corporation (an Infineon company) or diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/design.modus b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/design.modus index fce4144c..e0559226 100644 --- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/design.modus +++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/design.modus @@ -1,13 +1,8 @@ - + - - - - - @@ -215,17 +210,6 @@ - - - - - - - - - - - @@ -241,6 +225,16 @@ + + + + + + + + + + @@ -323,6 +317,2016 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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@@ -4371,7 +6340,7 @@ - + @@ -4381,10 +6350,6 @@ - - - - @@ -4425,6 +6390,11 @@ + + + + + diff --git a/sdk-bsp-psoc_e84-edgi-talk.yaml b/sdk-bsp-psoc_e84-edgi-talk.yaml index 23eeb7de..aefffb7f 100644 --- a/sdk-bsp-psoc_e84-edgi-talk.yaml +++ b/sdk-bsp-psoc_e84-edgi-talk.yaml @@ -395,6 +395,80 @@ example_projects: target_path_offset: '' files_and_folders: [] +- project_name: Edgi_Talk_M33_IPC + project_description: M33 双核通信示例 + project_type: rt-thread|@full|@5.0.2 + builtin_files: + - source_path_offset: 'projects/Edgi_Talk_IPC/Edgi_Talk_M33_IPC' + target_path_offset: '' + files_and_folders: + - "*" + - source_path_offset: 'projects/' + target_path_offset: '' + files_and_folders: + - libs + - source_path_offset: '' + target_path_offset: '' + files_and_folders: + - libraries + - rt-thread + - source_path_offset: 'tools' + target_path_offset: 'tools' + files_and_folders: + - "*" + external_files: + - package_name: GNU_Tools_for_ARM_Embedded_Processors + package_type: ToolChain_Support_Packages + package_vendor: 'ARM' + package_version: '13.3' + source_path_offset: '.' + target_path_offset: '.' + files_and_folders: [] + - package_name: OpenOCD-Infineon + package_type: Debugger_Support_Packages + package_vendor: 'Infineon' + package_version: '2.0.0' + source_path_offset: '' + target_path_offset: '' + files_and_folders: [] + +- project_name: Edgi_Talk_M55_IPC + project_description: M55 双核通信示例 + project_type: rt-thread|@full|@5.0.2 + builtin_files: + - source_path_offset: 'projects/Edgi_Talk_IPC/Edgi_Talk_M55_IPC' + target_path_offset: '' + files_and_folders: + - "*" + - source_path_offset: 'projects/' + target_path_offset: '' + files_and_folders: + - libs + - source_path_offset: '' + target_path_offset: '' + files_and_folders: + - libraries + - rt-thread + - source_path_offset: 'tools' + target_path_offset: 'tools' + files_and_folders: + - "*" + external_files: + - package_name: GNU_Tools_for_ARM_Embedded_Processors + package_type: ToolChain_Support_Packages + package_vendor: 'ARM' + package_version: '13.3' + source_path_offset: '.' + target_path_offset: '.' + files_and_folders: [] + - package_name: OpenOCD-Infineon + package_type: Debugger_Support_Packages + package_vendor: 'Infineon' + package_version: '2.0.0' + source_path_offset: '' + target_path_offset: '' + files_and_folders: [] + - project_name: Edgi_Talk_Extend_Screen project_description: M55 CherryUSB USB 拓展屏幕示例 project_type: rt-thread|@full|@5.0.2 diff --git a/tools/edgeprotecttools/cm33_s_signed_fw/proj_cm33_s_signed.hex b/tools/edgeprotecttools/cm33_s_signed_fw/proj_cm33_s_signed.hex index d76ce16d..8fb92726 100644 --- a/tools/edgeprotecttools/cm33_s_signed_fw/proj_cm33_s_signed.hex +++ b/tools/edgeprotecttools/cm33_s_signed_fw/proj_cm33_s_signed.hex @@ -1,5 +1,5 @@ :0200000470107A -:100000003DB8F39600000000000400008C8B010056 +:100000003DB8F3960000000000040000648A01007F :10001000000000000000000000000000FFFFFFFFE4 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