diff --git a/.github/workflows/action.yml b/.github/workflows/action.yml index 0c42e682..adc79779 100644 --- a/.github/workflows/action.yml +++ b/.github/workflows/action.yml @@ -76,6 +76,7 @@ jobs: - {RTT_BSP: "etherkit_profinet_pnet"} - {RTT_BSP: "etherkit_ethernetip_opener"} - {RTT_BSP: "etherkit_factory"} + - {RTT_BSP: "etherkit_ethercat_cherryecat"} steps: - uses: actions/checkout@v2 - name: Set up Python diff --git a/README.md b/README.md index c9f5aee7..1c09152c 100644 --- a/README.md +++ b/README.md @@ -34,6 +34,7 @@ $ sdk-bsp-rzn2l-etherkit │ ├── etherkit_driver_rs485 │ ├── etherkit_driver_spi │ ├── etherkit_driver_wdt +│ ├── etherkit_ethercat_cherryecat │ ├── etherkit_driver_hyperram │ ├── etherkit_ethernet │ ├── etherkit_usb_pcdc diff --git a/README_zh.md b/README_zh.md index 412dcacd..d64590b0 100644 --- a/README_zh.md +++ b/README_zh.md @@ -36,6 +36,7 @@ $ sdk-bsp-rzn2l-etherkit │ ├── etherkit_driver_rs485 │ ├── etherkit_driver_spi │ ├── etherkit_driver_wdt +│ ├── etherkit_ethercat_cherryecat │ ├── etherkit_driver_hyperram │ ├── etherkit_ethernet │ ├── etherkit_usb_pcdc diff --git a/projects/etherkit_driver_ethernet/project.ewp b/projects/etherkit_driver_ethernet/project.ewp index 87d72760..4497ca44 100644 --- a/projects/etherkit_driver_ethernet/project.ewp +++ b/projects/etherkit_driver_ethernet/project.ewp @@ -1,2823 +1,2822 @@ + - 4 - - Debug - - ARM - - 1 - - General - 3 - - 36 - 1 + 4 + + Debug + + ARM + 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 38 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 12 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - 1 - inputOutputBased - - - - ILINK - 0 - - 27 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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$PROJ_DIR$\rzn\fsp\src\bsp\mcu\rzn2l\bsp_loader_param.c - - - $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\cr\bsp_delay_core.c - - - - RZN_cfg - - - RZN_gen - - $PROJ_DIR$\rzn_gen\vector_data.c - - - $PROJ_DIR$\rzn_gen\hal_data.c - - - $PROJ_DIR$\rzn_gen\common_data.c - - - $PROJ_DIR$\rzn_gen\main.c - - - $PROJ_DIR$\rzn_gen\pin_data.c - - - - SAL - - $PROJ_DIR$\rt-thread\components\net\netdev\src\netdev.c - - - $PROJ_DIR$\rt-thread\components\net\netdev\src\netdev_ipaddr.c - - - $PROJ_DIR$\rt-thread\components\net\sal\impl\af_inet_lwip.c - - - $PROJ_DIR$\rt-thread\components\net\sal\socket\net_netdb.c - - - $PROJ_DIR$\rt-thread\components\net\sal\src\sal_socket.c + + General + 3 + + 36 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 38 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + 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$RASC_DEVICE_FAMILY$ "$PROJ_DIR$\configuration.xml" "$TARGET_PATH$" 2> "$BUILD_FILES_DIR$\.rasc_stderr.txt"" + $PROJ_DIR$ + postLink + + + $TARGET_BPATH$.sbd + + + + + $TARGET_PATH$ + + + + + + + + + Applications + + $PROJ_DIR$\src\hal_entry.c + + + + Compiler + + $PROJ_DIR$\rt-thread\components\libc\compilers\common\cctype.c + + + $PROJ_DIR$\rt-thread\components\libc\compilers\common\cstdlib.c + + + $PROJ_DIR$\rt-thread\components\libc\compilers\common\cstring.c + + + $PROJ_DIR$\rt-thread\components\libc\compilers\common\ctime.c + + + $PROJ_DIR$\rt-thread\components\libc\compilers\common\cunistd.c + + + $PROJ_DIR$\rt-thread\components\libc\compilers\common\cwchar.c + + + $PROJ_DIR$\rt-thread\components\libc\compilers\dlib\environ.c + + + $PROJ_DIR$\rt-thread\components\libc\compilers\dlib\syscall_close.c + + + $PROJ_DIR$\rt-thread\components\libc\compilers\dlib\syscall_lseek.c + + + $PROJ_DIR$\rt-thread\components\libc\compilers\dlib\syscall_mem.c + + + $PROJ_DIR$\rt-thread\components\libc\compilers\dlib\syscall_open.c + + + $PROJ_DIR$\rt-thread\components\libc\compilers\dlib\syscall_read.c + + + $PROJ_DIR$\rt-thread\components\libc\compilers\dlib\syscall_remove.c + + + $PROJ_DIR$\rt-thread\components\libc\compilers\dlib\syscall_write.c + + + $PROJ_DIR$\rt-thread\components\libc\compilers\dlib\syscalls.c + + + + CPU + + $PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\backtrace.c + + + $PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\context_iar.S + + + $PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\cpuport.c + + + $PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\gicv3.c + + + $PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\interrupt.c + + + $PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\stack.c + + + $PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\start_iar.S + + + $PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\trap.c + + + $PROJ_DIR$\rt-thread\libcpu\arm\cortex-r52\vector_iar.S + + + + DeviceDrivers + + $PROJ_DIR$\rt-thread\components\drivers\ipc\completion.c + + + $PROJ_DIR$\rt-thread\components\drivers\ipc\condvar.c + + + $PROJ_DIR$\rt-thread\components\drivers\ipc\dataqueue.c + + + $PROJ_DIR$\rt-thread\components\drivers\core\device.c + + + $PROJ_DIR$\rt-thread\components\drivers\pin\pin.c + + + $PROJ_DIR$\rt-thread\components\drivers\ipc\pipe.c + + + $PROJ_DIR$\rt-thread\components\drivers\ipc\ringblk_buf.c + + + $PROJ_DIR$\rt-thread\components\drivers\ipc\ringbuffer.c + + + $PROJ_DIR$\rt-thread\components\drivers\serial\serial_v2.c + + + $PROJ_DIR$\rt-thread\components\drivers\ipc\waitqueue.c + + + $PROJ_DIR$\rt-thread\components\drivers\ipc\workqueue.c + + + + Drivers + + $PROJ_DIR$\libraries\HAL_Drivers\drv_common.c + + + $PROJ_DIR$\libraries\HAL_Drivers\drv_eth.c + + + $PROJ_DIR$\libraries\HAL_Drivers\drv_gpio.c + + + $PROJ_DIR$\libraries\HAL_Drivers\drv_usart_v2.c + + + + Finsh + + $PROJ_DIR$\rt-thread\components\finsh\cmd.c + + + $PROJ_DIR$\rt-thread\components\finsh\msh.c + + + $PROJ_DIR$\rt-thread\components\finsh\msh_parse.c + + + $PROJ_DIR$\rt-thread\components\finsh\shell.c + + + + Kernel + + $PROJ_DIR$\rt-thread\src\clock.c + + + $PROJ_DIR$\rt-thread\src\components.c + + + $PROJ_DIR$\rt-thread\src\idle.c + + + $PROJ_DIR$\rt-thread\src\ipc.c + + + $PROJ_DIR$\rt-thread\src\irq.c + + + $PROJ_DIR$\rt-thread\src\kservice.c + + + $PROJ_DIR$\rt-thread\src\klibc\kstdio.c + + + $PROJ_DIR$\rt-thread\src\klibc\kstring.c + + + $PROJ_DIR$\rt-thread\src\mem.c + + + $PROJ_DIR$\rt-thread\src\mempool.c + + + $PROJ_DIR$\rt-thread\src\object.c + + + $PROJ_DIR$\rt-thread\src\scheduler_comm.c + + + $PROJ_DIR$\rt-thread\src\scheduler_up.c + + + $PROJ_DIR$\rt-thread\src\thread.c + + + $PROJ_DIR$\rt-thread\src\timer.c + + + + libcpu + + $PROJ_DIR$\rt-thread\libcpu\arm\common\atomic_arm.c + + + $PROJ_DIR$\rt-thread\libcpu\arm\common\div0.c + + + $PROJ_DIR$\rt-thread\libcpu\arm\common\showmem.c + + + + lwIP + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\api\api_lib.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\api\api_msg.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\ipv4\autoip.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\def.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\ipv4\dhcp.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\dns.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\api\err.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\ipv4\etharp.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\netif\ethernet.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\port\ethernetif.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\ipv4\icmp.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\ipv4\igmp.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\inet_chksum.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\init.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\ip.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\ipv4\ip4.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\ipv4\ip4_addr.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\ipv4\ip4_frag.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\netif\lowpan6.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\memp.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\api\netbuf.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\api\netdb.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\netif.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\api\netifapi.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\pbuf.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\apps\ping\ping.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\raw.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\api\sockets.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\stats.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\sys.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\port\sys_arch.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\tcp.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\tcp_in.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\tcp_out.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\api\tcpip.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\timeouts.c + + + $PROJ_DIR$\rt-thread\components\net\lwip\lwip-2.0.3\src\core\udp.c + + + + POSIX + + + RZN + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_address_expander.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_cache.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\cr\bsp_cache_core.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_clocks.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_common.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_ddr.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_ddr_fw_param.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_delay.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\cr\bsp_delay_core.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_io.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_irq.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\cr\bsp_irq_core.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\rzn2l\bsp_irq_sense.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\rzn2l\bsp_loader_param.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_register_protection.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_reset.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_sbrk.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_semaphore.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_slave_stop.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_tzc400.c + + + $PROJ_DIR$\rzn\fsp\src\r_ether_phy\r_ether_phy.c + + + $PROJ_DIR$\rzn\fsp\src\r_ether_selector\r_ether_selector.c + + + $PROJ_DIR$\rzn\fsp\src\r_ethsw\r_ethsw.c + + + $PROJ_DIR$\rzn\fsp\src\r_gmac\r_gmac.c + + + $PROJ_DIR$\rzn\fsp\src\r_ioport\r_ioport.c + + + $PROJ_DIR$\rzn\fsp\src\r_sci_uart\r_sci_uart.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\cmsis\Device\RENESAS\Source\startup.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\cmsis\Device\RENESAS\Source\cr\startup_core.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\cmsis\Device\RENESAS\Source\system.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\cmsis\Device\RENESAS\Source\cr\system_core.c + + + + RZN_cfg + + + RZN_gen + + $PROJ_DIR$\rzn_gen\common_data.c + + + $PROJ_DIR$\rzn_gen\hal_data.c + + + $PROJ_DIR$\rzn_gen\main.c + + + $PROJ_DIR$\rzn_gen\pin_data.c + + + $PROJ_DIR$\rzn_gen\vector_data.c + + + + SAL + + $PROJ_DIR$\rt-thread\components\net\sal\impl\af_inet_lwip.c + + + $PROJ_DIR$\rt-thread\components\net\sal\socket\net_netdb.c + + + $PROJ_DIR$\rt-thread\components\net\netdev\src\netdev.c + + + $PROJ_DIR$\rt-thread\components\net\netdev\src\netdev_ipaddr.c + + + $PROJ_DIR$\rt-thread\components\net\sal\src\sal_socket.c + + + + $PROJ_DIR$\buildinfo.ipcf + IAR.ControlFile - diff --git a/projects/etherkit_ethercat_cherryecat/.api_xml b/projects/etherkit_ethercat_cherryecat/.api_xml new file mode 100644 index 00000000..fc9bf0b3 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/.api_xml @@ -0,0 +1,2 @@ + + diff --git a/projects/etherkit_ethercat_cherryecat/.config b/projects/etherkit_ethercat_cherryecat/.config new file mode 100644 index 00000000..3f43f787 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/.config @@ -0,0 +1,1332 @@ + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=16 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=1024 +# CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +CONFIG_RT_KPRINTF_USING_LONGLONG=y +# end of kservice optimization + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +# CONFIG_RT_USING_SCHED_THREAD_CTX is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=512 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x50100 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_RT_USING_HW_ATOMIC=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_R=y +CONFIG_ARCH_ARM_CORTEX_R52=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_USING_SERIAL_V1 is not set +CONFIG_RT_USING_SERIAL_V2=y +CONFIG_RT_SERIAL_USING_DMA=y +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +CONFIG_RT_USING_HWTIMER=y + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +# CONFIG_RT_LIBC_USING_LIGHT_TZ_DST is not set +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# CONFIG_RT_USING_VBUS is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +CONFIG_PKG_USING_CHERRYECAT=y +# CONFIG_PKG_CHERRYECAT_NETDEV_CUSTOM is not set +# CONFIG_PKG_CHERRYECAT_NETDEV_HPMICRO is not set +CONFIG_PKG_CHERRYECAT_NETDEV_RENESAS=y +CONFIG_PKG_CHERRYECAT_PATH="/packages/system/CherryECAT" +CONFIG_PKG_USING_CHERRYECAT_LATEST_VERSION=y +CONFIG_PKG_CHERRYECAT_VER="latest" +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_MM32 is not set + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers + +# +# HC32 DDL Drivers +# +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set +# end of HC32 DDL Drivers + +# +# NXP HAL & SDK Drivers +# +# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set +# end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# CONFIG_PKG_USING_QMI8658 is not set +# CONFIG_PKG_USING_ICM20948 is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SEAN_WS2812B is not set +# CONFIG_PKG_USING_IC74HC165 is not set +# CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +CONFIG_SOC_FAMILY_RENESAS_RZ=y +CONFIG_SOC_SERIES_R9A07G0=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_R9A07G084=y + +# +# Onboard Peripheral Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_ONCHIP_RTC is not set +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_UART0_RX_USING_DMA is not set +# CONFIG_BSP_UART0_TX_USING_DMA is not set +CONFIG_BSP_UART0_RX_BUFSIZE=256 +CONFIG_BSP_UART0_TX_BUFSIZE=0 +# CONFIG_BSP_USING_UART5 is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_CANFD is not set +# CONFIG_BSP_USING_SCI is not set +# CONFIG_BSP_USING_HYPERRAM is not set +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_TIM is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_ETH is not set +# end of On-chip Peripheral Drivers + +# +# Board extended module Drivers +# +# CONFIG_BSP_USING_RW007 is not set +# end of Board extended module Drivers +# end of Hardware Drivers Config diff --git a/projects/etherkit_ethercat_cherryecat/.cproject b/projects/etherkit_ethercat_cherryecat/.cproject new file mode 100644 index 00000000..319b0e6e --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/.cproject @@ -0,0 +1,233 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/etherkit_ethercat_cherryecat/.gitignore b/projects/etherkit_ethercat_cherryecat/.gitignore new file mode 100644 index 00000000..4a339a10 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/.gitignore @@ -0,0 +1,14 @@ +/RTE +/Listings +/Objects +/Debug +/build +/makefile.targets +/rtconfig.pyc +/rt-thread +/libraries +/project.custom_argvars +/.vscode +/__pycache +/settings +/rtconfig_preinc.h \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/.project b/projects/etherkit_ethercat_cherryecat/.project new file mode 100644 index 00000000..2fca752f --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/.project @@ -0,0 +1,28 @@ + + + project + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.rt-thread.studio.rttnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + diff --git a/projects/etherkit_ethercat_cherryecat/.secure_azone b/projects/etherkit_ethercat_cherryecat/.secure_azone new file mode 100644 index 00000000..585ba89c --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/.secure_azone @@ -0,0 +1,4 @@ + + + + diff --git a/projects/etherkit_ethercat_cherryecat/.secure_rzone b/projects/etherkit_ethercat_cherryecat/.secure_rzone new file mode 100644 index 00000000..ecf37361 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/.secure_rzone @@ -0,0 +1,29 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/etherkit_ethercat_cherryecat/.secure_xml b/projects/etherkit_ethercat_cherryecat/.secure_xml new file mode 100644 index 00000000..12fd5370 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/.secure_xml @@ -0,0 +1,175 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/etherkit_ethercat_cherryecat/.settings/.rtmenus b/projects/etherkit_ethercat_cherryecat/.settings/.rtmenus new file mode 100644 index 00000000..37ba1251 Binary files /dev/null and b/projects/etherkit_ethercat_cherryecat/.settings/.rtmenus differ diff --git a/projects/etherkit_ethercat_cherryecat/.settings/etherkit_ethernet.JLink.Debug.rttlaunch b/projects/etherkit_ethercat_cherryecat/.settings/etherkit_ethernet.JLink.Debug.rttlaunch new file mode 100644 index 00000000..a818e2d3 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/.settings/etherkit_ethernet.JLink.Debug.rttlaunch @@ -0,0 +1,93 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/etherkit_ethercat_cherryecat/.settings/ilg.gnumcueclipse.managedbuild.cross.arm.prefs b/projects/etherkit_ethercat_cherryecat/.settings/ilg.gnumcueclipse.managedbuild.cross.arm.prefs new file mode 100644 index 00000000..7dbfc8a7 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/.settings/ilg.gnumcueclipse.managedbuild.cross.arm.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +toolchain.path.1287942917=${toolchain_install_path}/ARM/GNU_Tools_for_ARM_Embedded_Processors/10.2.1/bin diff --git a/projects/etherkit_ethercat_cherryecat/.settings/language.settings.xml b/projects/etherkit_ethercat_cherryecat/.settings/language.settings.xml new file mode 100644 index 00000000..1ba416b6 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/.settings/language.settings.xml @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/projects/etherkit_ethercat_cherryecat/.settings/local_temp_storage.prefs b/projects/etherkit_ethercat_cherryecat/.settings/local_temp_storage.prefs new file mode 100644 index 00000000..5ef7b9c4 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/.settings/local_temp_storage.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +temp.toolchain.exec.path=C\:\\Softwares\\RT-ThreadStudio\\repo\\Extract\\ToolChain_Support_Packages\\ARM\\GNU_Tools_for_ARM_Embedded_Processors\\10.2.1/bin diff --git a/projects/etherkit_ethercat_cherryecat/.settings/org.eclipse.core.resources.prefs b/projects/etherkit_ethercat_cherryecat/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 00000000..12ffae0b --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +rtt-studio.preferences.renesas.configurator.root=C\:\\Renesas\\rzn\\sc_v2025-01_fsp_v2.2.0 diff --git a/projects/etherkit_ethercat_cherryecat/.settings/org.eclipse.core.runtime.prefs b/projects/etherkit_ethercat_cherryecat/.settings/org.eclipse.core.runtime.prefs new file mode 100644 index 00000000..9f1acfcf --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/.settings/org.eclipse.core.runtime.prefs @@ -0,0 +1,3 @@ +content-types/enabled=true +content-types/org.eclipse.cdt.core.asmSource/file-extensions=s +eclipse.preferences.version=1 \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/.settings/projcfg.ini b/projects/etherkit_ethercat_cherryecat/.settings/projcfg.ini new file mode 100644 index 00000000..4f926ed7 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/.settings/projcfg.ini @@ -0,0 +1,20 @@ +#RT-Thread Studio Project Configuration +#Mon Sep 29 17:43:37 CST 2025 +project_type=rt-thread +chip_name=R9A07G084 +os_branch=full +example_name= +os_version=5.1.0 +selected_rtt_version=5.1.0 +cfg_version=v3.0 +board_base_nano_proj=False +is_use_scons_build=True +output_project_path=C\:\\Users\\RTT\\Desktop\\github\\sdk-bsp-rzn2l-etherkit\\projects +project_base_bsp=true +hardware_adapter=J-Link +project_name=etherkit_ethercat_cherryecat +is_base_example_project=False +board_name=EtherKit +device_vendor=RENESAS +bsp_path=repo/Extract/Board_Support_Packages/RealThread/EtherKit/1.3.0 +bsp_version=1.3.0 diff --git a/projects/etherkit_ethercat_cherryecat/.settings/standalone.prefs b/projects/etherkit_ethercat_cherryecat/.settings/standalone.prefs new file mode 100644 index 00000000..91d11822 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/.settings/standalone.prefs @@ -0,0 +1,43 @@ +#Sat Oct 11 14:47:50 CST 2025 +com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp_xspi0_boot.ld +com.renesas.cdt.ddsc.contentgen.options/options/suppresswarningspaths= +com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#Core\#\#\#\#5.7.0+renesas.3.fsp.2.2.0/all=1441545198,rzn/arm/CMSIS_5/LICENSE.txt|4247764709,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_gcc.h|1135074086,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/core_cr52.h|510668081,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_iccarm.h|4245531541,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_compiler.h|1887099957,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_cp15.h|3334069041,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_version.h +com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#Core\#\#\#\#5.7.0+renesas.3.fsp.2.2.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#rzn2l_rsk\#\#xspi0_x1_boot\#\#2.2.0/all=3491271161,script/fsp_xspi0_boot.ld|2137037368,rzn/board/rzn2l_rsk/board_leds.c|1608455294,rzn/board/rzn2l_rsk/board_init.c|2679402475,rzn/board/rzn2l_rsk/board.h|1041253830,rzn/board/rzn2l_rsk/board_ethernet_phy.h|3351740966,rzn/board/rzn2l_rsk/board_leds.h|1088084076,rzn/board/rzn2l_rsk/board_init.h +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#rzn2l_rsk\#\#xspi0_x1_boot\#\#2.2.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#all\#\#Memory\#\#\#\#2.2.0/all= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#all\#\#Memory\#\#\#\#2.2.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#device\#\#\#\#2.2.0/all=3932580821,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#device\#\#\#\#2.2.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#device\#\#R9A07G084M04GBG\#\#2.2.0/all= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#device\#\#R9A07G084M04GBG\#\#2.2.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#fsp\#\#\#\#2.2.0/all=1460414581,rzn/fsp/src/bsp/mcu/rzn2l/bsp_loader_param.c|2321958380,rzn/fsp/src/bsp/mcu/rzn2l/bsp_feature.h|4149273342,rzn/fsp/src/bsp/mcu/rzn2l/bsp_elc.h|4147125589,rzn/fsp/src/bsp/mcu/rzn2l/bsp_irq_sense.c|3928882208,rzn/fsp/src/bsp/mcu/rzn2l/bsp_override.h|3186817992,rzn/fsp/src/bsp/mcu/rzn2l/bsp_mcu_info.h +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#fsp\#\#\#\#2.2.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#2.2.0/all=500553905,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|1691547853,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|71901562,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/system_core.c|3810050431,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/startup_core.c|1181297824,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/R9A09G087.h|3932580821,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|1374776167,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|4128110811,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/R9A07G084.h|1949300192,rzn/fsp/src/bsp/mcu/all/bsp_io.h|3419808366,rzn/fsp/src/bsp/mcu/all/bsp_cache.h|4281041128,rzn/fsp/src/bsp/mcu/all/bsp_register_protection.h|1056966381,rzn/fsp/src/bsp/mcu/all/bsp_tzc400.h|1853261550,rzn/fsp/src/bsp/mcu/all/bsp_ddr_fw_param.h|2340541415,rzn/fsp/src/bsp/mcu/all/bsp_io.c|777766746,rzn/fsp/src/bsp/mcu/all/bsp_common.h|2159935905,rzn/fsp/src/bsp/mcu/all/bsp_reset.h|3805041378,rzn/fsp/src/bsp/mcu/all/bsp_module_stop.h|1518075339,rzn/fsp/src/bsp/mcu/all/bsp_irq.h|2813797547,rzn/fsp/src/bsp/mcu/all/bsp_tfu.h|3052576126,rzn/fsp/src/bsp/mcu/all/bsp_delay.c|620909623,rzn/fsp/src/bsp/mcu/all/bsp_compiler_support.h|2485735290,rzn/fsp/src/bsp/mcu/all/bsp_clocks.h|3899420712,rzn/fsp/src/bsp/mcu/all/bsp_common.c|155435521,rzn/fsp/src/bsp/mcu/all/bsp_slave_stop.c|288171482,rzn/fsp/src/bsp/mcu/all/bsp_clocks.c|358325813,rzn/fsp/src/bsp/mcu/all/bsp_irq.c|3035572228,rzn/fsp/src/bsp/mcu/all/bsp_sbrk.c|1122404825,rzn/fsp/src/bsp/mcu/all/bsp_cache.c|3375215354,rzn/fsp/src/bsp/mcu/all/bsp_tzc400.c|4004178582,rzn/fsp/src/bsp/mcu/all/bsp_exceptions.h|4171127952,rzn/fsp/src/bsp/mcu/all/bsp_address_expander.h|4237692344,rzn/fsp/src/bsp/mcu/all/bsp_register_protection.c|3075072751,rzn/fsp/src/bsp/mcu/all/bsp_reset.c|3404759526,rzn/fsp/src/bsp/mcu/all/bsp_ddr.h|3509889979,rzn/fsp/src/bsp/mcu/all/bsp_mcu_api.h|779228178,rzn/fsp/src/bsp/mcu/all/bsp_ddr.c|1356272951,rzn/fsp/src/bsp/mcu/all/bsp_address_expander.c|1889702459,rzn/fsp/src/bsp/mcu/all/bsp_semaphore.h|2618260322,rzn/fsp/src/bsp/mcu/all/bsp_slave_stop.h|3762948597,rzn/fsp/src/bsp/mcu/all/bsp_delay.h|3775213019,rzn/fsp/src/bsp/mcu/all/bsp_ddr_fw_param.c|3027953462,rzn/fsp/src/bsp/mcu/all/bsp_semaphore.c|3902133153,rzn/fsp/src/bsp/mcu/all/cr/bsp_cache_core.h|2249528202,rzn/fsp/src/bsp/mcu/all/cr/bsp_delay_core.h|1591030987,rzn/fsp/src/bsp/mcu/all/cr/bsp_cache_core.c|2628857650,rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.c|1476552636,rzn/fsp/src/bsp/mcu/all/cr/bsp_delay_core.c|237502674,rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.h|310861080,rzn/fsp/inc/fsp_features.h|610410096,rzn/fsp/inc/fsp_version.h|4252924486,rzn/fsp/inc/fsp_common_api.h|4017611099,rzn/fsp/inc/instances/r_ioport.h|474542689,rzn/fsp/inc/api/bsp_api.h|2795021536,rzn/fsp/inc/api/r_ioport_api.h +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#2.2.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ether_phy\#\#\#\#2.2.0/all=3419091927,rzn/fsp/src/r_ether_phy/r_ether_phy.c|204740734,rzn/fsp/inc/instances/r_ether_phy.h|3519950923,rzn/fsp/inc/api/r_ether_phy_api.h +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ether_phy\#\#\#\#2.2.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ether_selector\#\#\#\#2.2.0/all=3452251033,rzn/fsp/src/r_ether_selector/r_ether_selector.c|1141164539,rzn/fsp/inc/instances/r_ether_selector.h|786475994,rzn/fsp/inc/api/r_ether_selector_api.h +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ether_selector\#\#\#\#2.2.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ethsw\#\#\#\#2.2.0/all=1725931930,rzn/fsp/src/r_ethsw/r_ethsw.c|3863987970,rzn/fsp/inc/instances/r_ethsw.h|3935299353,rzn/fsp/inc/api/r_ether_switch_api.h +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ethsw\#\#\#\#2.2.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_gmac\#\#\#\#2.2.0/all=2767674387,rzn/fsp/src/r_gmac/r_gmac.c|3604085163,rzn/fsp/inc/instances/r_gmac.h|1576079366,rzn/fsp/inc/api/r_ether_api.h +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_gmac\#\#\#\#2.2.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_gpt\#\#\#\#2.2.0/all=1701283242,rzn/fsp/src/r_gpt/r_gpt.c|3514125611,rzn/fsp/inc/instances/r_gpt.h|2833340986,rzn/fsp/inc/api/r_timer_api.h +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_gpt\#\#\#\#2.2.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#2.2.0/all=824647496,rzn/fsp/src/r_ioport/r_ioport.c|4017611099,rzn/fsp/inc/instances/r_ioport.h|2795021536,rzn/fsp/inc/api/r_ioport_api.h +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#2.2.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_mtu3\#\#\#\#2.2.0/all=3441005877,rzn/fsp/src/r_mtu3/r_mtu3.c|2585942167,rzn/fsp/inc/instances/r_mtu3.h|2833340986,rzn/fsp/inc/api/r_timer_api.h +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_mtu3\#\#\#\#2.2.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#2.2.0/all=2555335099,rzn/fsp/src/r_sci_uart/r_sci_uart.c|257214413,rzn/fsp/inc/instances/r_sci_uart.h|300185683,rzn/fsp/inc/api/r_uart_api.h|2744795673,rzn/fsp/inc/api/r_transfer_api.h +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#2.2.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Projects\#\#all\#\#baremetal_blinky\#\#\#\#2.2.0/all= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Projects\#\#all\#\#baremetal_blinky\#\#\#\#2.2.0/libraries= +com.renesas.cdt.ddsc.project.standalone.projectgenerationoptions/isCpp=false +com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=SWPConfigurator +com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.ether_on_ether.1094288014=false +com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.ether_phy_on_ether_phy.277662383=false +com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.ether_phy_on_ether_phy.513125102=false +com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.ether_phy_on_ether_phy.518802053=false +com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.1968866849=false +com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.86814920=false diff --git a/projects/etherkit_ethercat_cherryecat/Kconfig b/projects/etherkit_ethercat_cherryecat/Kconfig new file mode 100644 index 00000000..3a9e894c --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/Kconfig @@ -0,0 +1,34 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "rt-thread" + +# you can change the RTT_ROOT default "rt-thread" +# example : default "F:/git_repositories/rt-thread" + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +config ENV_DIR + string + option env="ENV_ROOT" + default "/" + +config PLATFORM_DIR + string + option env="PLATFORM_DIR" + default "C:/Users/RTT/Desktop/github/sdk-bsp-rzn2l-etherkit/projects/etherkit_ethercat_cherryecat/platform" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "libraries/Kconfig" +source "$BSP_DIR/board/Kconfig" diff --git a/projects/etherkit_ethercat_cherryecat/README.md b/projects/etherkit_ethercat_cherryecat/README.md new file mode 100644 index 00000000..855ade92 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/README.md @@ -0,0 +1,51 @@ +# CherryECAT Driver Usage Instructions + +**English** | [**中文**](./README_zh.md) + +## Introduction + +This project provides cherryecat demo. + +## Hardware Connection + +To use Ethernet, connect the development board to any one of the three network ports using an Ethernet cable, and the other end should be connected to a network switch that has internet access. + +## FSP Configuration Instructions + +Open the project configuration file `configuration.xml` and add the `r_gamc` stack: + +![image-20241126104408737](figures/image-20241126104408737.png) + +Next, click on `g_ether0 Ethernet`, and configure the interrupt callback function to `user_ether0_callback`: + +![image-20241126104422910](figures/image-20241126104422910.png) + +Now configure the PHY settings. Select `g_ether_phy0`, set the common configuration to "User Own Target", change the PHY LSI address to `1` (refer to the schematic for the exact address), and set the PHY initialization callback function to `ether_phy_targets_initialize_rtl8211_rgmii()`. Also, set the MDIO to GMAC. + +![image-20241126104437432](figures/image-20241126104437432.png) + +Next, configure `g_ether_selector0`, set the Ethernet mode to "Switch Mode", set the PHY link to "Default Active-Low", and choose "RGMII" for the PHY interface mode. + +![image-20241126104519290](figures/image-20241126104519290.png) + +Configure the Ethernet pin parameters and select the operating mode to RGMII: + +![image-20241126104533098](figures/image-20241126104533098.png) + +Finally, configure `ETHER_GMAC`: + +![image-20241126104603633](figures/image-20241126104603633.png) + +## RT-Thread Studio Configuration + +Return to the Studio project, and configure RT-Thread Settings. Click on "Hardware", find the chip device driver, and enable Ethernet: + +![image-20241126104852383](figures/image-20241126104852383.png) + +## Running Results + +![cherryecat](figures/cherryecat1.png) +![cherryecat](figures/cherryecat2.png) +![cherryecat](figures/cherryecat3.png) +![cherryecat](figures/cherryecat4.png) +![cherryecat](figures/cherryecat5.png) \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/README_zh.md b/projects/etherkit_ethercat_cherryecat/README_zh.md new file mode 100644 index 00000000..b9d5e994 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/README_zh.md @@ -0,0 +1,51 @@ +# CherryECAT 驱动示例 + +**中文** | [**English**](./README.md) + +## 简介 + +本工程提供 cherryecat 的基础功能 + +## 硬件连接 + +需要使用网线连接到开发板的三网口其中任意一个网口，另一头连接到可以联网的交换机上。 + +## FSP配置说明 + +打开工程配置文件configuration.xml，新增r_gamc Stack： + +![image-20241126104408737](figures/image-20241126104408737.png) + +点击g_ether0 Ethernet，配置中断回调函数为user_ether0_callback： + +![image-20241126104422910](figures/image-20241126104422910.png) + +下面配置phy信息，选择g_ether_phy0，Common配置为User Own Target；修改PHY LSI地址为1（根据原理图查询具体地址）；设置phy初始化回调函数为ether_phy_targets_initialize_rtl8211_rgmii()；同时设置MDIO为GMAC。 + +![image-20241126104437432](figures/image-20241126104437432.png) + +配置g_ether_selector0，选择以太网模式为交换机模式，PHY link设置为默认active-low，PHY接口模式设置为RGMII。 + +![image-20241126104519290](figures/image-20241126104519290.png) + +网卡引脚参数配置，选择操作模式为RGMII： + +![image-20241126104533098](figures/image-20241126104533098.png) + +ETHER_GMAC配置： + +![image-20241126104603633](figures/image-20241126104603633.png) + +## RT-Thread Studio配置 + +回到Studio工程，配置RT-Thread Settings，点击选择硬件选项，找到芯片设备驱动，使能以太网； + +![image-20241126104852383](figures/image-20241126104852383.png) + +## 运行效果 + +![cherryecat](figures/cherryecat1.png) +![cherryecat](figures/cherryecat2.png) +![cherryecat](figures/cherryecat3.png) +![cherryecat](figures/cherryecat4.png) +![cherryecat](figures/cherryecat5.png) diff --git a/projects/etherkit_ethercat_cherryecat/SConscript b/projects/etherkit_ethercat_cherryecat/SConscript new file mode 100644 index 00000000..1b700776 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/SConscript @@ -0,0 +1,27 @@ +# for module compiling +import os +Import('RTT_ROOT') +Import('rtconfig') +from building import * +from gcc import * + +cwd = GetCurrentDir() +src = [] +CPPPATH = [cwd] +group = [] +list = os.listdir(cwd) + +CPPDEFINES = ['_RZN_ORDINAL=1'] + +if rtconfig.PLATFORM in ['iccarm'] + GetGCCLikePLATFORM(): + if rtconfig.PLATFORM == 'iccarm' or GetOption('target') != 'mdk5': + CPPPATH = [cwd + '/src'] + src = Glob('./src/*.c') + group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + group = group + SConscript(os.path.join(d, 'SConscript')) + +Return('group') diff --git a/projects/etherkit_ethercat_cherryecat/SConstruct b/projects/etherkit_ethercat_cherryecat/SConstruct new file mode 100644 index 00000000..e900110c --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/SConstruct @@ -0,0 +1,56 @@ +import os +import sys +import rtconfig + +if os.path.exists('rt-thread'): + RTT_ROOT = os.path.normpath(os.getcwd() + '/rt-thread') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '../../../rt-thread') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except Exception as e: + print("Error message:", e.message) + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + sys.exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/../libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +rtconfig.BSP_LIBRARY_TYPE = None + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/projects/etherkit_ethercat_cherryecat/board/Kconfig b/projects/etherkit_ethercat_cherryecat/board/Kconfig new file mode 100644 index 00000000..4c3fef35 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/board/Kconfig @@ -0,0 +1,572 @@ +menu "Hardware Drivers Config" + + config SOC_R9A07G084 + bool + select SOC_SERIES_R9A07G0 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + + menu "Onboard Peripheral Drivers" + + endmenu + + menu "On-chip Peripheral Drivers" + + source "libraries/HAL_Drivers/Kconfig" + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + select RT_USING_SERIAL_V2 + if BSP_USING_UART + menuconfig BSP_USING_UART0 + bool "Enable UART0" + default n + if BSP_USING_UART0 + config BSP_UART0_RX_USING_DMA + bool "Enable UART0 RX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + + config BSP_UART0_TX_USING_DMA + bool "Enable UART0 TX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + + config BSP_UART0_RX_BUFSIZE + int "Set UART0 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART0_TX_BUFSIZE + int "Set UART0 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART5 + bool "Enable UART5" + default n + if BSP_USING_UART5 + config BSP_UART5_RX_USING_DMA + bool "Enable UART5 RX DMA" + depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA + default n + + config BSP_UART5_TX_USING_DMA + bool "Enable UART5 TX DMA" + depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA + default n + + config BSP_UART5_RX_BUFSIZE + int "Set UART5 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART5_TX_BUFSIZE + int "Set UART5 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC0 + bool "Enable ADC0" + config BSP_USING_ADC1 + bool "Enable ADC1" + config BSP_USING_ADC2 + bool "Enable ADC2" + config BSP_USING_ADC3 + bool "Enable ADC3" + default n + endif + + menuconfig BSP_USING_CANFD + bool "Enable CANFD" + default n + select RT_USING_CAN + select RT_CAN_USING_CANFD + if BSP_USING_CANFD + config BSP_USING_CAN_RZ + bool "Enabled this option means turning on standard CAN, while disabling it means switching to CANFD." + default n + config BSP_USING_CANFD0 + bool "Enable CANFD0" + default n + config BSP_USING_CANFD1 + bool "Enable CANFD1" + default n + endif + + menuconfig BSP_USING_SCI + bool "Enable SCI Controller" + default n + config BSP_USING_SCIn_SPI + bool + depends on BSP_USING_SCI + select RT_USING_SPI + default n + + config BSP_USING_SCIn_I2C + bool + depends on BSP_USING_SCI + select RT_USING_I2C + default n + + config BSP_USING_SCIn_UART + bool + depends on BSP_USING_SCI + select RT_USING_SERIAL + select RT_USING_SERIAL_V2 + default n + + if BSP_USING_SCI + config BSP_USING_SCI0 + bool "Enable SCI0" + default n + if BSP_USING_SCI0 + choice + prompt "choice sci mode" + default BSP_USING_SCI0_SPI + config BSP_USING_SCI0_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI0_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI0_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI0_UART + config BSP_SCI0_UART_RX_BUFSIZE + int "Set UART0 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI0_UART_TX_BUFSIZE + int "Set UART0 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI1 + bool "Enable SCI1" + default n + if BSP_USING_SCI1 + choice + prompt "choice sci mode" + default BSP_USING_SCI1_SPI + config BSP_USING_SCI1_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI1_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI1_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI1_UART + config BSP_SCI1_UART_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI1_UART_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI2 + bool "Enable SCI2" + default n + if BSP_USING_SCI2 + choice + prompt "choice sci mode" + default BSP_USING_SCI2_SPI + config BSP_USING_SCI2_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI2_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI2_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI2_UART + config BSP_SCI2_UART_RX_BUFSIZE + int "Set UART2 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI2_UART_TX_BUFSIZE + int "Set UART2 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI3 + bool "Enable SCI3" + default n + if BSP_USING_SCI3 + choice + prompt "choice sci mode" + default BSP_USING_SCI3_SPI + config BSP_USING_SCI3_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI3_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI3_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI3_UART + config BSP_SCI3_UART_RX_BUFSIZE + int "Set UART3 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI3_UART_TX_BUFSIZE + int "Set UART3 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI4 + bool "Enable SCI4" + default n + if BSP_USING_SCI4 + choice + prompt "choice sci mode" + default BSP_USING_SCI4_SPI + config BSP_USING_SCI4_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI4_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI4_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI4_UART + config BSP_SCI4_UART_RX_BUFSIZE + int "Set UART4 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI4_UART_TX_BUFSIZE + int "Set UART4 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI5 + bool "Enable SCI5" + default n + if BSP_USING_SCI5 + choice + prompt "choice sci mode" + default BSP_USING_SCI5_SPI + config BSP_USING_SCI5_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI5_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI5_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI5_UART + config BSP_SCI5_UART_RX_BUFSIZE + int "Set UART5 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI5_UART_TX_BUFSIZE + int "Set UART5 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI6 + bool "Enable SCI6" + default n + if BSP_USING_SCI6 + choice + prompt "choice sci mode" + default BSP_USING_SCI6_SPI + config BSP_USING_SCI6_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI6_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI6_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI6_UART + config BSP_SCI6_UART_RX_BUFSIZE + int "Set UART6 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI6_UART_TX_BUFSIZE + int "Set UART6 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI7 + bool "Enable SCI7" + default n + if BSP_USING_SCI7 + choice + prompt "choice sci mode" + default BSP_USING_SCI7_SPI + config BSP_USING_SCI7_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI7_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI7_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI7_UART + config BSP_SCI7_UART_RX_BUFSIZE + int "Set UART7 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI7_UART_TX_BUFSIZE + int "Set UART7 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI8 + bool "Enable SCI8" + default n + if BSP_USING_SCI8 + choice + prompt "choice sci mode" + default BSP_USING_SCI8_SPI + config BSP_USING_SCI8_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI8_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI8_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI8_UART + config BSP_SCI8_UART_RX_BUFSIZE + int "Set UART8 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI8_UART_TX_BUFSIZE + int "Set UART8 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + config BSP_USING_SCI9 + bool "Enable SCI9" + default n + if BSP_USING_SCI9 + choice + prompt "choice sci mode" + default BSP_USING_SCI9_SPI + config BSP_USING_SCI9_SPI + select BSP_USING_SCIn_SPI + bool "SPI mode" + config BSP_USING_SCI9_I2C + select BSP_USING_SCIn_I2C + bool "I2C mode" + config BSP_USING_SCI9_UART + select BSP_USING_SCIn_UART + bool "UART mode" + endchoice + if BSP_USING_SCI9_UART + config BSP_SCI9_UART_RX_BUFSIZE + int "Set UART9 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_SCI9_UART_TX_BUFSIZE + int "Set UART9 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + endif + + config BSP_USING_HYPERRAM + bool "Enable XSPI0 CS1 Winbond octal hyperRAM" + default n + + menuconfig BSP_USING_I2C + bool "Enable I2C BUS" + default n + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C + config BSP_USING_HW_I2C + bool "Enable Hardware I2C BUS" + default n + if BSP_USING_HW_I2C + config BSP_USING_HW_I2C0 + bool "Enable Hardware I2C0 BUS" + default n + endif + if BSP_USING_HW_I2C + config BSP_USING_HW_I2C1 + bool "Enable Hardware I2C1 BUS" + default n + endif + if !BSP_USING_HW_I2C + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 BUS (software simulation)" + default y + if BSP_USING_I2C1 + config BSP_I2C1_SCL_PIN + hex "i2c1 scl pin number" + range 0x0000 0x0B0F + default 0x0B03 + config BSP_I2C1_SDA_PIN + hex "I2C1 sda pin number" + range 0x0000 0x0B0F + default 0x050E + endif + endif + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable SPI0 BUS" + default n + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n + config BSP_USING_SPI2 + bool "Enable SPI2 BUS" + default n + endif + + menuconfig BSP_USING_TIM + bool "Enable timer" + default n + select RT_USING_HWTIMER + if BSP_USING_TIM + config BSP_USING_TIM0 + bool "Enable TIM0" + default n + config BSP_USING_TIM1 + bool "Enable TIM1" + default n + endif + + menuconfig BSP_USING_PWM + bool "Enable PWM" + default n + select RT_USING_PWM + if BSP_USING_PWM + config BSP_USING_PWM5 + bool "Enable GPT5 (32-Bits) output PWM" + default n + endif + + config BSP_USING_ETH + bool "Enable Ethernet" + select RT_USING_SAL + select RT_USING_LWIP + select RT_USING_NETDEV + default n + + endmenu + + menu "Board extended module Drivers" + menuconfig BSP_USING_RW007 + bool "Enable RW007" + default n + select PKG_USING_RW007 + select BSP_USING_SPI + select BSP_USING_SPI2 + select RT_USING_MEMPOOL + select RW007_NOT_USE_EXAMPLE_DRIVERS + + if BSP_USING_RW007 + config RA_RW007_SPI_BUS_NAME + string "RW007 BUS NAME" + default "spi2" + + config RA_RW007_CS_PIN + hex "(HEX)CS pin index" + default 0x1207 + + config RA_RW007_BOOT0_PIN + hex "(HEX)BOOT0 pin index (same as spi clk pin)" + default 0x1204 + + config RA_RW007_BOOT1_PIN + hex "(HEX)BOOT1 pin index (same as spi cs pin)" + default 0x1207 + + config RA_RW007_INT_BUSY_PIN + hex "(HEX)INT/BUSY pin index" + default 0x1102 + + config RA_RW007_RST_PIN + hex "(HEX)RESET pin index" + default 0x1706 + endif + endmenu +endmenu diff --git a/projects/etherkit_ethercat_cherryecat/board/SConscript b/projects/etherkit_ethercat_cherryecat/board/SConscript new file mode 100644 index 00000000..a27ea8e4 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/board/SConscript @@ -0,0 +1,16 @@ +import os +from building import * + +objs = [] +cwd = GetCurrentDir() +list = os.listdir(cwd) +CPPPATH = [cwd] +src = Glob('*.c') + +objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + objs = objs + SConscript(os.path.join(item, 'SConscript')) + +Return('objs') diff --git a/projects/etherkit_ethercat_cherryecat/board/board.h b/projects/etherkit_ethercat_cherryecat/board/board.h new file mode 100644 index 00000000..8d16dfc1 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/board/board.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-03-11 Wangyuqiang first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#define RZ_SRAM_SIZE 1536 /* The SRAM size of the chip needs to be modified */ +#define RZ_SRAM_END (0x10000000 + RZ_SRAM_SIZE * 1024 - 1) + +#ifdef __ARMCC_VERSION +extern int Image$$RAM_END$$ZI$$Base; +#define HEAP_BEGIN ((void *)&Image$$RAM_END$$ZI$$Base) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) +#else +extern int __bss_end__; +#define HEAP_BEGIN ((void *)&__bss_end__) +#endif + +#define HEAP_END RZ_SRAM_END + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define MAX_HANDLERS BSP_VECTOR_TABLE_MAX_ENTRIES +#define GIC_IRQ_START 0 +#define GIC_ACK_INTID_MASK (0x000003FFU) +/* number of interrupts on board */ +#define ARM_GIC_NR_IRQS (448) +/* only one GIC available */ +#define ARM_GIC_MAX_NR 1 +/* end defined */ + +#define GICV3_DISTRIBUTOR_BASE_ADDR (0x100000) + +/* the basic constants and interfaces needed by gic */ +rt_inline rt_uint32_t platform_get_gic_dist_base(void) +{ + rt_uint32_t gic_base; + + __get_cp(15, 1, gic_base, 15, 3, 0); + return gic_base + GICV3_DISTRIBUTOR_BASE_ADDR; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/projects/etherkit_ethercat_cherryecat/board/ec_config.h b/projects/etherkit_ethercat_cherryecat/board/ec_config.h new file mode 100644 index 00000000..a57bb284 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/board/ec_config.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef EC_CONFIG_H +#define EC_CONFIG_H + +#include "rtthread.h" + +#define CONFIG_EC_PRINTF(...) rt_kprintf(__VA_ARGS__) + +#ifndef CONFIG_EC_DBG_LEVEL +#define CONFIG_EC_DBG_LEVEL EC_DBG_INFO +#endif + +#ifndef CONFIG_EC_SLAVE_DBG_LEVEL +#define CONFIG_EC_SLAVE_DBG_LEVEL EC_DBG_INFO +#endif + +/* Enable print with color */ +#define CONFIG_EC_PRINTF_COLOR_ENABLE + +#define EC_FAST_CODE_SECTION + +#ifndef CONFIG_EC_MAX_NETDEVS +#define CONFIG_EC_MAX_NETDEVS 1 +#endif + +#ifndef CONFIG_EC_NONPERIOD_PRIO +#define CONFIG_EC_NONPERIOD_PRIO 0 +#endif + +#ifndef CONFIG_EC_NONPERIOD_STACKSIZE +#define CONFIG_EC_NONPERIOD_STACKSIZE 2048 +#endif + +#ifndef CONFIG_EC_NONPERIOD_INTERVAL_MS +#define CONFIG_EC_NONPERIOD_INTERVAL_MS 10 +#endif + +#ifndef CONFIG_EC_NONPERIOD_WAITERS +#define CONFIG_EC_NONPERIOD_WAITERS 20 +#endif + +#ifndef CONFIG_EC_SCAN_PRIO +#define CONFIG_EC_SCAN_PRIO 1 +#endif + +#ifndef CONFIG_EC_SCAN_STACKSIZE +#define CONFIG_EC_SCAN_STACKSIZE 2048 +#endif + +#ifndef CONFIG_EC_SCAN_INTERVAL_MS +#define CONFIG_EC_SCAN_INTERVAL_MS 100 +#endif + +#ifndef CONFIG_EC_PER_SM_MAX_PDOS +#define CONFIG_EC_PER_SM_MAX_PDOS 8 +#endif + +#ifndef CONFIG_EC_PER_PDO_MAX_PDO_ENTRIES +#define CONFIG_EC_PER_PDO_MAX_PDO_ENTRIES 8 +#endif + +#define CONFIG_EC_PERF_ENABLE +#define CONFIG_EC_CMD_ENABLE +#define CONFIG_EC_TIMESTAMP_CUSTOM +#define CONFIG_EC_PHY_CUSTOM + +#ifndef CONFIG_EC_MAX_PDO_BUFSIZE +#define CONFIG_EC_MAX_PDO_BUFSIZE 2048 +#endif + +#ifndef CONFIG_EC_MAX_ENET_TXBUF_COUNT +#define CONFIG_EC_MAX_ENET_TXBUF_COUNT 10 +#endif + +#ifndef CONFIG_EC_MAX_ENET_RXBUF_COUNT +#define CONFIG_EC_MAX_ENET_RXBUF_COUNT 10 +#endif + +// #define CONFIG_EC_FOE + +#endif \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/board/ports/SConscript b/projects/etherkit_ethercat_cherryecat/board/ports/SConscript new file mode 100644 index 00000000..e8ac9ae5 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/board/ports/SConscript @@ -0,0 +1,16 @@ +import os +from building import * + +objs = [] +src = Glob('*.c') +cwd = GetCurrentDir() +CPPPATH = [cwd] + +objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + objs = objs + SConscript(os.path.join(item, 'SConscript')) + +Return('objs') diff --git a/projects/etherkit_ethercat_cherryecat/board/ports/gpio_cfg.h b/projects/etherkit_ethercat_cherryecat/board/ports/gpio_cfg.h new file mode 100644 index 00000000..d179d4ab --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/board/ports/gpio_cfg.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-03-11 Wangyuqiang first version + */ + +/* Number of IRQ channels on the device */ +#define RA_IRQ_MAX 16 + +/* PIN to IRQx table */ +#define PIN2IRQX_TABLE \ +{ \ + switch (pin) \ + { \ + case BSP_IO_PORT_00_PIN_1: \ + case BSP_IO_PORT_09_PIN_2: \ + case BSP_IO_PORT_18_PIN_3: \ + return 0; \ + case BSP_IO_PORT_00_PIN_3: \ + case BSP_IO_PORT_07_PIN_4: \ + case BSP_IO_PORT_18_PIN_4: \ + return 1; \ + case BSP_IO_PORT_01_PIN_2: \ + return 2; \ + case BSP_IO_PORT_01_PIN_4: \ + return 3; \ + case BSP_IO_PORT_02_PIN_0: \ + case BSP_IO_PORT_22_PIN_2: \ + return 4; \ + case BSP_IO_PORT_03_PIN_5: \ + case BSP_IO_PORT_13_PIN_2: \ + return 5; \ + case BSP_IO_PORT_14_PIN_2: \ + case BSP_IO_PORT_21_PIN_5: \ + return 6; \ + case BSP_IO_PORT_16_PIN_3: \ + return 7; \ + case BSP_IO_PORT_03_PIN_6: \ + case BSP_IO_PORT_16_PIN_6: \ + return 8; \ + case BSP_IO_PORT_03_PIN_7: \ + case BSP_IO_PORT_21_PIN_6: \ + return 9; \ + case BSP_IO_PORT_04_PIN_4: \ + case BSP_IO_PORT_18_PIN_1: \ + case BSP_IO_PORT_21_PIN_7: \ + return 10; \ + case BSP_IO_PORT_10_PIN_4: \ + case BSP_IO_PORT_18_PIN_6: \ + return 11; \ + case BSP_IO_PORT_05_PIN_0: \ + case BSP_IO_PORT_05_PIN_4: \ + case BSP_IO_PORT_05_PIN_6: \ + return 12; \ + case BSP_IO_PORT_00_PIN_4: \ + case BSP_IO_PORT_00_PIN_7: \ + case BSP_IO_PORT_05_PIN_1: \ + return 13; \ + case BSP_IO_PORT_02_PIN_2: \ + case BSP_IO_PORT_03_PIN_0: \ + case BSP_IO_PORT_05_PIN_2: \ + return 14; \ + case BSP_IO_PORT_02_PIN_3: \ + case BSP_IO_PORT_05_PIN_3: \ + case BSP_IO_PORT_22_PIN_0: \ + return 15; \ + default : \ + return -1; \ + } \ +} diff --git a/projects/etherkit_ethercat_cherryecat/buildinfo.ipcf b/projects/etherkit_ethercat_cherryecat/buildinfo.ipcf new file mode 100644 index 00000000..f9b42655 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/buildinfo.ipcf @@ -0,0 +1,40 @@ + + + + R9A07G084M04 + + + + + _RZN_ORDINAL=1 + _RZN_CORE=CR52_0 + _RENESAS_RZN_ + + + + + _RZN_ORDINAL=1 + _RZN_CORE=CR52_0 + _RENESAS_RZN_ + + + true + $PROJ_DIR$/script/fsp_xspi0_boot.icf + + + --config_search "$PROJ_DIR$" + + + system_init + + + + + RASC_EXE_PATH + C:\Renesas\rzn\sc_v2024-01.1_fsp_v2.0.0\eclipse\rasc.exe + + + + + + diff --git a/projects/etherkit_ethercat_cherryecat/buildinfo.json b/projects/etherkit_ethercat_cherryecat/buildinfo.json new file mode 100644 index 00000000..27190c01 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/buildinfo.json @@ -0,0 +1,35 @@ +{ + "definedMacros": [ + "_RZN_ORDINAL=1", + "_RZN_CORE=CR52_0", + "_RENESAS_RZN_" + ], + "sourcePaths": [ + "rzn", + "rzn_gen", + "src" + ], + "excludedFilePaths": [], + "includePaths": [ + "rzn/arm/CMSIS_5/CMSIS/Core_A/Include", + "rzn/arm/CMSIS_5/CMSIS/Core_R/Include", + "rzn/fsp/inc", + "rzn/fsp/inc/api", + "rzn/fsp/inc/instances", + "rzn/fsp/src/bsp/mcu/all/cr", + "rzn_cfg/fsp_cfg", + "rzn_cfg/fsp_cfg/bsp", + "rzn_gen", + "src" + ], + "libraryPaths": [], + "libraryNames": [], + "objectFiles": [], + "linkerScript": "script/fsp_xspi0_boot.ld", + "targetDeviceName": "R9A07G084M04GBG", + "entrySymbol": "system_init", + "isPreBuildContentGenEnabled": true, + "isPostBuildContentGenEnabled": true, + "isTargetDeviceSupportsTrustZone": false, + "buildOptionsMap": {} +} \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/configuration.xml b/projects/etherkit_ethercat_cherryecat/configuration.xml new file mode 100644 index 00000000..f1046a25 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/configuration.xml @@ -0,0 +1,1694 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Simple application that blinks an LED. No RTOS included. + Renesas.RZN_baremetal_blinky.2.2.0.pack + + + Board Support Package Common Files + Renesas.RZN.2.2.0.pack + + + Memory Config Checking + Renesas.RZN.2.2.0.pack + + + I/O Port + Renesas.RZN.2.2.0.pack + + + Arm CMSIS Version 5 - Core + Arm.CMSIS5.5.7.0+renesas.3.fsp.2.2.0.pack + + + RSK+RZN2L Board Support Files (xSPI0 x1 boot mode) + Renesas.RZN_board_rzn2l_rsk.2.2.0.pack + + + Board support package for R9A07G084M04GBG + Renesas.RZN_mcu_rzn2l.2.2.0.pack + + + Board support package for RZN2L + Renesas.RZN_mcu_rzn2l.2.2.0.pack + + + Board support package for RZN2L - FSP Data + Renesas.RZN_mcu_rzn2l.2.2.0.pack + + + SCI UART + Renesas.RZN.2.2.0.pack + + + Ethernet PHY + Renesas.RZN.2.2.0.pack + + + Ethernet Selector + Renesas.RZN.2.2.0.pack + + + Ethernet Switch + Renesas.RZN.2.2.0.pack + + + Ethernet + Renesas.RZN.2.2.0.pack + + + General PWM Timer + Renesas.RZN.2.2.0.pack + + + Multi-Function Timer Pulse Unit 3 + Renesas.RZN.2.2.0.pack + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/etherkit_ethercat_cherryecat/envsetup.sh b/projects/etherkit_ethercat_cherryecat/envsetup.sh new file mode 100644 index 00000000..cb56dd85 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/envsetup.sh @@ -0,0 +1,22 @@ +#!/bin/bash + +export RTT_ROOT=${PWD}/rt-thread +export ENV_ROOT=${HOME}/.env +export BSP_ROOT=${PWD} +export RTT_CC='gcc' +export RTT_EXEC_PATH='/usr/bin' + +rtt_dir='../../rt-thread' +lib_dir='../../libraries' + +if [ ! -L "rt-thread" ]; then + if [ -d $rtt_dir ]; then + ln -s $rtt_dir ./rt-thread + fi +fi + +if [ ! -L "libraries" ]; then + if [ -d $lib_dir ]; then + ln -s $lib_dir ./libraries + fi +fi diff --git a/projects/etherkit_ethercat_cherryecat/figures/cherryecat1.png b/projects/etherkit_ethercat_cherryecat/figures/cherryecat1.png new file mode 100644 index 00000000..931a2052 Binary files /dev/null and b/projects/etherkit_ethercat_cherryecat/figures/cherryecat1.png differ diff --git a/projects/etherkit_ethercat_cherryecat/figures/cherryecat2.png b/projects/etherkit_ethercat_cherryecat/figures/cherryecat2.png new file mode 100644 index 00000000..94491724 Binary files /dev/null and b/projects/etherkit_ethercat_cherryecat/figures/cherryecat2.png differ diff --git a/projects/etherkit_ethercat_cherryecat/figures/cherryecat3.png b/projects/etherkit_ethercat_cherryecat/figures/cherryecat3.png new file mode 100644 index 00000000..5cf3624e Binary files /dev/null and b/projects/etherkit_ethercat_cherryecat/figures/cherryecat3.png differ diff --git a/projects/etherkit_ethercat_cherryecat/figures/cherryecat4.png b/projects/etherkit_ethercat_cherryecat/figures/cherryecat4.png new file mode 100644 index 00000000..684f8e8c Binary files /dev/null and b/projects/etherkit_ethercat_cherryecat/figures/cherryecat4.png differ diff --git a/projects/etherkit_ethercat_cherryecat/figures/cherryecat5.png b/projects/etherkit_ethercat_cherryecat/figures/cherryecat5.png new file mode 100644 index 00000000..9a44d583 Binary files /dev/null and b/projects/etherkit_ethercat_cherryecat/figures/cherryecat5.png differ diff --git a/projects/etherkit_ethercat_cherryecat/figures/image-20241126104408737.png b/projects/etherkit_ethercat_cherryecat/figures/image-20241126104408737.png new file mode 100644 index 00000000..4412a710 Binary files /dev/null and b/projects/etherkit_ethercat_cherryecat/figures/image-20241126104408737.png differ diff --git a/projects/etherkit_ethercat_cherryecat/figures/image-20241126104422910.png b/projects/etherkit_ethercat_cherryecat/figures/image-20241126104422910.png new file mode 100644 index 00000000..9fa321df Binary files /dev/null and b/projects/etherkit_ethercat_cherryecat/figures/image-20241126104422910.png differ diff --git a/projects/etherkit_ethercat_cherryecat/figures/image-20241126104437432.png b/projects/etherkit_ethercat_cherryecat/figures/image-20241126104437432.png new file mode 100644 index 00000000..b4e6fde4 Binary files /dev/null and b/projects/etherkit_ethercat_cherryecat/figures/image-20241126104437432.png differ diff --git a/projects/etherkit_ethercat_cherryecat/figures/image-20241126104519290.png b/projects/etherkit_ethercat_cherryecat/figures/image-20241126104519290.png new file mode 100644 index 00000000..4c34f310 Binary files /dev/null and b/projects/etherkit_ethercat_cherryecat/figures/image-20241126104519290.png differ diff --git a/projects/etherkit_ethercat_cherryecat/figures/image-20241126104533098.png b/projects/etherkit_ethercat_cherryecat/figures/image-20241126104533098.png new file mode 100644 index 00000000..fea03f17 Binary files /dev/null and b/projects/etherkit_ethercat_cherryecat/figures/image-20241126104533098.png differ diff --git a/projects/etherkit_ethercat_cherryecat/figures/image-20241126104603633.png b/projects/etherkit_ethercat_cherryecat/figures/image-20241126104603633.png new file mode 100644 index 00000000..3095ace4 Binary files /dev/null and b/projects/etherkit_ethercat_cherryecat/figures/image-20241126104603633.png differ diff --git a/projects/etherkit_ethercat_cherryecat/figures/image-20241126104852383.png b/projects/etherkit_ethercat_cherryecat/figures/image-20241126104852383.png new file mode 100644 index 00000000..eefb9849 Binary files /dev/null and b/projects/etherkit_ethercat_cherryecat/figures/image-20241126104852383.png differ diff --git a/projects/etherkit_ethercat_cherryecat/memory_regions.ld b/projects/etherkit_ethercat_cherryecat/memory_regions.ld new file mode 100644 index 00000000..e95adf7c --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/memory_regions.ld @@ -0,0 +1,40 @@ + + /* generated memory regions file - do not edit */ + ATCM_START = 0x00000000; + ATCM_LENGTH = 0x20000; + BTCM_START = 0x00100000; + BTCM_LENGTH = 0x20000; + SYSTEM_RAM_START = 0x10000000; + SYSTEM_RAM_LENGTH = 0x180000; + SYSTEM_RAM_MIRROR_START = 0x30000000; + SYSTEM_RAM_MIRROR_LENGTH = 0x180000; + xSPI0_CS0_SPACE_MIRROR_START = 0x40000000; + xSPI0_CS0_SPACE_MIRROR_LENGTH = 0x4000000; + xSPI0_CS1_SPACE_MIRROR_START = 0x44000000; + xSPI0_CS1_SPACE_MIRROR_LENGTH = 0x4000000; + xSPI1_CS0_SPACE_MIRROR_START = 0x48000000; + xSPI1_CS0_SPACE_MIRROR_LENGTH = 0x4000000; + CS0_SPACE_MIRROR_START = 0x50000000; + CS0_SPACE_MIRROR_LENGTH = 0x4000000; + CS2_SPACE_MIRROR_START = 0x54000000; + CS2_SPACE_MIRROR_LENGTH = 0x4000000; + CS3_SPACE_MIRROR_START = 0x58000000; + CS3_SPACE_MIRROR_LENGTH = 0x4000000; + CS5_SPACE_MIRROR_START = 0x5C000000; + CS5_SPACE_MIRROR_LENGTH = 0x4000000; + xSPI0_CS0_SPACE_START = 0x60000000; + xSPI0_CS0_SPACE_LENGTH = 0x4000000; + xSPI0_CS1_SPACE_START = 0x64000000; + xSPI0_CS1_SPACE_LENGTH = 0x4000000; + xSPI1_CS0_SPACE_START = 0x68000000; + xSPI1_CS0_SPACE_LENGTH = 0x4000000; + CS0_SPACE_START = 0x70000000; + CS0_SPACE_LENGTH = 0x4000000; + CS2_SPACE_START = 0x74000000; + CS2_SPACE_LENGTH = 0x4000000; + CS3_SPACE_START = 0x78000000; + CS3_SPACE_LENGTH = 0x4000000; + CS5_SPACE_START = 0x7C000000; + CS5_SPACE_LENGTH = 0x4000000; + RAM_NS_BUFFER_LENGTH = 0x6100; + CR52_0 = 1; diff --git a/projects/etherkit_ethercat_cherryecat/mklinks.bat b/projects/etherkit_ethercat_cherryecat/mklinks.bat new file mode 100644 index 00000000..24046fcd --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/mklinks.bat @@ -0,0 +1,6 @@ +@echo off +%1 mshta vbscript:CreateObject("Shell.Application").ShellExecute("cmd.exe","/c %~s0 ::","","runas",1)(window.close)&&exit +cd /d "%~dp0" +@echo on +mklink /D rt-thread ..\..\rt-thread +mklink /D libraries ..\..\libraries \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/mklinks.sh b/projects/etherkit_ethercat_cherryecat/mklinks.sh new file mode 100644 index 00000000..04fe15d6 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/mklinks.sh @@ -0,0 +1,3 @@ +#!/bin/bash +ln -s ../../rt-thread rt-thread +ln -s ../../libraries libraries diff --git a/projects/etherkit_ethercat_cherryecat/ozone_scons.jdebug b/projects/etherkit_ethercat_cherryecat/ozone_scons.jdebug new file mode 100644 index 00000000..0e4132ec --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/ozone_scons.jdebug @@ -0,0 +1,361 @@ +/********************************************************************* +* (c) SEGGER Microcontroller GmbH * +* The Embedded Experts * +* www.segger.com * +********************************************************************** + +File : ozone_scons.jdebug +Created : 2 Dec 2024 10:53 +Ozone Version : V3.38b +*/ + +/********************************************************************* +* +* OnProjectLoad +* +* Function description +* Project load routine. Required. +* +********************************************************************** +*/ +void OnProjectLoad (void) { + // + // Dialog-generated settings + // + Project.AddPathSubstitute ("./", "$(ProjectDir)"); + Project.AddPathSubstitute ("./", "$(ProjectDir)"); + Project.SetDevice ("R9A07G084M04"); + Project.SetHostIF ("USB", ""); + Project.SetTargetIF ("SWD"); + Project.SetTIFSpeed ("50 MHz"); + Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-R52_AArch32.svd"); + Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-R52_AArch32.svd"); + // + // User settings + // + File.Open ("$(ProjectDir)/rtthread.elf"); +} + +/********************************************************************* +* +* OnStartupComplete +* +* Function description +* Called when program execution has reached/passed +* the startup completion point. Optional. +* +********************************************************************** +*/ +//void OnStartupComplete (void) { +//} + +/********************************************************************* +* +* TargetReset +* +* Function description +* Replaces the default target device reset routine. Optional. +* +* Notes +* This example demonstrates the usage when +* debugging an application in RAM on a Cortex-M target device. +* +********************************************************************** +*/ +void TargetReset (void) { +// +// unsigned int SP; +// unsigned int PC; +// unsigned int VectorTableAddr; +// +// VectorTableAddr = Elf.GetBaseAddr(); +// // +// // Set up initial stack pointer +// // +// if (VectorTableAddr != 0xFFFFFFFF) { +// SP = Target.ReadU32(VectorTableAddr); +// Target.SetReg("SP", SP); +// } +// // +// // Set up entry point PC +// // +// PC = Elf.GetEntryPointPC(); +// +// if (PC != 0xFFFFFFFF) { +// Target.SetReg("PC", PC); +// } else if (VectorTableAddr != 0xFFFFFFFF) { +// PC = Target.ReadU32(VectorTableAddr + 4); +// Target.SetReg("PC", PC); +// } else { +// Util.Error("Project file error: failed to set entry point PC", 1); +// } +} + +/********************************************************************* +* +* BeforeTargetReset +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void BeforeTargetReset (void) { +//} + +/********************************************************************* +* +* AfterTargetReset +* +* Function description +* Event handler routine. Optional. +* The default implementation initializes SP and PC to reset values. +** +********************************************************************** +*/ +void AfterTargetReset (void) { + _SetupTarget(); +} + +/********************************************************************* +* +* DebugStart +* +* Function description +* Replaces the default debug session startup routine. Optional. +* +********************************************************************** +*/ +//void DebugStart (void) { +//} + +/********************************************************************* +* +* TargetConnect +* +* Function description +* Replaces the default target IF connection routine. Optional. +* +********************************************************************** +*/ +//void TargetConnect (void) { +//} + +/********************************************************************* +* +* BeforeTargetConnect +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void BeforeTargetConnect (void) { +//} + +/********************************************************************* +* +* AfterTargetConnect +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void AfterTargetConnect (void) { +//} + +/********************************************************************* +* +* TargetDownload +* +* Function description +* Replaces the default program download routine. Optional. +* +********************************************************************** +*/ +//void TargetDownload (void) { +//} + +/********************************************************************* +* +* BeforeTargetDownload +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void BeforeTargetDownload (void) { +//} + +/********************************************************************* +* +* AfterTargetDownload +* +* Function description +* Event handler routine. Optional. +* The default implementation initializes SP and PC to reset values. +* +********************************************************************** +*/ +void AfterTargetDownload (void) { + _SetupTarget(); +} + +/********************************************************************* +* +* BeforeTargetDisconnect +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void BeforeTargetDisconnect (void) { +//} + +/********************************************************************* +* +* AfterTargetDisconnect +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void AfterTargetDisconnect (void) { +//} + +/********************************************************************* +* +* AfterTargetHalt +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void AfterTargetHalt (void) { +//} + +/********************************************************************* +* +* BeforeTargetResume +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void BeforeTargetResume (void) { +//} + +/********************************************************************* +* +* OnSnapshotLoad +* +* Function description +* Called upon loading a snapshot. Optional. +* +* Additional information +* This function is used to restore the target state in cases +* where values cannot simply be written to the target. +* Typical use: GPIO clock needs to be enabled, before +* GPIO is configured. +* +********************************************************************** +*/ +//void OnSnapshotLoad (void) { +//} + +/********************************************************************* +* +* OnSnapshotSave +* +* Function description +* Called upon saving a snapshot. Optional. +* +* Additional information +* This function is usually used to save values of the target +* state which can either not be trivially read, +* or need to be restored in a specific way or order. +* Typically use: Memory Mapped Registers, +* such as PLL and GPIO configuration. +* +********************************************************************** +*/ +//void OnSnapshotSave (void) { +//} + +/********************************************************************* +* +* OnError +* +* Function description +* Called when an error ocurred. Optional. +* +********************************************************************** +*/ +//void OnError (void) { +//} + +/********************************************************************* +* +* AfterProjectLoad +* +* Function description +* After Project load routine. Optional. +* +********************************************************************** +*/ +//void AfterProjectLoad (void) { +//} + +/********************************************************************* +* +* _SetupTarget +* +* Function description +* Setup the target. +* Called by AfterTargetReset() and AfterTargetDownload(). +* +* Auto-generated function. May be overridden by Ozone. +* +********************************************************************** +*/ +void _SetupTarget(void) { + // + // this function is intentionally empty because both inital PC and + // initial SP were chosen not to be set + // + + U64 PC; + U32 cpsr; + int ElfClass; + + ElfClass = Elf.GetFileClass(); + // + // Set up initial PC + // + PC = Elf.GetExprValue("system_init"); + if (PC != 0xFFFFFFFF) { + if (ElfClass == ELF_CLASS_64) { + // + // AArch64 + // + Target.SetReg("PC", PC); + } else if (ElfClass == ELF_CLASS_32) { + // + // AArch32 + // + Exec.Reset(); + Target.SetReg("CPSR", 0x01da); + Target.SetReg("R15 (PC)", PC); + } else { + Util.Error("Project script error: failed to set initial PC", 1); + } + } else { + Util.Error("Project script error: failed to set initial PC", 1); + } +} diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/.clang-format b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/.clang-format new file mode 100644 index 00000000..336989de --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/.clang-format @@ -0,0 +1,171 @@ +# clang-format configuration file. Intended for clang-format >= 11.0 +# +# For more information, see: +# +# https://clang.llvm.org/docs/ClangFormat.html +# https://clang.llvm.org/docs/ClangFormatStyleOptions.html +# +--- +# 语言: None, Cpp, Java, JavaScript, ObjC, Proto, TableGen, TextProto +Language: Cpp +# BasedOnStyle: LLVM +# 访问说明符(public、private等)的偏移 +AccessModifierOffset: -4 +# 开括号(开圆括号、开尖括号、开方括号)后的对齐: Align, DontAlign, AlwaysBreak(总是在开括号后换行) +AlignAfterOpenBracket: Align +# 连续赋值时，对齐所有等号 +AlignConsecutiveAssignments: false +# 对齐位域 +AlignConsecutiveBitFields: true +# 连续声明时，对齐所有声明的变量名 +AlignConsecutiveDeclarations: false +# 连续宏时，进行对齐 +AlignConsecutiveMacros: true +# 左对齐逃脱换行(使用反斜杠换行)的反斜杠 +AlignEscapedNewlines: Left +# 水平对齐二元和三元表达式的操作数 +AlignOperands: true +# 对齐连续的尾随的注释 +AlignTrailingComments: true +# 允许函数声明的所有参数在放在下一行 +AllowAllParametersOfDeclarationOnNextLine: false +# 允许短的块放在同一行 +AllowShortBlocksOnASingleLine: false +# 允许短的case标签放在同一行 +AllowShortCaseLabelsOnASingleLine: false +# 允许短的函数放在同一行: None, InlineOnly(定义在类中), Empty(空函数), Inline(定义在类中，空函数), All +AllowShortFunctionsOnASingleLine: None +# 允许短的if语句保持在同一行 +AllowShortIfStatementsOnASingleLine: false +# 允许短的循环保持在同一行 +AllowShortLoopsOnASingleLine: false +# 总是在定义返回类型后换行(deprecated) +AlwaysBreakAfterDefinitionReturnType: None +# 总是在返回类型后换行: None, All, TopLevel(顶级函数，不包括在类中的函数), +# AllDefinitions(所有的定义，不包括声明), TopLevelDefinitions(所有的顶级函数的定义) +AlwaysBreakAfterReturnType: None +# 总是在多行string字面量前换行 +AlwaysBreakBeforeMultilineStrings: false +# 总是在template声明后换行 +AlwaysBreakTemplateDeclarations: false +# false表示函数实参要么都在同一行，要么都各自一行 +BinPackArguments: true +# false表示所有形参要么都在同一行，要么都各自一行 +BinPackParameters: true +# 大括号换行，只有当BreakBeforeBraces设置为Custom时才有效 +BraceWrapping: + AfterClass: false + AfterControlStatement: false + AfterEnum: false + AfterFunction: true + AfterNamespace: false + AfterObjCDeclaration: false + AfterStruct: false + AfterUnion: false + AfterExternBlock: false # Unknown to clang-format-5.0 + BeforeCatch: false + BeforeElse: false + IndentBraces: false + SplitEmptyFunction: true # Unknown to clang-format-4.0 + SplitEmptyRecord: true # Unknown to clang-format-4.0 + SplitEmptyNamespace: true # Unknown to clang-format-4.0 +# 在二元运算符前换行: None(在操作符后换行), NonAssignment(在非赋值的操作符前换行), All(在操作符前换行) +BreakBeforeBinaryOperators: None +BreakBeforeBraces: Custom +#BreakBeforeInheritanceComma: false # Unknown to clang-format-4.0 +# 在三元运算符前换行 +BreakBeforeTernaryOperators: false +# 在构造函数的初始化列表的逗号前换行 +BreakConstructorInitializersBeforeComma: false +BreakAfterJavaFieldAnnotations: false +BreakStringLiterals: false +# 每行字符的限制，0表示没有限制 +ColumnLimit: 0 +# 描述具有特殊意义的注释的正则表达式，它不应该被分割为多行或以其它方式改变 +CommentPragmas: '^ IWYU pragma:' +CompactNamespaces: false # Unknown to clang-format-4.0 +# 构造函数的初始化列表要么都在同一行，要么都各自一行 +ConstructorInitializerAllOnOneLineOrOnePerLine: false +# 构造函数的初始化列表的缩进宽度 +ConstructorInitializerIndentWidth: 4 +# 延续的行的缩进宽度 +ContinuationIndentWidth: 4 +# 去除C++11的列表初始化的大括号{后和}前的空格 +Cpp11BracedListStyle: false +# 继承最常用的指针和引用的对齐方式 +DerivePointerAlignment: false +# 关闭格式化 +DisableFormat: false +ForEachMacros: + - 'SHELL_EXPORT_CMD' + +# 自动检测函数的调用和定义是否被格式为每行一个参数(Experimental) +ExperimentalAutoDetectBinPacking: false +# 缩进case标签 +IndentCaseLabels: true +# 缩进宽度 +IndentWidth: 4 +# 函数返回类型换行时，缩进函数声明或函数定义的函数名 +IndentWrappedFunctionNames: false +# 保留在块开始处的空行 +KeepEmptyLinesAtTheStartOfBlocks: false +# 开始一个块的宏的正则表达式 +MacroBlockBegin: '' +# 结束一个块的宏的正则表达式 +MacroBlockEnd: '' +# 连续空行的最大数量 +MaxEmptyLinesToKeep: 1 +# 命名空间的缩进: None, Inner(缩进嵌套的命名空间中的内容), All +NamespaceIndentation: None +# 使用ObjC块时缩进宽度 +ObjCBlockIndentWidth: 4 +# 在ObjC的@property后添加一个空格 +ObjCSpaceAfterProperty: false +# 在ObjC的protocol列表前添加一个空格 +ObjCSpaceBeforeProtocolList: true +# 在call(后对函数调用换行的penalty +PenaltyBreakBeforeFirstCallParameter: 30 +# 在一个注释中引入换行的penalty +PenaltyBreakComment: 10 +# 第一次在<<前换行的penalty +PenaltyBreakFirstLessLess: 0 +# 在一个字符串字面量中引入换行的penalty +PenaltyBreakString: 10 +# 对于每个在行字符数限制之外的字符的penalty +PenaltyExcessCharacter: 100 +# 将函数的返回类型放到它自己的行的penalty +PenaltyReturnTypeOnItsOwnLine: 60 +# 指针和引用的对齐: Left, Right, Middle +PointerAlignment: Right +# 允许重新排版注释 +ReflowComments: false +# 允许排序#include +SortIncludes: false +# 在C风格类型转换后添加空格 +SpaceAfterCStyleCast: false +# 在赋值运算符之前添加空格 +SpaceBeforeAssignmentOperators: true +# 开圆括号之前添加一个空格: Never, ControlStatements, Always +SpaceBeforeParens: ControlStatements +# 在空的圆括号中添加空格 +SpaceInEmptyParentheses: false +# 在尾随的评论前添加的空格数(只适用于//) +SpacesBeforeTrailingComments: 1 +# 在尖括号的<后和>前添加空格 +SpacesInAngles: false +# 在容器(ObjC和JavaScript的数组和字典等)字面量中添加空格 +SpacesInContainerLiterals: false +# 在C风格类型转换的括号中添加空格 +SpacesInCStyleCastParentheses: false +# 在圆括号的(后和)前添加空格 +SpacesInParentheses: false +# 在方括号的[后和]前添加空格，lamda表达式和未指明大小的数组的声明不受影响 +SpacesInSquareBrackets: false +# 标准: Cpp03, Cpp11, Auto +Standard: Cpp03 +# tab宽度 +TabWidth: 4 +# 使用tab字符: Never, ForIndentation, ForContinuationAndIndentation, Always +UseTab: Never +... + diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/.gitattributes b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/.gitattributes new file mode 100644 index 00000000..74d8c6b2 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/.gitattributes @@ -0,0 +1,47 @@ +*.c linguist-language=C +*.C linguist-language=C +*.h linguist-language=C +*.H linguist-language=C + +* text=auto + +*.S text +*.asm text +*.c text +*.cc text +*.cpp text +*.cxx text +*.h text +*.htm text +*.html text +*.in text +*.ld text +*.m4 text +*.mak text +*.mk text +*.py text +*.rb text +*.s text +*.sct text +*.sh text +*.txt text +*.xml text +SConscript text +Makefile text +AUTHORS text +COPYING text + +*.LZO -text +*.Opt -text +*.Uv2 -text +*.ewp -text +*.eww -text +*.vcproj -text +*.bat -text +*.dos -text +*.icf -text +*.inf -text +*.ini -text +*.sct -text +*.xsd -text +Jamfile -text \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/.github/workflows/build_demo.yml b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/.github/workflows/build_demo.yml new file mode 100644 index 00000000..9d6fbc28 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/.github/workflows/build_demo.yml @@ -0,0 +1,36 @@ +name: Build Demo + +on: + push: + branches: [ master ] + pull_request: + branches: [ master ] + +jobs: + build: + runs-on: ubuntu-latest + steps: + - name: Checkout repository + uses: actions/checkout@v3 + + - name: Install dependencies + run: sudo apt-get update && sudo apt-get install -y cmake ninja-build + + - name: Download hpm_sdk + run: | + cd ~ + git clone https://github.com/hpmicro/hpm_sdk.git + + - name: Download RISC-V toolchain + run: | + cd ~ + wget https://github.com/hpmicro/riscv-gnu-toolchain/releases/download/2023.10.18/rv32imac_zicsr_zifencei_multilib_b_ext-linux.tar.gz + tar -xzf rv32imac_zicsr_zifencei_multilib_b_ext-linux.tar.gz + + - name: Build demo + run: | + cd demo/hpmicro + export HPM_SDK_BASE=~/hpm_sdk + export GNURISCV_TOOLCHAIN_PATH=~/rv32imac_zicsr_zifencei_multilib_b_ext-linux + export HPM_SDK_TOOLCHAIN_VARIANT= + cmake -S . -B build -GNinja -DBOARD=hpm6800evk -DHPM_BUILD_TYPE=ram -DCMAKE_BUILD_TYPE=debug;cmake --build build diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/.gitignore b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/.gitignore new file mode 100644 index 00000000..cf458423 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/.gitignore @@ -0,0 +1,23 @@ +.vscode +build +**/Drivers/** +**/MDK-ARM/DebugConfig/** +**/MDK-ARM/RTE/** +**/obj/** +**/RET/** +**/Listings/** +**/Objects/** +*.map +*.o +*.d +*.htm +*.dep +*.lnp +*.iex +*.lst +*.axf +*.crf +*.hex +*.Bak +*.uvguix.* +*.scvd \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/.readthedocs.yaml b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/.readthedocs.yaml new file mode 100644 index 00000000..ed14f4de --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/.readthedocs.yaml @@ -0,0 +1,35 @@ +# Read the Docs configuration file for Sphinx projects +# See https://docs.readthedocs.io/en/stable/config-file/v2.html for details + +# Required +version: 2 + +# Set the OS, Python version and other tools you might need +build: + os: ubuntu-22.04 + tools: + python: "3.11" + # You can also specify other tool versions: + # nodejs: "20" + # rust: "1.70" + # golang: "1.20" + +# Build documentation in the "docs/" directory with Sphinx +sphinx: + configuration: docs/source/conf.py + # You can configure Sphinx to use a different builder, for instance use the dirhtml builder for simpler URLs + # builder: "dirhtml" + # Fail on all warnings to avoid broken references + # fail_on_warning: true + +# Optionally build your docs in additional formats such as PDF and ePub +# formats: +# - pdf +# - epub + +# Optional but recommended, declare the Python requirements required +# to build your documentation +# See https://docs.readthedocs.io/en/stable/guides/reproducible-builds.html +python: + install: + - requirements: docs/requirements.txt \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/CMakeLists.txt b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/CMakeLists.txt new file mode 100644 index 00000000..bfcc5abc --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/CMakeLists.txt @@ -0,0 +1,39 @@ +if(CONFIG_CHERRYECAT) + + list(APPEND cherryec_incs + ${CMAKE_CURRENT_LIST_DIR}/include + ) + + list(APPEND cherryec_srcs + ${CMAKE_CURRENT_LIST_DIR}/src/ec_cmd.c + ${CMAKE_CURRENT_LIST_DIR}/src/ec_coe.c + ${CMAKE_CURRENT_LIST_DIR}/src/ec_common.c + ${CMAKE_CURRENT_LIST_DIR}/src/ec_datagram.c + ${CMAKE_CURRENT_LIST_DIR}/src/ec_foe.c + ${CMAKE_CURRENT_LIST_DIR}/src/ec_mailbox.c + ${CMAKE_CURRENT_LIST_DIR}/src/ec_master.c + ${CMAKE_CURRENT_LIST_DIR}/src/ec_netdev.c + ${CMAKE_CURRENT_LIST_DIR}/src/ec_perf.c + ${CMAKE_CURRENT_LIST_DIR}/src/ec_sii.c + ${CMAKE_CURRENT_LIST_DIR}/src/ec_slave.c + ${CMAKE_CURRENT_LIST_DIR}/src/ec_timestamp.c + ${CMAKE_CURRENT_LIST_DIR}/src/phy/chry_phy.c + ) + + if(DEFINED CONFIG_CHERRYECAT_OSAL) + if("${CONFIG_CHERRYECAT_OSAL}" STREQUAL "freertos") + list(APPEND cherryec_srcs ${CMAKE_CURRENT_LIST_DIR}/osal/ec_osal_freertos.c) + elseif("${CONFIG_CHERRYECAT_OSAL}" STREQUAL "rtthread") + list(APPEND cherryec_srcs ${CMAKE_CURRENT_LIST_DIR}/osal/ec_osal_rtthread.c) + elseif("${CONFIG_CHERRYECAT_OSAL}" STREQUAL "threadx") + list(APPEND cherryec_srcs ${CMAKE_CURRENT_LIST_DIR}/osal/ec_osal_threadx.c) + endif() + endif() + + if(HPM_SDK_BASE) + list(APPEND cherryec_srcs port/netdev_hpmicro.c) + sdk_inc(${cherryec_incs}) + sdk_src(${cherryec_srcs}) + endif() + +endif() \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/LICENSE b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/LICENSE new file mode 100644 index 00000000..261eeb9e --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/LICENSE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/README.md b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/README.md new file mode 100644 index 00000000..0dd6330d --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/README.md @@ -0,0 +1,111 @@ +**English | [简体中文](README_zh.md)** + +

CherryECAT

+

+ + + +

+ +CherryECAT is a tiny and beautiful, high real-time and low-jitter EtherCAT master stack, specially designed for MCUs running with RTOS. + +## Feature + +- ~ 4K ram, ~32K flash(24K + 8K shell cmd + debug log) +- Asynchronous queue-based transfer (one transfer can carry multiple datagrams) +- Zero-copy technology: directly use enet tx/rx buffer to fill and parse ethercat data +- Support hot-plugging + - Automatic scanning bus + - Automatic updating slave information when the topology changes +- Support automatic monitoring slave status +- Support distributed clocks +- Support CANopen over EtherCAT(COE) +- Support File over EtherCAT(FOE) +- Support Ethernet over EtherCAT(EOE) +- Support Slave SII access +- Support Slave register access +- Support multi master +- Support backup redundancy +- Minimum PDO cyclic time < 40 us (depends on master and slave hardware) +- Support multi cyclic time(every slave can use different proportional cyclic time) +- Support ethercat cmd with shell, ref to IgH + +## Hardware limitations + +- **Master** + - CPU (cache > 16K, memcpy speed > 100MB/s) + - ENET must support descriptor dma and iperf with lwip > 90 Mbps + - Code must run in ram, ignore if no dc + - Must support High-Precision Timer (jitter < 1us) + - Must support High-Precision timestamp (ARM DWT/RISC-V MCYCLE) + - Must support long long print + +- **Slave** + - Must support COE + - Must support sdo complete access + - SII must have sync manager information + +## Shell cmd + +![ethercat](docs/assets/ethercat.png) +![ethercat](docs/assets/ethercat1.png) +![ethercat](docs/assets/ethercat2.png) +![ethercat](docs/assets/ethercat3.png) +![ethercat](docs/assets/ethercat4.png) +![ethercat](docs/assets/ethercat5.png) +![ethercat](docs/assets/ethercat6.png) +![ethercat](docs/assets/ethercat7.png) +![ethercat](docs/assets/ethercat8.png) + +## Tool + +- esi_parser + +Use **esi_parser.py** to generate slave eeprom information and download eeprom to slave. + +``` +python ./esi_parser.py ECAT_CIA402_ESI.xml eeprom.bin eeprom.h + +Parsing XML file: ECAT_CIA402_ESI.xml +Parsed XML: Vendor=0x0048504D, Product=0x00000003 +Device Name: ECAT_CIA402 +Mailbox RX: 0x1000(128) +Mailbox TX: 0x1080(128) +Generating EEPROM data... +✓ Successfully converted 'ECAT_CIA402_ESI.xml' to 'eeprom.bin' +✓ Generated 2048 bytes of EEPROM data +✓ Vendor ID: 0x0048504D +✓ Product Code: 0x00000003 +✓ Revision: 0x00000001 +✓ Device Name: ECAT_CIA402 +✓ Generated C header file: eeprom.h +``` + +- eni_parser + +Use **eni_parser.py** to generate CherryECAT slave sync config. + +``` +python ./eni_parser.py ECAT_CIA402_ENI.xml sync_config.h + +Parsing ENI file: ECAT_CIA402_ENI.xml +Generating C code... +✓ Successfully converted 'ECAT_CIA402_ENI.xml' to 'sync_config.h' +✓ Generated C code for 1 slave(s) +✓ Slave 1: + - RxPDO 0x1602: 3 entries + - TxPDO 0x1A02: 3 entries +``` + +## Support Boards + +- HPM6750EVK2/HPM6800EVK/**HPM5E00EVK**(hybrid internal) +- RT-Thread RZN2L-EtherKit + +## Contact + +QQ group: 563650597 + +## License + +FOE,EOE and Backup redundancy features are available for commercial charge; other are free to use \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/README_zh.md b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/README_zh.md new file mode 100644 index 00000000..d606147f --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/README_zh.md @@ -0,0 +1,111 @@ +**[English](README.md) | 简体中文** + +

CherryECAT

+

+ + + +

+ +CherryECAT 是一个小而美的、高实时性、低抖动的 EtherCAT 主机协议栈，专为跑在 RTOS 下的 MCU 设计。 + +## 特性 + +- ~ 4K ram，~32K flash（24K + 8K shell cmd + debug log） +- 异步队列式传输（一次传输可以携带多个 datagram） +- 零拷贝技术：直接使用 enet tx/rx buffer 填充和解析 ethercat 数据 +- 支持热插拔 + - 自动扫描总线 + - 拓扑结构发生变化时自动更新 Slave 信息 +- 支持自动监控 Slave 状态 +- 支持分布式时钟 +- 支持 CANopen over EtherCAT (COE) +- 支持 File over EtherCAT(FOE) +- 支持 Ethernet over EtherCAT(EOE) +- 支持 Slave SII 读写 +- 支持 Slave 寄存器读写 +- 支持多主站 +- 支持备份冗余 +- 最小 PDO cyclic time < 40 us (实际数值受主站硬件和从站硬件影响) +- 支持多周期（每个从站可以使用不同的成比例的周期） +- 支持 ethercat 命令行交互，参考 IgH + +## 硬件限制 + +- 主站 + - CPU (cache > 16K, memcpy speed > 100MB/s) + - 以太网必须支持 descriptor dma 并且 iperf with lwip > 90 Mbps + - 代码必须跑在 ram 上，如果不使用 DC 同步则忽视 + - 必须支持高精度定时器（抖动小于 1us） + - 必须支持高精度时间戳 (ARM DWT/RISC-V MCYCLE) + - 必须支持 64 位打印 + +- 从站 + - 必须支持 COE + - 必须支持 sdo complete access + - SII 必须携带 sync manager 信息 + +## Shell 命令 + +![ethercat](docs/assets/ethercat.png) +![ethercat](docs/assets/ethercat1.png) +![ethercat](docs/assets/ethercat2.png) +![ethercat](docs/assets/ethercat3.png) +![ethercat](docs/assets/ethercat4.png) +![ethercat](docs/assets/ethercat5.png) +![ethercat](docs/assets/ethercat6.png) +![ethercat](docs/assets/ethercat7.png) +![ethercat](docs/assets/ethercat8.png) + +## 工具 + +- esi_parser + +使用 **esi_parser.py** 生成从站 eeprom 信息用于烧录从站 + +``` +python ./esi_parser.py ECAT_CIA402_ESI.xml eeprom.bin eeprom.h + +Parsing XML file: ECAT_CIA402_ESI.xml +Parsed XML: Vendor=0x0048504D, Product=0x00000003 +Device Name: ECAT_CIA402 +Mailbox RX: 0x1000(128) +Mailbox TX: 0x1080(128) +Generating EEPROM data... +✓ Successfully converted 'ECAT_CIA402_ESI.xml' to 'eeprom.bin' +✓ Generated 2048 bytes of EEPROM data +✓ Vendor ID: 0x0048504D +✓ Product Code: 0x00000003 +✓ Revision: 0x00000001 +✓ Device Name: ECAT_CIA402 +✓ Generated C header file: eeprom.h +``` + +- eni_parser + +使用 **eni_parser.py** 生成 CherryECAT slave sync 配置 + +``` +python ./eni_parser.py ECAT_CIA402_ENI.xml sync_config.h + +Parsing ENI file: ECAT_CIA402_ENI.xml +Generating C code... +✓ Successfully converted 'ECAT_CIA402_ENI.xml' to 'sync_config.h' +✓ Generated C code for 1 slave(s) +✓ Slave 1: + - RxPDO 0x1602: 3 entries + - TxPDO 0x1A02: 3 entries +``` + +## 支持的开发板 + +- HPM6750EVK2/HPM6800EVK/**HPM5E00EVK**(hybrid internal) +- RT-Thread RZN2L-EtherKit + +## 联系 + +QQ group: 563650597 + +## License + +FOE，EOE，备份冗余功能为商用收费，其余功能免费商用 \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/SConscript b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/SConscript new file mode 100644 index 00000000..0427c62f --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/SConscript @@ -0,0 +1,35 @@ +from building import * + +cwd = GetCurrentDir() +path = [cwd + '/include'] +src = [] + +LIBS = [] +LIBPATH = [] +CPPDEFINES = [] + +src += Glob('src/ec_cmd.c') +src += Glob('src/ec_coe.c') +src += Glob('src/ec_common.c') +src += Glob('src/ec_datagram.c') +src += Glob('src/ec_foe.c') +src += Glob('src/ec_mailbox.c') +src += Glob('src/ec_master.c') +src += Glob('src/ec_netdev.c') +src += Glob('src/ec_perf.c') +src += Glob('src/ec_sii.c') +src += Glob('src/ec_slave.c') +src += Glob('src/ec_timestamp.c') +src += Glob('src/phy/chry_phy.c') +src += Glob('osal/ec_osal_rtthread.c') + +if GetDepend(['PKG_CHERRYECAT_NETDEV_HPMICRO']): + src += Glob('port/netdev_hpmicro.c') + +if GetDepend(['PKG_CHERRYECAT_NETDEV_RENESAS']): + src += Glob('port/netdev_renesas.c') + +group = DefineGroup('CherryECAT', src, depend = ['PKG_USING_CHERRYECAT'], LIBS = LIBS, LIBPATH=LIBPATH, CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') + diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/VERSION b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/VERSION new file mode 100644 index 00000000..d57fdb9f --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/VERSION @@ -0,0 +1,5 @@ +VERSION_MAJOR = 0 +VERSION_MINOR = 1 +PATCHLEVEL = 0 +VERSION_TWEAK = 0 +EXTRAVERSION = 0 diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/cherryec_config_template.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/cherryec_config_template.h new file mode 100644 index 00000000..5af4f443 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/cherryec_config_template.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef EC_CONFIG_H +#define EC_CONFIG_H + +#define CONFIG_EC_PRINTF(...) printf(__VA_ARGS__) + +#ifndef CONFIG_EC_DBG_LEVEL +#define CONFIG_EC_DBG_LEVEL EC_DBG_INFO +#endif + +#ifndef CONFIG_EC_SLAVE_DBG_LEVEL +#define CONFIG_EC_SLAVE_DBG_LEVEL EC_DBG_INFO +#endif + +/* Enable print with color */ +#define CONFIG_EC_PRINTF_COLOR_ENABLE + +#define EC_FAST_CODE_SECTION + +#ifndef CONFIG_EC_MAX_NETDEVS +#define CONFIG_EC_MAX_NETDEVS 1 +#endif + +#ifndef CONFIG_EC_NONPERIOD_PRIO +#define CONFIG_EC_NONPERIOD_PRIO 0 +#endif + +#ifndef CONFIG_EC_NONPERIOD_STACKSIZE +#define CONFIG_EC_NONPERIOD_STACKSIZE 2048 +#endif + +#ifndef CONFIG_EC_NONPERIOD_INTERVAL_MS +#define CONFIG_EC_NONPERIOD_INTERVAL_MS 10 +#endif + +#ifndef CONFIG_EC_NONPERIOD_WAITERS +#define CONFIG_EC_NONPERIOD_WAITERS 20 +#endif + +#ifndef CONFIG_EC_SCAN_PRIO +#define CONFIG_EC_SCAN_PRIO 1 +#endif + +#ifndef CONFIG_EC_SCAN_STACKSIZE +#define CONFIG_EC_SCAN_STACKSIZE 2048 +#endif + +#ifndef CONFIG_EC_SCAN_INTERVAL_MS +#define CONFIG_EC_SCAN_INTERVAL_MS 100 +#endif + +#ifndef CONFIG_EC_PER_SM_MAX_PDOS +#define CONFIG_EC_PER_SM_MAX_PDOS 8 +#endif + +#ifndef CONFIG_EC_PER_PDO_MAX_PDO_ENTRIES +#define CONFIG_EC_PER_PDO_MAX_PDO_ENTRIES 8 +#endif + +#define CONFIG_EC_PERF_ENABLE +#define CONFIG_EC_CMD_ENABLE +// #define CONFIG_EC_TIMESTAMP_CUSTOM +// #define CONFIG_EC_PHY_CUSTOM + +#ifndef CONFIG_EC_MAX_PDO_BUFSIZE +#define CONFIG_EC_MAX_PDO_BUFSIZE 2048 +#endif + +#ifndef CONFIG_EC_MAX_ENET_TXBUF_COUNT +#define CONFIG_EC_MAX_ENET_TXBUF_COUNT 10 +#endif + +#ifndef CONFIG_EC_MAX_ENET_RXBUF_COUNT +#define CONFIG_EC_MAX_ENET_RXBUF_COUNT 10 +#endif + +// #define CONFIG_EC_FOE + +#endif \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/CMakeLists.txt b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/CMakeLists.txt new file mode 100644 index 00000000..1d05040f --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/CMakeLists.txt @@ -0,0 +1,49 @@ +# Copyright (c) 2021 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +cmake_minimum_required(VERSION 3.13) + +set(HPM_SDK_LD_NO_NANO_SPECS 1) + +set(CONFIG_FREERTOS 1) +# set(CONFIG_CHERRYRB 1) +set(CONFIG_CHERRYSH 1) +set(CONFIG_CHERRYSH_INTERFACE "uart") + +set(CONFIG_ENET_PHY 1) +set(APP_USE_ENET_PORT_COUNT 1) +#set(APP_USE_ENET_ITF_RGMII 1) +#set(APP_USE_ENET_ITF_RMII 1) +#set(APP_USE_ENET_PHY_DP83867 1) +#set(APP_USE_ENET_PHY_RTL8211 1) +#set(APP_USE_ENET_PHY_DP83848 1) +set(APP_USE_ENET_PHY_RTL8201 1) + +set(CONFIG_CHERRYECAT 1) +set(CONFIG_CHERRYECAT_OSAL "freertos") + +if(NOT (HPM_BUILD_TYPE STREQUAL "ram")) +message(FATAL_ERROR "Only support ram build for demo") +endif() + +#Set CONFIG_FREERTOS_TIMER_RESOURCE_GPTMR to use GPTMR as system's tick source +#set(CONFIG_FREERTOS_TIMER_RESOURCE_GPTMR 1) + +find_package(hpm-sdk REQUIRED HINTS $ENV{HPM_SDK_BASE}) + +project(cherryec) + +sdk_compile_definitions(-D__freertos_irq_stack_top=_stack) +sdk_compile_definitions(-DCONFIG_FREERTOS=1) +sdk_compile_definitions(-DUSE_NONVECTOR_MODE=1) +sdk_compile_definitions(-DDISABLE_IRQ_PREEMPTIVE=1) + +sdk_compile_options("-O2") + +sdk_inc(.) +sdk_inc(inc) +sdk_app_src(main.c) + +add_subdirectory(../.. cherryec) +generate_ses_project() + diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/inc/FreeRTOSConfig.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/inc/FreeRTOSConfig.h new file mode 100644 index 00000000..2a9cb035 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/inc/FreeRTOSConfig.h @@ -0,0 +1,152 @@ +/* + * Copyright (c) 2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/* + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + */ + +#include "board.h" + +#if (portasmHAS_MTIME == 0) +#define configMTIME_BASE_ADDRESS (0) +#define configMTIMECMP_BASE_ADDRESS (0) +#else +#define configMTIME_BASE_ADDRESS (HPM_MCHTMR_BASE) +#define configMTIMECMP_BASE_ADDRESS (HPM_MCHTMR_BASE + 8UL) +#endif + +#define configUSE_PREEMPTION 1 +#define configCPU_CLOCK_HZ ((uint32_t) 24000000) +#define configTICK_RATE_HZ ((TickType_t) 1000) +#define configMAX_PRIORITIES (32) +#define configMINIMAL_STACK_SIZE (256) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configGENERATE_RUN_TIME_STATS 0 + +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_MUTEXES 1 + +/* Memory allocation definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE ((size_t) (64 * 1024)) + +/* Hook function definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Set the following definitions to 1 to include the API function, or zero to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTaskAbortDelay 1 +#define INCLUDE_xTaskGetHandle 1 +#define INCLUDE_xSemaphoreGetMutexHolder 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 4 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE) + +/* Task priorities.*/ +#ifndef uartPRIMARY_PRIORITY + #define uartPRIMARY_PRIORITY (configMAX_PRIORITIES - 3) +#endif + +/* Normal assert() semantics without relying on the provision of an assert.h header file. */ +#define configASSERT(x) if ((x) == 0) { taskDISABLE_INTERRUPTS(); __asm volatile("ebreak"); for (;;); } + +/* + * The size of the global output buffer that is available for use when there + * are multiple command interpreters running at once (for example, one on a UART + * and one on TCP/IP). This is done to prevent an output buffer being defined by + * each implementation - which would waste RAM. In this case, there is only one + * command interpreter running. + */ + +/* + * The buffer into which output generated by FreeRTOS+CLI is placed. This must + * be at least big enough to contain the output of the task-stats command, as the + * example implementation does not include buffer overlow checking. + */ +#define configCOMMAND_INT_MAX_OUTPUT_SIZE 2096 +#define configINCLUDE_QUERY_HEAP_COMMAND 1 + +/* This file is included from assembler files - make sure C code is not included in assembler files. */ +#ifndef __ASSEMBLER__ + void vAssertCalled(const char *pcFile, unsigned long ulLine); + void vConfigureTickInterrupt(void); + void vClearTickInterrupt(void); + void vPreSleepProcessing(unsigned long uxExpectedIdleTime); + void vPostSleepProcessing(unsigned long uxExpectedIdleTime); +#endif /* __ASSEMBLER__ */ + +/****** Hardware/compiler specific settings. *******/ +/* + * The application must provide a function that configures a peripheral to + * create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT() + * in FreeRTOSConfig.h to call the function. + */ +#define configSETUP_TICK_INTERRUPT() vConfigureTickInterrupt() +#define configCLEAR_TICK_INTERRUPT() vClearTickInterrupt() + +/* + * The configPRE_SLEEP_PROCESSING() and configPOST_SLEEP_PROCESSING() macros + * allow the application writer to add additional code before and after the MCU is + * placed into the low power state respectively. The empty implementations + * provided in this demo can be extended to save even more power. + */ +#define configPRE_SLEEP_PROCESSING(uxExpectedIdleTime) vPreSleepProcessing(uxExpectedIdleTime); +#define configPOST_SLEEP_PROCESSING(uxExpectedIdleTime) vPostSleepProcessing(uxExpectedIdleTime); + + +/* Compiler specifics. */ +#define fabs(x) __builtin_fabs(x) + +/* Enable Hardware Stack Protection and Recording mechanism. */ +#define configHSP_ENABLE 0 + +/* Record the highest address of stack. */ +#if (configHSP_ENABLE == 1 && configRECORD_STACK_HIGH_ADDRESS != 1) +#define configRECORD_STACK_HIGH_ADDRESS 1 +#endif + +#endif /* FREERTOS_CONFIG_H */ diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/inc/cia402_def.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/inc/cia402_def.h new file mode 100644 index 00000000..0277b235 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/inc/cia402_def.h @@ -0,0 +1,136 @@ +#ifndef CIA402_DEF_H +#define CIA402_DEF_H + +/** +STRUCT_PACKED_START: Is defined before the typedef struct construct to pack the generic structures if necessary */ +#ifndef STRUCT_PACKED_START +#define STRUCT_PACKED_START ATTR_PACKED +#endif + +/** +STRUCT_PACKED_END: Is defined after the typedef struct {} construct to pack the generic structures if necessary */ +#ifndef STRUCT_PACKED_END +#define STRUCT_PACKED_END +#endif + +/*--------------------------------------------- +- ControlWord Commands (IEC61800_184e) +-----------------------------------------------*/ +#define CONTROLWORD_COMMAND_SHUTDOWN 0x0006 /**< \brief Shutdown command*/ +#define CONTROLWORD_COMMAND_SWITCHON 0x0007 /**< \brief Switch on command*/ +#define CONTROLWORD_COMMAND_SWITCHON_ENABLEOPERATION 0x000F /**< \brief Switch on & Enable command*/ +#define CONTROLWORD_COMMAND_DISABLEVOLTAGE 0x0000 /**< \brief Disable voltage command*/ +#define CONTROLWORD_COMMAND_QUICKSTOP 0x0002 /**< \brief Quickstop command*/ +#define CONTROLWORD_COMMAND_DISABLEOPERATION 0x0007 /**< \brief Disable operation command*/ +#define CONTROLWORD_COMMAND_ENABLEOPERATION 0x000F /**< \brief Enable operation command*/ +#define CONTROLWORD_COMMAND_FAULTRESET 0x0080 /**< \brief Fault reset command*/ + +/*--------------------------------------------- +- StatusWord Masks and Flags +-----------------------------------------------*/ +#define STATUSWORD_STATE_MASK 0x006F /**< \brief State mask*/ +#define STATUSWORD_VOLTAGE_ENABLED 0x0010 /**< \brief Indicate high voltage enabled*/ +#define STATUSWORD_WARNING 0x0080 /**< \brief Warning active*/ +#define STATUSWORD_MANUFACTORSPECIFIC 0x0100 /**< \brief Manufacturer specific*/ +#define STATUSWORD_INTERNAL_LIMIT 0x0800 /**< \brief Internal limit*/ +#define STATUSWORD_REMOTE 0x0200 /**< \brief Set if the control word is processed*/ +#define STATUSWORD_TARGET_REACHED 0x0400 /**< \brief Target reached*/ +#define STATUSWORD_INTERNALLIMITACTIVE 0x0800 /**< \brief Internal limit active*/ +#define STATUSWORD_DRIVE_FOLLOWS_COMMAND 0x1000 /**< \brief Drive follows command (used in cyclic synchronous modes)*/ + +/*--------------------------------------------- +- StatusWord +-----------------------------------------------*/ +#define STATUSWORD_STATE_NOTREADYTOSWITCHON 0x0000 /**< \brief Not ready to switch on*/ +#define STATUSWORD_STATE_SWITCHEDONDISABLED 0x0040 /**< \brief Switched on but disabled*/ +#define STATUSWORD_STATE_READYTOSWITCHON 0x0021 /**< \brief Ready to switch on*/ +#define STATUSWORD_STATE_SWITCHEDON 0x0023 /**< \brief Switched on*/ +#define STATUSWORD_STATE_OPERATIONENABLED 0x0027 /**< \brief Operation enabled*/ +#define STATUSWORD_STATE_QUICKSTOPACTIVE 0x0007 /**< \brief Quickstop active*/ +#define STATUSWORD_STATE_FAULTREACTIONACTIVE 0x000F /**< \brief Fault reaction active*/ +#define STATUSWORD_STATE_FAULT 0x0008 /**< \brief Fault state*/ + +/*--------------------------------------------- +- CiA402 Modes of Operation (object 0x6060) (IEC61800_184e) +-----------------------------------------------*/ +// -128 to -1 Manufacturer-specific operation modes +#define NO_MODE 0 /**< \brief No mode*/ +#define PROFILE_POSITION_MODE 1 /**< \brief Position Profile mode*/ +#define VELOCITY_MODE 2 /**< \brief Velocity mode*/ +#define PROFILE_VELOCITY_MOCE 3 /**< \brief Velocity Profile mode*/ +#define PROFILE_TORQUE_MODE 4 /**< \brief Torque Profile mode*/ +//5 reserved +#define HOMING_MODE 6 /**< \brief Homing mode*/ +#define INTERPOLATION_POSITION_MODE 7 /**< \brief Interpolation Position mode*/ +#define CYCLIC_SYNC_POSITION_MODE 8 /**< \brief Cyclic Synchronous Position mode*/ +#define CYCLIC_SYNC_VELOCITY_MODE 9 /**< \brief Cyclic Synchronous Velocity mode*/ +#define CYCLIC_SYNC_TORQUE_MODE 10 /**< \brief Cyclic Synchronous Torque mode*/ +//+11 to +127 reserved + +/** + * \addtogroup PDO Process Data Objects + * @{ + */ +/** \brief Data structure to handle the process data transmitted via 0x1A00 (csp/csv TxPDO)*/ +typedef struct STRUCT_PACKED_START +{ + uint16_t ObjStatusWord; /**< \brief Status word (0x6041)*/ + int32_t ObjPositionActualValue; /**< \brief Actual position (0x6064)*/ + int32_t ObjVelocityActualValue; /**< \brief Actual velocity (0x606C)*/ + int16_t ObjModesOfOperationDisplay; /**< \brief Current mode of operation (0x6061)*/ +}STRUCT_PACKED_END +TCiA402PDO1A00; + + +/** \brief Data structure to handle the process data transmitted via 0x1A01 (csp TxPDO)*/ +typedef struct STRUCT_PACKED_START +{ + uint16_t ObjStatusWord; /**< \brief Status word (0x6041)*/ + int32_t ObjPositionActualValue; /**< \brief Actual position (0x6064)*/ + uint16_t Padding16Bit; /**< \brief 16bit padding*/ +}STRUCT_PACKED_END +TCiA402PDO1A01; + + +/** \brief Data structure to handle the process data transmitted via 0x1A02 (csv TxPDO)*/ +typedef struct STRUCT_PACKED_START +{ + uint16_t ObjStatusWord; /**< \brief Status word (0x6041)*/ + int32_t ObjPositionActualValue; /**< \brief Actual position (0x6064)*/ + uint16_t Padding16Bit; /**< \brief 16bit padding*/ +}STRUCT_PACKED_END +TCiA402PDO1A02; + + +/** \brief Data structure to handle the process data transmitted via 0x1600 (csp/csv RxPDO)*/ +typedef struct STRUCT_PACKED_START +{ + uint16_t ObjControlWord; /**< \brief Control word (0x6040)*/ + int32_t ObjTargetPosition; /**< \brief Target position (0x607A)*/ + int32_t ObjTargetVelocity; /**< \brief Target velocity (0x60FF)*/ + int16_t ObjModesOfOperation; /**< \brief Mode of operation (0x6060)*/ +}STRUCT_PACKED_END +TCiA402PDO1600; + + +/** \brief Data structure to handle the process data transmitted via 0x1601 (csp RxPDO)*/ +typedef struct STRUCT_PACKED_START +{ + uint16_t ObjControlWord; /**< \brief Control word (0x6040)*/ + int32_t ObjTargetPosition; /**< \brief Target position (0x607A)*/ + uint16_t Padding16Bit; /**< \brief 16bit padding*/ +}STRUCT_PACKED_END +TCiA402PDO1601; + + +/** \brief Data structure to handle the process data transmitted via 0x1602 (csv RxPDO)*/ +typedef struct STRUCT_PACKED_START +{ + uint16_t ObjControlWord; /**< \brief Control word (0x6040)*/ + int32_t ObjTargetVelocity; /**< \brief Target velocity (0x60FF)*/ + uint16_t Padding16Bit; /**< \brief 16bit padding*/ +}STRUCT_PACKED_END +TCiA402PDO1602; +/** @}*/ + +#endif \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/inc/csh_config.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/inc/csh_config.h new file mode 100644 index 00000000..00ffd1a3 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/inc/csh_config.h @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2022, Egahp + * Copyright (c) 2024, HPMicro + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef CSH_CONFIG_H +#define CSH_CONFIG_H + +/*!< argument check */ +#define CONFIG_CSH_DEBUG 0 + +/*!< default row */ +#define CONFIG_CSH_DFTROW 25 + +/*!< default column */ +#define CONFIG_CSH_DFTCOL 80 + +/*!< history support <+550byte> */ +#define CONFIG_CSH_HISTORY 1 + +/*!< completion support <+1100byte> */ +#define CONFIG_CSH_COMPLETION 1 + +/*!< max completion item list count (use stack 4 x count byte) */ +#define CONFIG_CSH_MAX_COMPLETION 40 + +/*!< prompt edit support <+1000byte> */ +#define CONFIG_CSH_PROMPTEDIT 1 + +/*!< prompt segment count */ +#define CONFIG_CSH_PROMPTSEG 7 + +/*!< xterm support */ +#define CONFIG_CSH_XTERM 0 + +/*!< newline */ +#define CONFIG_CSH_NEWLINE "\r\n" + +/*!< tab space count */ +#define CONFIG_CSH_SPACE 4 + +/*!< independent ctrl map */ +#define CONFIG_CSH_CTRLMAP 0 + +/*!< independent alt map */ +#define CONFIG_CSH_ALTMAP 0 + +/*!< refresh prompt */ +#define CONFIG_CSH_REFRESH_PROMPT 1 + +/*!< no waiting for sget */ +#define CONFIG_CSH_NOBLOCK 1 + +/*!< help information */ +#define CONFIG_CSH_HELP "" + +/*!< path length 0:const path, <=255:variable path */ +#define CONFIG_CSH_MAXLEN_PATH 128 + +/*!< path segment count */ +#define CONFIG_CSH_MAXSEG_PATH 16 + +/*!< user count */ +#define CONFIG_CSH_MAX_USER 1 + +/*!< max argument count */ +#define CONFIG_CSH_MAX_ARG 8 + +/*!< linebuffer static or on stack */ +#define CONFIG_CSH_LNBUFF_STATIC 1 + +/*!< linebuffer size (valid only if lnbuff on stack) */ +#define CONFIG_CSH_LNBUFF_SIZE 256 + +/*!< multi-thread mode */ +#define CONFIG_CSH_MULTI_THREAD 1 + +/*!< independent signal handler (for multi instances) */ +#define CONFIG_CSH_SIGNAL_HANDLER 0 + +/*!< Ctrl+c/d/q/s/z/\ F1-F12 UE <+120byte> */ +#define CONFIG_CSH_USER_CALLBACK 1 + +/*!< enable macro export symbol table */ +#define CONFIG_CSH_SYMTAB 1 + +#endif diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/inc/ec_config.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/inc/ec_config.h new file mode 100644 index 00000000..7419e55e --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/inc/ec_config.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef EC_CONFIG_H +#define EC_CONFIG_H + +#define CONFIG_EC_PRINTF(...) printf(__VA_ARGS__) + +#ifndef CONFIG_EC_DBG_LEVEL +#define CONFIG_EC_DBG_LEVEL EC_DBG_INFO +#endif + +#ifndef CONFIG_EC_SLAVE_DBG_LEVEL +#define CONFIG_EC_SLAVE_DBG_LEVEL EC_DBG_INFO +#endif + +/* Enable print with color */ +#define CONFIG_EC_PRINTF_COLOR_ENABLE + +#define EC_FAST_CODE_SECTION __attribute__((section(".fast"))) + +#ifndef CONFIG_EC_MAX_NETDEVS +#define CONFIG_EC_MAX_NETDEVS 1 +#endif + +#ifndef CONFIG_EC_NONPERIOD_PRIO +#define CONFIG_EC_NONPERIOD_PRIO 0 +#endif + +#ifndef CONFIG_EC_NONPERIOD_STACKSIZE +#define CONFIG_EC_NONPERIOD_STACKSIZE 2048 +#endif + +#ifndef CONFIG_EC_NONPERIOD_INTERVAL_MS +#define CONFIG_EC_NONPERIOD_INTERVAL_MS 10 +#endif + +#ifndef CONFIG_EC_NONPERIOD_WAITERS +#define CONFIG_EC_NONPERIOD_WAITERS 20 +#endif + +#ifndef CONFIG_EC_SCAN_PRIO +#define CONFIG_EC_SCAN_PRIO 1 +#endif + +#ifndef CONFIG_EC_SCAN_STACKSIZE +#define CONFIG_EC_SCAN_STACKSIZE 2048 +#endif + +#ifndef CONFIG_EC_SCAN_INTERVAL_MS +#define CONFIG_EC_SCAN_INTERVAL_MS 100 +#endif + +#ifndef CONFIG_EC_PER_SM_MAX_PDOS +#define CONFIG_EC_PER_SM_MAX_PDOS 8 +#endif + +#ifndef CONFIG_EC_PER_PDO_MAX_PDO_ENTRIES +#define CONFIG_EC_PER_PDO_MAX_PDO_ENTRIES 8 +#endif + +#define CONFIG_EC_PERF_ENABLE +#define CONFIG_EC_CMD_ENABLE +// #define CONFIG_EC_TIMESTAMP_CUSTOM +// #define CONFIG_EC_PHY_CUSTOM + +#ifndef CONFIG_EC_MAX_PDO_BUFSIZE +#define CONFIG_EC_MAX_PDO_BUFSIZE 2048 +#endif + +#ifndef CONFIG_EC_MAX_ENET_TXBUF_COUNT +#define CONFIG_EC_MAX_ENET_TXBUF_COUNT 10 +#endif + +#ifndef CONFIG_EC_MAX_ENET_RXBUF_COUNT +#define CONFIG_EC_MAX_ENET_RXBUF_COUNT 10 +#endif + +// #define CONFIG_EC_FOE + +#endif \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/inc/shell.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/inc/shell.h new file mode 100644 index 00000000..1bf5ef5d --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/inc/shell.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2022, Egahp + * Copyright (c) 2024, HPMicro + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef SHELL_H +#define SHELL_H + +#include "hpm_uart_drv.h" +#include "csh.h" + +extern int shell_init(UART_Type *uart, bool need_login); +extern void shell_uart_isr(void); +extern void shell_lock(void); +extern void shell_unlock(void); + +#endif diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/main.c b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/main.c new file mode 100644 index 00000000..45ac78fc --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/demo/hpmicro/main.c @@ -0,0 +1,216 @@ +/* + * Copyright (c) 2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* FreeRTOS kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* HPM example includes. */ +#include +#include "board.h" +#include "hpm_clock_drv.h" +#include "hpm_uart_drv.h" +#include "shell.h" +#include "hpm_gptmr_drv.h" +#include "cia402_def.h" +#include "ec_master.h" + +SDK_DECLARE_EXT_ISR_M(BOARD_CONSOLE_UART_IRQ, shell_uart_isr) + +#define task_start_PRIORITY (configMAX_PRIORITIES - 2U) + +#define MOTOR_MODE_CSV_CSP 0 +#define MOTOR_MODE_CSP 1 +#define MOTOR_MODE_CSV 2 + +volatile uint8_t motor_mode = MOTOR_MODE_CSV; + +ec_master_t g_ec_master; + +static void task_start(void *param); + +int main(void) +{ + board_init(); + + if (pdPASS != xTaskCreate(task_start, "task_start", 1024U, NULL, task_start_PRIORITY, NULL)) { + printf("Task start creation failed!\r\n"); + while (1) { + }; + } + + vTaskStartScheduler(); + printf("Unexpected scheduler exit!\r\n"); + while (1) { + }; + + return 0; +} + +static void task_start(void *param) +{ + (void)param; + + printf("Try to initialize the uart\r\n" + " if you are using the console uart as the shell uart\r\n" + " failure to initialize may result in no log\r\n"); + + uart_config_t shell_uart_config = { 0 }; + uart_default_config(BOARD_CONSOLE_UART_BASE, &shell_uart_config); + shell_uart_config.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_UART_CLK_NAME); + shell_uart_config.baudrate = 115200; + + if (status_success != uart_init(BOARD_CONSOLE_UART_BASE, &shell_uart_config)) { + /* uart failed to be initialized */ + printf("Failed to initialize uart\r\n"); + while (1) { + }; + } + + printf("Initialize shell uart successfully\r\n"); + + /* default password is : 12345678 */ + /* shell_init() must be called in-task */ + if (0 != shell_init(BOARD_CONSOLE_UART_BASE, false)) { + /* shell failed to be initialized */ + printf("Failed to initialize shell\r\n"); + while (1) { + }; + } + + printf("Initialize shell successfully\r\n"); + + /* irq must be enabled after shell_init() */ + uart_enable_irq(BOARD_CONSOLE_UART_BASE, uart_intr_rx_data_avail_or_timeout); + intc_m_enable_irq_with_priority(BOARD_CONSOLE_UART_IRQ, 1); + + printf("Enable shell uart interrupt\r\n"); + + ec_master_cmd_init(&g_ec_master); + ec_master_init(&g_ec_master, 0); + + printf("Exit start task\r\n"); + + vTaskDelete(NULL); +} + +CSH_CMD_EXPORT(ethercat, ); + +unsigned char cherryecat_eepromdata[2048]; // EEPROM data buffer, please generate by esi_parse.py + +static ec_pdo_entry_info_t dio_1600[] = { + { 0x6000, 0x00, 0x20 }, +}; + +static ec_pdo_entry_info_t dio_1a00[] = { + { 0x7010, 0x00, 0x20 }, +}; + +static ec_pdo_info_t dio_rxpdos[] = { + { 0x1600, 1, &dio_1600[0] }, +}; + +static ec_pdo_info_t dio_txpdos[] = { + { 0x1a00, 1, &dio_1a00[0] }, +}; + +static ec_sync_info_t dio_syncs[] = { + { 2, EC_DIR_OUTPUT, 1, dio_rxpdos }, + { 3, EC_DIR_INPUT, 1, dio_txpdos }, +}; + +static ec_pdo_entry_info_t coe402_1602[] = { + { 0x6040, 0x00, 0x10 }, + { 0x60ff, 0x00, 0x20 }, + { 0x0000, 0x00, 0x10 }, +}; + +static ec_pdo_entry_info_t coe402_1a02[] = { + { 0x6041, 0x00, 0x10 }, + { 0x6064, 0x00, 0x20 }, + { 0x0000, 0x00, 0x10 }, +}; + +static ec_pdo_info_t cia402_rxpdos[] = { + { 0x1602, 3, &coe402_1602[0] }, +}; + +static ec_pdo_info_t cia402_txpdos[] = { + { 0x1a02, 3, &coe402_1a02[0] }, +}; + +static ec_sync_info_t cia402_syncs[] = { + { 2, EC_DIR_OUTPUT, 1, cia402_rxpdos }, + { 3, EC_DIR_INPUT, 1, cia402_txpdos }, +}; + +int ec_start(int argc, const char **argv) +{ + static ec_slave_config_t slave_cia402_config; + static ec_slave_config_t slave_dio_config; + + if (g_ec_master.slave_count == 0) { + printf("No slave found, please check the connection\r\n"); + return -1; + } + + if (argc < 2) { + printf("Please input: ec_start \r\n"); + return -1; + } + + slave_cia402_config.dc_assign_activate = 0x300; + + slave_cia402_config.dc_sync[0].cycle_time = atoi(argv[1]) * 1000; + slave_cia402_config.dc_sync[0].shift_time = 1000000; + slave_cia402_config.dc_sync[1].cycle_time = 0; + slave_cia402_config.dc_sync[1].shift_time = 0; + + slave_cia402_config.sync = cia402_syncs; + slave_cia402_config.sync_count = sizeof(cia402_syncs) / sizeof(ec_sync_info_t); + + slave_dio_config.dc_assign_activate = 0x300; + + slave_dio_config.dc_sync[0].cycle_time = atoi(argv[1]) * 1000; + slave_dio_config.dc_sync[0].shift_time = 1000000; + slave_dio_config.dc_sync[1].cycle_time = 0; + slave_dio_config.dc_sync[1].shift_time = 0; + slave_dio_config.sync = dio_syncs; + slave_dio_config.sync_count = sizeof(dio_syncs) / sizeof(ec_sync_info_t); + + for (uint32_t i = 0; i < g_ec_master.slave_count; i++) { + if (g_ec_master.slaves[i].sii.vendor_id != 0x0048504D) { // HPMicro + EC_LOG_ERR("Unsupported slave found: vendor_id=0x%08x\n", g_ec_master.slaves[i].sii.vendor_id); + return -1; + } + + switch (g_ec_master.slaves[i].sii.product_code) { + case 0x00000001: // DIO + g_ec_master.slaves[i].config = &slave_dio_config; + break; + case 0x00000002: // FOE + break; + case 0x00000003: // CIA402 + g_ec_master.slaves[i].config = &slave_cia402_config; + break; + + default: + break; + } + } + + ec_master_start(&g_ec_master, atoi(argv[1])); + return 0; +} +CSH_CMD_EXPORT(ec_start, ); + +int ec_stop(int argc, const char **argv) +{ + ec_master_stop(&g_ec_master); + return 0; +} +CSH_CMD_EXPORT(ec_stop, ); \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/.gitignore b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/.gitignore new file mode 100644 index 00000000..c809c12d --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/.gitignore @@ -0,0 +1 @@ +*build \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/Makefile 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b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/assets/ethercat8.png new file mode 100644 index 00000000..f683f9ad Binary files /dev/null and b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/assets/ethercat8.png differ diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/make.bat b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/make.bat new file mode 100644 index 00000000..6247f7e2 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/make.bat @@ -0,0 +1,35 @@ +@ECHO OFF + +pushd %~dp0 + +REM Command file for Sphinx documentation + +if "%SPHINXBUILD%" == "" ( + set SPHINXBUILD=sphinx-build +) +set SOURCEDIR=source +set BUILDDIR=build + +if "%1" == "" goto help + +%SPHINXBUILD% >NUL 2>NUL +if errorlevel 9009 ( + echo. + echo.The 'sphinx-build' command was not found. Make sure you have Sphinx + echo.installed, then set the SPHINXBUILD environment variable to point + echo.to the full path of the 'sphinx-build' executable. Alternatively you + echo.may add the Sphinx directory to PATH. + echo. + echo.If you don't have Sphinx installed, grab it from + echo.http://sphinx-doc.org/ + exit /b 1 +) + +%SPHINXBUILD% -M %1 %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O% +goto end + +:help +%SPHINXBUILD% -M help %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O% + +:end +popd diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/requirements.txt b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/requirements.txt new file mode 100644 index 00000000..03cfbf10 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/requirements.txt @@ -0,0 +1,9 @@ +# markdown suport +recommonmark +# markdown table suport +sphinx-markdown-tables + +# theme default rtd + +# crate-docs-theme +sphinx-rtd-theme \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/api.rst b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/api.rst new file mode 100644 index 00000000..6d549339 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/api.rst @@ -0,0 +1,2 @@ +API 手册 +=========================== diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/conf.py b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/conf.py new file mode 100644 index 00000000..361d9daa --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/conf.py @@ -0,0 +1,37 @@ +# Configuration file for the Sphinx documentation builder. + +# -- Project information + +project = 'CherryEC' +copyright = '2025 ~ 2026, sakumisu' +author = 'sakumisu' + +release = '0.1.0' +version = '0.1.0' + +# -- General configuration + +extensions = [ + 'sphinx.ext.duration', + 'sphinx.ext.doctest', + 'sphinx.ext.autodoc', + 'sphinx.ext.autosummary', + 'sphinx.ext.intersphinx', + 'recommonmark', + 'sphinx_markdown_tables' +] + +intersphinx_mapping = { +# 'python': ('https://docs.python.org/3/', None), +# 'sphinx': ('https://www.sphinx-doc.org/en/master/', None), +} +intersphinx_disabled_domains = ['std'] + +templates_path = ['_templates'] + +# -- Options for HTML output + +html_theme = 'sphinx_rtd_theme' + +# -- Options for EPUB output +epub_show_urls = 'footnote' diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/ethercat.rst b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/ethercat.rst new file mode 100644 index 00000000..303cecea --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/ethercat.rst @@ -0,0 +1,32 @@ +EtherCAT 概念 +=========================== + +EtherCAT 官方文档汇总 +----------------------------- + +EtherCAT 数据格式 +-------------------- + +EtherCAT 寻址模式 +-------------------- + +EtherCAT 状态机 +-------------------- + +EtherCAT 同步 +-------------------- + +EtherCAT SII EEPROM +----------------------- + +EtherCAT SM & FMMU +----------------------- + +EtherCAT SDO & PDO +----------------------- + +EtherCAT COE +----------------------- + +EtherCAT FOE +----------------------- \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/index.rst b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/index.rst new file mode 100644 index 00000000..5eb0a418 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/index.rst @@ -0,0 +1,17 @@ +.. CherryEC 使用指南 documentation master file, created by + sphinx-quickstart on Thu Nov 21 10:50:33 2019. + You can adapt this file completely to your liking, but it should at least + contain the root `toctree` directive. + +CherryEC 使用指南 +====================================================== + +CherryEC 是一个小而美的、高实时性、低抖动 EtherCAT 主机协议栈，专为跑在 RTOS 下的 MCU 设计。 + +.. toctree:: + :maxdepth: 1 + + quickstart + api + ethercat + version \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/quickstart.rst b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/quickstart.rst new file mode 100644 index 00000000..34e204d5 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/quickstart.rst @@ -0,0 +1,9 @@ +快速入门 +=========================== + + +HPMicro Boards +----------------------------- + +RT-Thread RuiQing +----------------------------- \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/version.rst b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/version.rst new file mode 100644 index 00000000..ebccbc07 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/docs/source/version.rst @@ -0,0 +1,2 @@ +版本说明 +=========================== diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_cmd.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_cmd.h new file mode 100644 index 00000000..1513ad37 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_cmd.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef EC_CMD_H +#define EC_CMD_H + +typedef struct ec_master ec_master_t; + +void ec_master_cmd_init(ec_master_t *master); +int ethercat(int argc, const char **argv); + +#endif diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_coe.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_coe.h new file mode 100644 index 00000000..66334039 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_coe.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef EC_COE_H +#define EC_COE_H + +int ec_coe_download(ec_master_t *master, + uint16_t slave_index, + ec_datagram_t *datagram, + uint16_t index, + uint8_t subindex, + const void *buf, + uint32_t size, + bool complete_access); + +int ec_coe_upload(ec_master_t *master, + uint16_t slave_index, + ec_datagram_t *datagram, + uint16_t index, + uint8_t subindex, + const void *buf, + uint32_t maxsize, + uint32_t *size, + bool complete_access); +#endif \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_common.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_common.h new file mode 100644 index 00000000..a5ccaf1e --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_common.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef EC_COMMON_H +#define EC_COMMON_H + +void *ec_memcpy(void *s1, const void *s2, size_t n); +void ec_memset(void *s, int c, size_t n); +const char *ec_state_string(uint8_t states, uint8_t multi); +const char *ec_mbox_protocol_string(uint8_t prot); +const char *ec_alstatus_string(uint16_t errorcode); +const char *ec_mbox_error_string(uint16_t errorcode); +const char *ec_sdo_abort_string(uint32_t errorcode); +const char *foe_errorcode_string(uint16_t errorcode); + +#endif \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_datagram.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_datagram.h new file mode 100644 index 00000000..d99719e6 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_datagram.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef EC_DATAGRAM_H +#define EC_DATAGRAM_H + +/** EtherCAT datagram type. + */ +typedef enum { + EC_DATAGRAM_NONE = 0x00, /**< Dummy. */ + EC_DATAGRAM_APRD = 0x01, /**< Auto Increment Physical Read. */ + EC_DATAGRAM_APWR = 0x02, /**< Auto Increment Physical Write. */ + EC_DATAGRAM_APRW = 0x03, /**< Auto Increment Physical ReadWrite. */ + EC_DATAGRAM_FPRD = 0x04, /**< Configured Address Physical Read. */ + EC_DATAGRAM_FPWR = 0x05, /**< Configured Address Physical Write. */ + EC_DATAGRAM_FPRW = 0x06, /**< Configured Address Physical ReadWrite. */ + EC_DATAGRAM_BRD = 0x07, /**< Broadcast Read. */ + EC_DATAGRAM_BWR = 0x08, /**< Broadcast Write. */ + EC_DATAGRAM_BRW = 0x09, /**< Broadcast ReadWrite. */ + EC_DATAGRAM_LRD = 0x0A, /**< Logical Read. */ + EC_DATAGRAM_LWR = 0x0B, /**< Logical Write. */ + EC_DATAGRAM_LRW = 0x0C, /**< Logical ReadWrite. */ + EC_DATAGRAM_ARMW = 0x0D, /**< Auto Increment Physical Read Multiple + Write. */ + EC_DATAGRAM_FRMW = 0x0E, /**< Configured Address Physical Read Multiple + Write. */ +} ec_datagram_type_t; + +/** EtherCAT datagram state. + */ +typedef enum { + EC_DATAGRAM_INIT, /**< Initial state of a new datagram. */ + EC_DATAGRAM_QUEUED, /**< Queued for sending. */ + EC_DATAGRAM_SENT, /**< Sent (still in the queue). */ + EC_DATAGRAM_RECEIVED, /**< Received (dequeued). */ + EC_DATAGRAM_TIMED_OUT, /**< Timed out (dequeued). */ + EC_DATAGRAM_ERROR /**< Error while sending/receiving (dequeued). */ +} ec_datagram_state_t; + +/** EtherCAT datagram. + */ +typedef struct { + ec_dlist_t queue; + ec_dlist_t ext_queue; + ec_dlist_t sent; + ec_netdev_index_t netdev_idx; /**< Netdev via which the datagram shall be / was sent. */ + ec_datagram_type_t type; /**< Datagram type (APRD, BWR, etc.). */ + bool static_alloc; /**< True, if \a data is statically allocated. */ + uint8_t address[EC_ADDR_LEN]; /**< Recipient address. */ + uint8_t *data; /**< Datagram payload. */ + size_t mem_size; /**< Datagram \a data memory size. */ + size_t data_size; /**< Size of the data in \a data. */ + uint8_t index; /**< Index (set by master). */ + uint16_t working_counter; /**< Working counter. */ + ec_datagram_state_t state; /**< State. */ + uint32_t lrw_read_offset; /**< Read Offset in LRW datagram. */ + uint32_t lrw_read_size; /**< Read Size in LRW datagram. */ + uint64_t jiffies_sent; /**< Jiffies, when the datagram was sent. */ + uint64_t jiffies_received; /**< Jiffies, when the datagram was received. */ + char name[EC_DATAGRAM_NAME_SIZE]; /**< Description of the datagram. */ + bool waiter; /**< True, if someone is waiting for the datagram. */ + ec_osal_sem_t wait; /**< Semaphore for waiting. */ +} ec_datagram_t; + +void ec_datagram_init(ec_datagram_t *datagram, size_t mem_size); +void ec_datagram_init_static(ec_datagram_t *datagram, uint8_t *data, size_t mem_size); +void ec_datagram_clear(ec_datagram_t *datagram); +void ec_datagram_unqueue(ec_datagram_t *datagram); +void ec_datagram_zero(ec_datagram_t *datagram); +void ec_datagram_fill(ec_datagram_t *datagram, + ec_datagram_type_t type, + uint16_t adp, + uint16_t ado, + uint16_t size); +void ec_datagram_aprd(ec_datagram_t *datagram, uint16_t autoinc_address, uint16_t mem_address, size_t data_size); +void ec_datagram_apwr(ec_datagram_t *datagram, uint16_t autoinc_address, uint16_t mem_address, size_t data_size); +void ec_datagram_aprw(ec_datagram_t *datagram, uint16_t autoinc_address, uint16_t mem_address, size_t data_size); +void ec_datagram_armw(ec_datagram_t *datagram, uint16_t autoinc_address, uint16_t mem_address, size_t data_size); +void ec_datagram_fprd(ec_datagram_t *datagram, uint16_t configured_address, uint16_t mem_address, size_t data_size); +void ec_datagram_fpwr(ec_datagram_t *datagram, uint16_t configured_address, uint16_t mem_address, size_t data_size); +void ec_datagram_fprw(ec_datagram_t *datagram, uint16_t configured_address, uint16_t mem_address, size_t data_size); +void ec_datagram_frmw(ec_datagram_t *datagram, uint16_t configured_address, uint16_t mem_address, size_t data_size); +void ec_datagram_brd(ec_datagram_t *datagram, uint16_t mem_address, size_t data_size); +void ec_datagram_bwr(ec_datagram_t *datagram, uint16_t mem_address, size_t data_size); +void ec_datagram_brw(ec_datagram_t *datagram, uint16_t mem_address, size_t data_size); +void ec_datagram_lrd(ec_datagram_t *datagram, uint32_t offset, size_t data_size); +void ec_datagram_lwr(ec_datagram_t *datagram, uint32_t offset, size_t data_size); +void ec_datagram_lrw(ec_datagram_t *datagram, uint32_t offset, size_t data_size); +const char *ec_datagram_type_string(const ec_datagram_t *datagram); + +#endif \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_def.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_def.h new file mode 100644 index 00000000..f64ecb1b --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_def.h @@ -0,0 +1,541 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef EC_DEF_H +#define EC_DEF_H + +/* + * IEEE 802.3 Ethernet magic constants. The frame sizes omit the preamble + * and FCS/CRC (frame check sequence). + */ +#define ETH_ALEN 6 /* Octets in one ethernet addr */ +#define ETH_TLEN 2 /* Octets in ethernet type field */ +#define ETH_HLEN 14 /* Total octets in header. */ +#define ETH_ZLEN 60 /* Min. octets in frame sans FCS */ +#define ETH_DATA_LEN 1500 /* Max. octets in payload */ +#define ETH_FRAME_LEN 1514 /* Max. octets in frame sans FCS */ +#define ETH_FCS_LEN 4 /* Octets in the FCS */ + +#define ETH_MIN_MTU 68 /* Min IPv4 MTU per RFC791 */ +#define ETH_MAX_MTU 0xFFFFU /* 65535, same as IP_MAX_MTU */ + +/** Datagram timeout in microseconds. */ +#define EC_IO_TIMEOUT 500 + +/** Time to send a byte in nanoseconds. + * + * t_ns = 1 / (100 MBit/s / 8 bit/byte) = 80 ns/byte + */ +#define EC_BYTE_TRANSMISSION_TIME_NS 80 + +/** Minimum size of a buffer used with ec_state_string(). */ +#define EC_STATE_STRING_SIZE 32 + +/** Maximum SII size in words, to avoid infinite reading. */ +#define EC_MAX_SII_SIZE 4096 + +/** Number of statistic rate intervals to maintain. */ +#define EC_RATE_COUNT 3 + +/***************************************************************************** + * EtherCAT protocol + ****************************************************************************/ + +/** Size of an EtherCAT frame header. */ +#define EC_FRAME_HEADER_SIZE 2 + +/** Size of an EtherCAT datagram header. */ +#define EC_DATAGRAM_HEADER_SIZE 10 + +/** Size of an EtherCAT datagram workcounter. */ +#define EC_DATAGRAM_WC_SIZE 2 + +/** Size of the EtherCAT address field. */ +#define EC_ADDR_LEN 4 + +/** Resulting maximum data size of a single datagram in a frame. */ +#define EC_MAX_DATA_SIZE (ETH_DATA_LEN - EC_FRAME_HEADER_SIZE - EC_DATAGRAM_HEADER_SIZE - EC_DATAGRAM_WC_SIZE) + +/** Mailbox header size. */ +#define EC_MBOX_HEADER_SIZE 6 + +/** Word offset of first SII category. */ +#define EC_FIRST_SII_CATEGORY_OFFSET 0x40 + +/** Size of a sync manager configuration page. */ +#define EC_SYNC_PAGE_SIZE 8 + +/** Maximum number of FMMUs per slave. */ +#define EC_MAX_FMMUS 16 + +/** Size of an FMMU configuration page. */ +#define EC_FMMU_PAGE_SIZE 16 + +/** Number of DC sync signals. */ +#define EC_SYNC_SIGNAL_COUNT 2 + +/** Size of the datagram decription string. + * + * This is also used as the maximum lenth of EoE device names. + **/ +#define EC_DATAGRAM_NAME_SIZE 20 + +/** Maximum hostname size. + * + * Used inside the EoE set IP parameter request. + */ +#define EC_MAX_HOSTNAME_SIZE 32 + +/** Maximum number of sync managers per slave. + */ +#define EC_MAX_SYNC_MANAGERS 16 + +/** Maximum string length. + * + * Used in ec_slave_info_t. + */ +#define EC_MAX_STRING_LENGTH 64 + +/** Maximum number of slave ports. */ +#define EC_MAX_PORTS 4 + +/** Slave state mask. + * + * Apply this mask to a slave state byte to get the slave state without + * the error flag. + */ +#define EC_SLAVE_STATE_MASK 0x0F + +/** State of an EtherCAT slave. + */ +typedef enum { + EC_SLAVE_STATE_UNKNOWN = 0x00, + /**< unknown state */ + EC_SLAVE_STATE_INIT = 0x01, + /**< INIT state (no mailbox communication, no IO) */ + EC_SLAVE_STATE_PREOP = 0x02, + /**< PREOP state (mailbox communication, no IO) */ + EC_SLAVE_STATE_BOOT = 0x03, + /**< Bootstrap state (mailbox communication, firmware update) */ + EC_SLAVE_STATE_SAFEOP = 0x04, + /**< SAFEOP (mailbox communication and input update) */ + EC_SLAVE_STATE_OP = 0x08, + /**< OP (mailbox communication and input/output update) */ + EC_SLAVE_STATE_ACK_ERR = 0x10 + /**< Acknowledge/Error bit (no actual state) */ +} ec_slave_state_t; + +/** Slave information interface CANopen over EtherCAT details flags. + */ +typedef struct { + uint8_t enable_sdo : 1; /**< Enable SDO access. */ + uint8_t enable_sdo_info : 1; /**< SDO information service available. */ + uint8_t enable_pdo_assign : 1; /**< PDO mapping configurable. */ + uint8_t enable_pdo_configuration : 1; /**< PDO configuration possible. */ + uint8_t enable_upload_at_startup : 1; /**< ?. */ + uint8_t enable_sdo_complete_access : 1; /**< Complete access possible. */ + uint8_t : 2; /**< Reserved bits. */ +} ec_sii_coe_details_t; + +/** Slave information interface general flags. + */ +typedef struct { + uint8_t enable_safeop : 1; /**< ?. */ + uint8_t enable_not_lrw : 1; /**< Slave does not support LRW. */ + uint8_t : 6; /**< Reserved bits. */ +} ec_sii_general_flags_t; + +/** EtherCAT slave distributed clocks range. + */ +typedef enum { + EC_DC_32, /**< 32 bit. */ + EC_DC_64 /*< 64 bit for system time, system time offset and + port 0 receive time. */ +} ec_slave_dc_range_t; + +/** EtherCAT slave sync signal configuration. + */ +typedef struct { + uint32_t cycle_time; /**< Cycle time [ns]. */ + int32_t shift_time; /**< Shift time [ns]. */ +} ec_sync_signal_t; + +/** Master netdev. + */ +typedef enum { + EC_NETDEV_MAIN, /**< Main netdev. */ + EC_NETDEV_BACKUP /**< Backup netdev */ +} ec_netdev_index_t; + +typedef struct ec_alstatus { + uint16_t alstatus; + uint16_t unused; + uint16_t alstatuscode; +} ec_alstatus_t; + +/* AL Status Codes */ +#define EC_ALSTATUSCODE_NOERROR 0x0000 /**< No error*/ +#define EC_ALSTATUSCODE_UNSPECIFIEDERROR 0x0001 /**< Unspecified error*/ +#define EC_ALSTATUSCODE_NOMEMORY 0x0002 /**< No Memory*/ +#define EC_ALSTATUSCODE_INVALID_REVISION 0x0004 /**< Output/Input mapping is not valid for this hardware or software revision (0x1018:03)*/ +#define EC_ALSTATUSCODE_FW_SII_NOT_MATCH 0x0006 /**< Firmware and EEPROM do not match. Slave needs BOOT-INIT transition*/ +#define EC_ALSTATUSCODE_FW_UPDATE_FAILED 0x0007 /**< Firmware update not successful. Old firmware still running*/ +#define EC_ALSTATUSCODE_INVALIDALCONTROL 0x0011 /**< Invalid requested state change*/ +#define EC_ALSTATUSCODE_UNKNOWNALCONTROL 0x0012 /**< Unknown requested state*/ +#define EC_ALSTATUSCODE_BOOTNOTSUPP 0x0013 /**< Bootstrap not supported*/ +#define EC_ALSTATUSCODE_NOVALIDFIRMWARE 0x0014 /**< No valid firmware*/ +#define EC_ALSTATUSCODE_INVALIDMBXCFGINBOOT 0x0015 /**< Invalid mailbox configuration (BOOT state)*/ +#define EC_ALSTATUSCODE_INVALIDMBXCFGINPREOP 0x0016 /**< Invalid mailbox configuration (PreOP state)*/ +#define EC_ALSTATUSCODE_INVALIDSMCFG 0x0017 /**< Invalid sync manager configuration*/ +#define EC_ALSTATUSCODE_NOVALIDINPUTS 0x0018 /**< No valid inputs available*/ +#define EC_ALSTATUSCODE_NOVALIDOUTPUTS 0x0019 /**< No valid outputs*/ +#define EC_ALSTATUSCODE_SYNCERROR 0x001A /**< Synchronization error*/ +#define EC_ALSTATUSCODE_SMWATCHDOG 0x001B /**< Sync manager watchdog*/ +#define EC_ALSTATUSCODE_SYNCTYPESNOTCOMPATIBLE 0x001C /**< Invalid Sync Manager Types*/ +#define EC_ALSTATUSCODE_INVALIDSMOUTCFG 0x001D /**< Invalid Output Configuration*/ +#define EC_ALSTATUSCODE_INVALIDSMINCFG 0x001E /**< Invalid Input Configuration*/ +#define EC_ALSTATUSCODE_INVALIDWDCFG 0x001F /**< Invalid Watchdog Configuration*/ +#define EC_ALSTATUSCODE_WAITFORCOLDSTART 0x0020 /**< Slave needs cold start*/ +#define EC_ALSTATUSCODE_WAITFORINIT 0x0021 /**< Slave needs INIT*/ +#define EC_ALSTATUSCODE_WAITFORPREOP 0x0022 /**< Slave needs PREOP*/ +#define EC_ALSTATUSCODE_WAITFORSAFEOP 0x0023 /**< Slave needs SAFEOP*/ +#define EC_ALSTATUSCODE_INVALIDINPUTMAPPING 0x0024 /**< Invalid Input Mapping*/ +#define EC_ALSTATUSCODE_INVALIDOUTPUTMAPPING 0x0025 /**< Invalid Output Mapping*/ +#define EC_ALSTATUSCODE_INCONSISTENTSETTINGS 0x0026 /**< Inconsistent Settings*/ +#define EC_ALSTATUSCODE_FREERUNNOTSUPPORTED 0x0027 /**< FreeRun not supported*/ +#define EC_ALSTATUSCODE_SYNCHRONNOTSUPPORTED 0x0028 /**< SyncMode not supported*/ +#define EC_ALSTATUSCODE_FREERUNNEEDS3BUFFERMODE 0x0029 /**< FreeRun needs 3Buffer Mode*/ +#define EC_ALSTATUSCODE_BACKGROUNDWATCHDOG 0x002A /**< Background Watchdog*/ +#define EC_ALSTATUSCODE_NOVALIDINPUTSANDOUTPUTS 0x002B /**< No Valid Inputs and Outputs*/ +#define EC_ALSTATUSCODE_FATALSYNCERROR 0x002C /**< Fatal Sync Error*/ +#define EC_ALSTATUSCODE_NOSYNCERROR 0x002D /**< No Sync Error*/ +#define EC_ALSTATUSCODE_CYCLETIMETOOSMALL 0x002E /**< EtherCAT cycle time smaller Minimum Cycle Time supported by slave*/ +#define EC_ALSTATUSCODE_DCINVALIDSYNCCFG 0x0030 /**< Invalid DC SYNCH Configuration*/ +#define EC_ALSTATUSCODE_DCINVALIDLATCHCFG 0x0031 /**< Invalid DC Latch Configuration*/ +#define EC_ALSTATUSCODE_DCPLLSYNCERROR 0x0032 /**< PLL Error*/ +#define EC_ALSTATUSCODE_DCSYNCIOERROR 0x0033 /**< DC Sync IO Error*/ +#define EC_ALSTATUSCODE_DCSYNCMISSEDERROR 0x0034 /**< DC Sync Timeout Error*/ +#define EC_ALSTATUSCODE_DCINVALIDSYNCCYCLETIME 0x0035 /**< DC Invalid Sync Cycle Time*/ +#define EC_ALSTATUSCODE_DCSYNC0CYCLETIME 0x0036 /**< DC Sync0 Cycle Time*/ +#define EC_ALSTATUSCODE_DCSYNC1CYCLETIME 0x0037 /**< DC Sync1 Cycle Time*/ +#define EC_ALSTATUSCODE_MBX_AOE 0x0041 /**< MBX_AOE*/ +#define EC_ALSTATUSCODE_MBX_EOE 0x0042 /**< MBX_EOE*/ +#define EC_ALSTATUSCODE_MBX_COE 0x0043 /**< MBX_COE*/ +#define EC_ALSTATUSCODE_MBX_FOE 0x0044 /**< MBX_FOE*/ +#define EC_ALSTATUSCODE_MBX_SOE 0x0045 /**< MBX_SOE*/ +#define EC_ALSTATUSCODE_MBX_VOE 0x004F /**< MBX_VOE*/ +#define EC_ALSTATUSCODE_EE_NOACCESS 0x0050 /**< EEPROM no access*/ +#define EC_ALSTATUSCODE_EE_ERROR 0x0051 /**< EEPROM Error*/ +#define EC_ALSTATUSCODE_EXT_HARDWARE_NOT_READY 0x0052 /**< External hardware not ready. This AL Status Code should be used if the EtherCAT-Slave refused the state transition due to an external connection to another device or signal is missing*/ +#define EC_ALSTATUSCODE_DEVICE_IDENT_VALUE_UPDATED 0x0061 /**< In legacy identification mode (dip switch mapped to register 0x12) this error is returned if the EEPROM ID value does not match to dipswitch value*/ +#define EC_ALSTATUSCODE_MODULE_ID_LIST_NOT_MATCH 0x0070 /**< Detected Module Ident List (0xF030) and Configured Module Ident List (0xF050) does not match*/ +#define EC_ALSTATUSCODE_SUPPLY_VOLTAGE_TOO_LOW 0x0080 /**< The slave supply voltage is too low*/ +#define EC_ALSTATUSCODE_SUPPLY_VOLTAGE_TOO_HIGH 0x0081 /**< The slave supply voltage is too high*/ +#define EC_ALSTATUSCODE_TEMPERATURE_TOO_LOW 0x0082 /**< The slave temperature is too low*/ +#define EC_ALSTATUSCODE_TEMPERATURE_TOO_HIGH 0x0083 /**< The slave temperature is too high*/ + +#define EC_SII_ADDRESS_MANUF (0x0008) +#define EC_SII_ADDRESS_PRODUCTCODE (0x000a) +#define EC_SII_ADDRESS_REVISION (0x000c) +#define EC_SII_ADDRESS_SN (0x000E) +#define EC_SII_ADDRESS_BOOTRXMBX (0x0014) +#define EC_SII_ADDRESS_BOOTTXMBX (0x0016) +#define EC_SII_ADDRESS_MBXSIZE (0x0019) +#define EC_SII_ADDRESS_TXMBXADR (0x001a) +#define EC_SII_ADDRESS_RXMBXADR (0x0018) +#define EC_SII_ADDRESS_MBXPROTO (0x001c) +#define EC_SII_ADDRESS_ADDITIONAL_INFO (0x0040) + +#define EC_SII_TYPE_NOP 0x0000 +#define EC_SII_TYPE_STRINGS 0x000A +#define EC_SII_TYPE_DATATYPES 0x0014 +#define EC_SII_TYPE_GENERAL 0x001E +#define EC_SII_TYPE_FMMU 0x0028 +#define EC_SII_TYPE_SM 0x0029 +#define EC_SII_TYPE_FMMUX 0x002A +#define EC_SII_TYPE_SYNCUNIT 0x002B +#define EC_SII_TYPE_TXPDO 0x0032 +#define EC_SII_TYPE_RXPDO 0x0033 +#define EC_SII_TYPE_DC 0x003C +#define EC_SII_TYPE_END 0xFFFF + +#define EC_SII_FMMU_NONE 0x0000 +#define EC_SII_FMMU_READ 0x0001 +#define EC_SII_FMMU_WRITE 0x0002 +#define EC_SII_FMMU_SM_STATUS 0x0003 + +#define EC_SII_SM_UNKNOWN 0x0000 +#define EC_SII_SM_MBX_OUT 0x0001 +#define EC_SII_SM_MBX_IN 0x0002 +#define EC_SII_SM_PROCESS_DATA_OUTPUT 0x0003 +#define EC_SII_SM_PROCESS_DATA_INPUT 0x0004 + +typedef struct __PACKED ec_sii_base { + uint16_t pdi_control; + uint16_t pdi_config; + uint16_t sync_impulselen; + uint16_t pdi_config2; + uint16_t aliasaddr; /**< Configured station alias. */ + uint8_t reserved[4]; + uint16_t checksum; + uint32_t vendor_id; /**< Vendor ID. */ + uint32_t product_code; /**< Vendor-specific product code. */ + uint32_t revision_number; /**< Revision number. */ + uint32_t serial_number; /**< Serial number. */ + uint8_t reserved2[8]; + uint16_t boot_rx_mailbox_offset; /**< Bootstrap receive mailbox address. */ + uint16_t boot_rx_mailbox_size; /**< Bootstrap receive mailbox size. */ + uint16_t boot_tx_mailbox_offset; /**< Bootstrap transmit mailbox address. */ + uint16_t boot_tx_mailbox_size; /**< Bootstrap transmit mailbox size. */ + uint16_t std_rx_mailbox_offset; /**< Standard receive mailbox address. */ + uint16_t std_rx_mailbox_size; /**< Standard receive mailbox size. */ + uint16_t std_tx_mailbox_offset; /**< Standard transmit mailbox address. */ + uint16_t std_tx_mailbox_size; /**< Standard transmit mailbox size. */ + uint16_t mailbox_protocols; /**< Supported mailbox protocols. */ + uint8_t reserved3[66]; + uint16_t size; + uint16_t version; +} ec_sii_base_t; + +typedef struct __PACKED ec_sii_general { + uint8_t groupidx; + uint8_t imgidx; + uint8_t orderidx; + uint8_t nameidx; + uint8_t reserved1; + ec_sii_coe_details_t coe_details; + uint8_t foe_details; + uint8_t eoe_details; + uint8_t soe_channels; + uint8_t ds402_channels; + uint8_t sysmanclass; + ec_sii_general_flags_t flags; + int16_t current_on_ebus; + uint8_t reserved2; + uint8_t reserved3; + uint16_t phy_port; + uint16_t phy_memaddress; + uint8_t pad[12]; +} ec_sii_general_t; + +typedef struct __PACKED ec_sii_sm { + uint16_t physical_start_address; + uint16_t length; + uint8_t control; + uint8_t status; + uint8_t active; + uint8_t type; +} ec_sii_sm_t; + +typedef struct __PACKED ec_sii_pdo_entry { + uint16_t index; + uint8_t subindex; + uint8_t nameidx; + uint8_t data_type; + uint8_t bitlen; + uint16_t flags; +} ec_sii_pdo_entry_t; + +typedef struct __PACKED ec_sii_pdo_mapping { + uint16_t index; /* txpdo: 1a00~1bff, rxpdo: 1600~17ff */ + uint8_t nentry; + uint8_t sm_idx; + uint8_t synchronization; + uint8_t nameidx; + uint16_t flags; + ec_sii_pdo_entry_t entry[]; +} ec_sii_pdo_mapping_t; + +typedef struct __PACKED ec_sm_reg { + uint16_t physical_start_address; + uint16_t length; + uint8_t control; + uint8_t status; + uint8_t active; + uint8_t pdi_control; +} ec_sm_reg_t; + +typedef struct __PACKED ec_fmmu_reg { + uint32_t logical_start_address; + uint16_t length; + uint8_t logical_start_bit; + uint8_t logical_stop_bit; + uint16_t physical_start_address; + uint8_t physical_start_bit; + uint8_t type; + uint8_t active; + uint8_t reserved[3]; +} ec_fmmu_reg_t; + +/** + * \brief SmAssignObjects SyncManager Assignment Objects + * SyncManager 2 : 0x1C12
+ * SyncManager 3 : 0x1C13
+ */ +typedef struct __PACKED ec_pdo_assign_t { + uint16_t count; /**< PDO mapping count. */ + uint16_t entry[CONFIG_EC_PER_SM_MAX_PDOS]; +} ec_pdo_assign_t; + +typedef struct __PACKED ec_pdo_mapping_t { + uint16_t count; /**< PDO entry count. */ + uint32_t entry[CONFIG_EC_PER_PDO_MAX_PDO_ENTRIES]; +} ec_pdo_mapping_t; + +typedef struct __PACKED ec_mailbox_header { + uint16_t length; + uint16_t address; + uint8_t channel : 6; + uint8_t priority : 2; + uint8_t type : 4; + uint8_t counter : 3; + uint8_t reserved : 1; +} ec_mailbox_header_t; + +/** Size of the mailbox header. + */ +#define EC_MBOX_HEADER_SIZE 6 + +#define EC_MBXPROT_AOE 0x0001 +#define EC_MBXPROT_EOE 0x0002 +#define EC_MBXPROT_COE 0x0004 +#define EC_MBXPROT_FOE 0x0008 +#define EC_MBXPROT_SOE 0x0010 +#define EC_MBXPROT_VOE 0x0020 + +/** Mailbox types. + * + * These are used in the 'Type' field of the mailbox header. + */ +enum { + EC_MBOX_TYPE_EOE = 0x02, + EC_MBOX_TYPE_COE = 0x03, + EC_MBOX_TYPE_FOE = 0x04, + EC_MBOX_TYPE_SOE = 0x05, + EC_MBOX_TYPE_VOE = 0x0f, +}; + +#define EC_SM_INDEX_MBX_WRITE 0x0000 +#define EC_SM_INDEX_MBX_READ 0x0001 +#define EC_SM_INDEX_PROCESS_DATA_OUTPUT 0x0002 +#define EC_SM_INDEX_PROCESS_DATA_INPUT 0x0003 + +typedef struct __PACKED ec_coe_header { + uint16_t number : 9; + uint16_t reserved : 3; + uint16_t service : 4; +} ec_coe_header_t; + +typedef struct __PACKED ec_sdo_header_common { + uint8_t size_indicator : 1; + uint8_t transfertype : 1; // expedited transfer + uint8_t data_set_size : 2; + uint8_t complete_access : 1; + uint8_t command : 3; +} ec_sdo_header_common_t; + +typedef struct __PACKED ec_sdo_header_segment { + uint8_t more_follows : 1; + uint8_t segdata_size : 3; + uint8_t toggle : 1; + uint8_t command : 3; +} ec_sdo_header_segment_t; + +typedef struct __PACKED ec_sdo_header { + union { + uint8_t byte; + ec_sdo_header_common_t common; + ec_sdo_header_segment_t segment; + }; + uint16_t index; + uint8_t subindex; +} ec_sdo_header_t; + +#define EC_COE_SERVICE_EMERGENCY 0x01 +#define EC_COE_SERVICE_SDO_REQUEST 0x02 +#define EC_COE_SERVICE_SDO_RESPONSE 0x03 +#define EC_COE_SERVICE_TXPDO 0x04 +#define EC_COE_SERVICE_RXPDO 0x05 +#define EC_COE_SERVICE_TXPDO_REMOTE_REQUSET 0x06 +#define EC_COE_SERVICE_RXPDO_REMOTE_REQUEST 0x07 +#define EC_COE_SERVICE_SDOINFO 0x08 + +#define EC_COE_REQUEST_SEGMENT_DOWNLOAD 0x00 +#define EC_COE_REQUEST_DOWNLOAD 0x01 +#define EC_COE_REQUEST_UPLOAD 0x02 +#define EC_COE_REQUEST_SEGMENT_UPLOAD 0x03 +#define EC_COE_REQUEST_ABORT 0x04 + +#define EC_COE_RESPONSE_SEGMENT_UPLOAD 0x00 +#define EC_COE_RESPONSE_SEGMENT_DOWNLOAD 0x01 +#define EC_COE_RESPONSE_UPLOAD 0x02 +#define EC_COE_RESPONSE_DOWNLOAD 0x03 + +typedef struct __PACKED { + uint16_t opcode; + union { + uint32_t password; + uint32_t packet_number; + uint32_t error_code; + }; +} ec_foe_header_t; + +#define EC_FOE_OPCODE_READ 0x0001 +#define EC_FOE_OPCODE_WRITE 0x0002 +#define EC_FOE_OPCODE_DATA 0x0003 +#define EC_FOE_OPCODE_ACK 0x0004 +#define EC_FOE_OPCODE_ERROR 0x0005 +#define EC_FOE_OPCODE_BUSY 0x0006 + +#define EC_FOE_ERRCODE_NOTDEFINED 0x8000 /**< \brief Not defined*/ +#define EC_FOE_ERRCODE_NOTFOUND 0x8001 /**< \brief The file requested by an FoE upload service could not be found on the server*/ +#define EC_FOE_ERRCODE_ACCESS 0x8002 /**< \brief Read or write access to this file not allowed (e.g. due to local control).*/ +#define EC_FOE_ERRCODE_DISKFULL 0x8003 /**< \brief Disk to store file is full or memory allocation exceeded*/ +#define EC_FOE_ERRCODE_ILLEGAL 0x8004 /**< \brief Illegal FoE operation, e.g. service identifier invalid*/ +#define EC_FOE_ERRCODE_PACKENO 0x8005 /**< \brief FoE packet number invalid*/ +#define EC_FOE_ERRCODE_EXISTS 0x8006 /**< \brief The file which is requested to be downloaded does already exist*/ +#define EC_FOE_ERRCODE_NOUSER 0x8007 /**< \brief No User*/ +#define EC_FOE_ERRCODE_BOOTSTRAPONLY 0x8008 /**< \brief FoE only supported in Bootstrap*/ +#define EC_FOE_ERRCODE_NOTINBOOTSTRAP 0x8009 /**< \brief This file may not be accessed in BOOTSTRAP state*/ +#define EC_FOE_ERRCODE_NORIGHTS 0x800A /**< \brief Password invalid*/ +#define EC_FOE_ERRCODE_PROGERROR 0x800B /**< \brief Generic programming error. Should only be returned if error reason cannot be distinguished*/ +#define EC_FOE_ERRCODE_INVALID_CHECKSUM 0x800C /**< \brief checksum included in the file is invalid*/ +#define EC_FOE_ERRCODE_INVALID_FIRMWARE 0x800D /**< \brief The hardware does not support the downloaded firmware*/ +#define EC_FOE_ERRCODE_NO_FILE 0x800F /**< \brief Do not use (identical with 0x8001)*/ +#define EC_FOE_ERRCODE_NO_FILE_HEADER 0x8010 /**< \brief Missing file header of error in file header*/ +#define EC_FOE_ERRCODE_FLASH_ERROR 0x8011 /**< \brief Flash cannot be accessed*/ + +typedef enum { + EC_DIR_OUTPUT, /**< Values written by the master. */ + EC_DIR_INPUT, /**< Values read by the master. */ +} ec_direction_t; + +typedef enum { + EC_WD_DEFAULT, /**< Use the default setting of the sync manager. */ + EC_WD_ENABLE, /**< Enable the watchdog. */ + EC_WD_DISABLE, /**< Disable the watchdog. */ +} ec_watchdog_mode_t; + +typedef struct { + uint16_t index; /**< PDO entry index. */ + uint8_t subindex; /**< PDO entry subindex. */ + uint8_t bit_length; /**< Size of the PDO entry in bit. */ +} ec_pdo_entry_info_t; + +typedef struct { + uint16_t index; /**< PDO index. */ + uint32_t n_entries; + ec_pdo_entry_info_t const *entries; +} ec_pdo_info_t; + +typedef struct { + uint8_t index; /**< Sync manager index. */ + ec_direction_t dir; + uint32_t n_pdos; + ec_pdo_info_t const *pdos; + ec_watchdog_mode_t watchdog_mode; +} ec_sync_info_t; + +#endif \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_errno.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_errno.h new file mode 100644 index 00000000..c8efe23a --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_errno.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef EC_ERRNO_H +#define EC_ERRNO_H + +#define EC_ERR_OK 0 /**< No error */ +#define EC_ERR_NOMEM 1 /**< Out of memory */ +#define EC_ERR_INVAL 2 /**< Invalid argument */ +#define EC_ERR_TIMEOUT 3 /**< Timeout */ +#define EC_ERR_IO 4 /**< I/O error */ +#define EC_ERR_WC 5 /**< working counter error */ +#define EC_ERR_ALERR 6 /**< AL status error */ +#define EC_ERR_SII 7 /**< SII error */ +#define EC_ERR_MBOX 8 /**< mailbox error */ +#define EC_ERR_COE_TYPE 9 /**< COE type error */ +#define EC_ERR_COE_SIZE 10 /**< COE size error */ +#define EC_ERR_COE_REQUEST 11 /**< COE request & index & subindex error */ +#define EC_ERR_COE_TOGGLE 12 /**< COE toggle error */ +#define EC_ERR_COE_ABORT 13 /**< COE abort error */ +#define EC_ERR_FOE_TYPE 14 /**< FOE type error */ +#define EC_ERR_FOE_SIZE 15 /**< FOE size error */ +#define EC_ERR_FOE_OPCODE 16 /**< FOE opcode error */ +#define EC_ERR_FOE_PACKNO 17 /**< FOE packet number error */ + +#define EC_ERR_UNKNOWN 255 + +#endif \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_foe.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_foe.h new file mode 100644 index 00000000..bdcd133c --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_foe.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef EC_FOE_H +#define EC_FOE_H + +int ec_foe_write(ec_master_t *master, + uint16_t slave_index, + ec_datagram_t *datagram, + const char *filename, + uint32_t password, + const void *buf, + uint32_t size); + +int ec_foe_read(ec_master_t *master, + uint16_t slave_index, + ec_datagram_t *datagram, + const char *filename, + uint32_t password, + void *buf, + uint32_t maxsize, + uint32_t *size); +#endif \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_list.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_list.h new file mode 100644 index 00000000..7778edb6 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_list.h @@ -0,0 +1,468 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef EC_LIST_H +#define EC_LIST_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * ec_container_of - return the member address of ptr, if the type of ptr is the + * struct type. + */ +#define ec_container_of(ptr, type, member) \ + ((type *)((char *)(ptr) - (unsigned long)(&((type *)0)->member))) + +/** + * Single List structure + */ +struct ec_slist_node { + struct ec_slist_node *next; /**< point to next node. */ +}; +typedef struct ec_slist_node ec_slist_t; /**< Type for single list. */ + +/** + * @brief initialize a single list + * + * @param l the single list to be initialized + */ +static inline void ec_slist_init(ec_slist_t *l) +{ + l->next = NULL; +} + +static inline void ec_slist_add_head(ec_slist_t *l, ec_slist_t *n) +{ + n->next = l->next; + l->next = n; +} + +static inline void ec_slist_add_tail(ec_slist_t *l, ec_slist_t *n) +{ + ec_slist_t *tmp = l; + + while (tmp->next) { + tmp = tmp->next; + } + + /* append the node to the tail */ + tmp->next = n; + n->next = NULL; +} + +static inline void ec_slist_insert(ec_slist_t *l, ec_slist_t *next, ec_slist_t *n) +{ + if (!next) { + ec_slist_add_tail(next, l); + return; + } + + while (l->next) { + if (l->next == next) { + l->next = n; + n->next = next; + } + + l = l->next; + } +} + +static inline ec_slist_t *ec_slist_remove(ec_slist_t *l, ec_slist_t *n) +{ + ec_slist_t *tmp = l; + /* remove slist head */ + while (tmp->next && tmp->next != n) { + tmp = tmp->next; + } + + /* remove node */ + if (tmp->next != (ec_slist_t *)0) { + tmp->next = tmp->next->next; + } + + return l; +} + +static inline unsigned int ec_slist_len(const ec_slist_t *l) +{ + unsigned int len = 0; + const ec_slist_t *list = l->next; + + while (list != NULL) { + list = list->next; + len++; + } + + return len; +} + +static inline unsigned int ec_slist_contains(ec_slist_t *l, ec_slist_t *n) +{ + while (l->next) { + if (l->next == n) { + return 0; + } + + l = l->next; + } + + return 1; +} + +static inline ec_slist_t *ec_slist_head(ec_slist_t *l) +{ + return l->next; +} + +static inline ec_slist_t *ec_slist_tail(ec_slist_t *l) +{ + while (l->next) { + l = l->next; + } + + return l; +} + +static inline ec_slist_t *ec_slist_next(ec_slist_t *n) +{ + return n->next; +} + +static inline int ec_slist_isempty(ec_slist_t *l) +{ + return l->next == NULL; +} + +/** + * @brief initialize a slist object + */ +#define EC_SLIST_OBJESCT_INIT(object) \ + { \ + NULL \ + } + +/** + * @brief initialize a slist object + */ +#define EC_SLIST_DEFINE(slist) \ + ec_slist_t slist = { NULL } + +/** + * @brief get the struct for this single list node + * @param node the entry point + * @param type the type of structure + * @param member the name of list in structure + */ +#define ec_slist_entry(node, type, member) \ + ec_container_of(node, type, member) + +/** + * ec_slist_first_entry - get the first element from a slist + * @ptr: the slist head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the slist_struct within the struct. + * + * Note, that slist is expected to be not empty. + */ +#define ec_slist_first_entry(ptr, type, member) \ + ec_slist_entry((ptr)->next, type, member) + +/** + * ec_slist_tail_entry - get the tail element from a slist + * @ptr: the slist head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the slist_struct within the struct. + * + * Note, that slist is expected to be not empty. + */ +#define ec_slist_tail_entry(ptr, type, member) \ + ec_slist_entry(ec_slist_tail(ptr), type, member) + +/** + * ec_slist_first_entry_or_null - get the first element from a slist + * @ptr: the slist head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the slist_struct within the struct. + * + * Note, that slist is expected to be not empty. + */ +#define ec_slist_first_entry_or_null(ptr, type, member) \ + (ec_slist_isempty(ptr) ? NULL : ec_slist_first_entry(ptr, type, member)) + +/** + * ec_slist_for_each - iterate over a single list + * @pos: the ec_slist_t * to use as a loop cursor. + * @head: the head for your single list. + */ +#define ec_slist_for_each(pos, head) \ + for (pos = (head)->next; pos != NULL; pos = pos->next) + +#define ec_slist_for_each_safe(pos, next, head) \ + for (pos = (head)->next, next = pos->next; pos; \ + pos = next, next = pos->next) + +/** + * ec_slist_for_each_entry - iterate over single list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your single list. + * @member: the name of the list_struct within the struct. + */ +#define ec_slist_for_each_entry(pos, head, member) \ + for (pos = ec_slist_entry((head)->next, typeof(*pos), member); \ + &pos->member != (NULL); \ + pos = ec_slist_entry(pos->member.next, typeof(*pos), member)) + +#define ec_slist_for_each_entry_safe(pos, n, head, member) \ + for (pos = ec_slist_entry((head)->next, typeof(*pos), member), \ + n = ec_slist_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (NULL); \ + pos = n, n = ec_slist_entry(pos->member.next, typeof(*pos), member)) + +/** + * Double List structure + */ +struct ec_dlist_node { + struct ec_dlist_node *next; /**< point to next node. */ + struct ec_dlist_node *prev; /**< point to prev node. */ +}; +typedef struct ec_dlist_node ec_dlist_t; /**< Type for lists. */ + +/** + * @brief initialize a list + * + * @param l list to be initialized + */ +static inline void ec_dlist_init(ec_dlist_t *l) +{ + l->next = l->prev = l; +} + +/** + * @brief insert a node after a list + * + * @param l list to insert it + * @param n new node to be inserted + */ +static inline void ec_dlist_add_head(ec_dlist_t *l, ec_dlist_t *n) +{ + l->next->prev = n; + n->next = l->next; + + l->next = n; + n->prev = l; +} + +/** + * @brief insert a node before a list + * + * @param n new node to be inserted + * @param l list to insert it + */ +static inline void ec_dlist_add_tail(ec_dlist_t *l, ec_dlist_t *n) +{ + l->prev->next = n; + n->prev = l->prev; + + l->prev = n; + n->next = l; +} + +/** + * @brief remove node from list. + * @param n the node to remove from the list. + */ +static inline void ec_dlist_remove(ec_dlist_t *n) +{ + n->next->prev = n->prev; + n->prev->next = n->next; + + n->next = n->prev = n; +} + +/** + * @brief move node from list. + * @param n the node to remove from the list. + */ +static inline void ec_dlist_move_head(ec_dlist_t *l, ec_dlist_t *n) +{ + ec_dlist_remove(n); + ec_dlist_add_head(l, n); +} + +/** + * @brief move node from list. + * @param n the node to remove from the list. + */ +static inline void ec_dlist_move_tail(ec_dlist_t *l, ec_dlist_t *n) +{ + ec_dlist_remove(n); + ec_dlist_add_tail(l, n); +} + +/** + * @brief tests whether a list is empty + * @param l the list to test. + */ +static inline int ec_dlist_isempty(const ec_dlist_t *l) +{ + return l->next == l; +} + +/** + * @brief get the list length + * @param l the list to get. + */ +static inline unsigned int ec_dlist_len(const ec_dlist_t *l) +{ + unsigned int len = 0; + const ec_dlist_t *p = l; + + while (p->next != l) { + p = p->next; + len++; + } + + return len; +} + +/** + * @brief remove and init list + * @param n the list to get. + */ +static inline void ec_dlist_del_init(ec_dlist_t *n) +{ + ec_dlist_remove(n); +} + +/** + * @brief initialize a dlist object + */ +#define EC_DLIST_OBJESCT_INIT(object) \ + { \ + &(object), &(object) \ + } +/** + * @brief initialize a dlist object + */ +#define EC_DLIST_DEFINE(list) \ + ec_dlist_t list = { &(list), &(list) } + +/** + * @brief get the struct for this entry + * @param node the entry point + * @param type the type of structure + * @param member the name of list in structure + */ +#define ec_dlist_entry(node, type, member) \ + ec_container_of(node, type, member) + +/** + * dlist_first_entry - get the first element from a list + * @ptr: the list head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + * + * Note, that list is expected to be not empty. + */ +#define ec_dlist_first_entry(ptr, type, member) \ + ec_dlist_entry((ptr)->next, type, member) +/** + * dlist_first_entry_or_null - get the first element from a list + * @ptr: the list head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + * + * Note, that list is expected to be not empty. + */ +#define ec_dlist_first_entry_or_null(ptr, type, member) \ + (ec_dlist_isempty(ptr) ? NULL : ec_dlist_first_entry(ptr, type, member)) + +/** + * ec_dlist_for_each - iterate over a list + * @pos: the ec_dlist_t * to use as a loop cursor. + * @head: the head for your list. + */ +#define ec_dlist_for_each(pos, head) \ + for (pos = (head)->next; pos != (head); pos = pos->next) + +/** + * ec_dlist_for_each_prev - iterate over a list + * @pos: the dlist_t * to use as a loop cursor. + * @head: the head for your list. + */ +#define ec_dlist_for_each_prev(pos, head) \ + for (pos = (head)->prev; pos != (head); pos = pos->prev) + +/** + * ec_dlist_for_each_safe - iterate over a list safe against removal of list entry + * @pos: the dlist_t * to use as a loop cursor. + * @n: another dlist_t * to use as temporary storage + * @head: the head for your list. + */ +#define ec_dlist_for_each_safe(pos, n, head) \ + for (pos = (head)->next, n = pos->next; pos != (head); \ + pos = n, n = pos->next) + +#define ec_dlist_for_each_prev_safe(pos, n, head) \ + for (pos = (head)->prev, n = pos->prev; pos != (head); \ + pos = n, n = pos->prev) +/** + * ec_dlist_for_each_entry - iterate over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define ec_dlist_for_each_entry(pos, head, member) \ + for (pos = ec_dlist_entry((head)->next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = ec_dlist_entry(pos->member.next, typeof(*pos), member)) + +/** + * ec_dlist_for_each_entry_reverse - iterate over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define ec_dlist_for_each_entry_reverse(pos, head, member) \ + for (pos = ec_dlist_entry((head)->prev, typeof(*pos), member); \ + &pos->member != (head); \ + pos = ec_dlist_entry(pos->member.prev, typeof(*pos), member)) + +/** + * ec_dlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define ec_dlist_for_each_entry_safe(pos, n, head, member) \ + for (pos = ec_dlist_entry((head)->next, typeof(*pos), member), \ + n = ec_dlist_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = ec_dlist_entry(n->member.next, typeof(*n), member)) + +/** + * ec_dlist_for_each_entry_safe_reverse - iterate over list of given type safe against removal of list entry + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define ec_dlist_for_each_entry_safe_reverse(pos, n, head, member) \ + for (pos = ec_dlist_entry((head)->prev, typeof(*pos), field), \ + n = ec_dlist_entry(pos->member.prev, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = ec_dlist_entry(pos->member.prev, typeof(*pos), member)) + +#ifdef __cplusplus +} +#endif + +#endif /* EC_LIST_H */ diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_log.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_log.h new file mode 100644 index 00000000..5f4c48a7 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_log.h @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef EC_LOG_H +#define EC_LOG_H + +#include + +/* DEBUG level */ +#define EC_DBG_ERROR 0 +#define EC_DBG_WARNING 1 +#define EC_DBG_INFO 2 +#define EC_DBG_LOG 3 + +#ifndef EC_DBG_TAG +#define EC_DBG_TAG "EC" +#endif +/* + * The color for terminal (foreground) + * BLACK 30 + * RED 31 + * GREEN 32 + * YELLOW 33 + * BLUE 34 + * PURPLE 35 + * CYAN 36 + * WHITE 37 + */ + +#define ec_master_dbg_log_line(lvl, color_n, fmt, ...) \ + do { \ + CONFIG_EC_PRINTF("\033[" #color_n "m[" lvl "/ec_master" \ + "] "); \ + CONFIG_EC_PRINTF(fmt, ##__VA_ARGS__); \ + CONFIG_EC_PRINTF("\033[0m"); \ + } while (0) + +#define ec_slave_dbg_log_line(lvl, color_n, fmt, ...) \ + do { \ + CONFIG_EC_PRINTF("\033[" #color_n "m[" lvl "/ec_slave" \ + "] "); \ + CONFIG_EC_PRINTF(fmt, ##__VA_ARGS__); \ + CONFIG_EC_PRINTF("\033[0m"); \ + } while (0) + +#if (CONFIG_EC_DBG_LEVEL >= EC_DBG_LOG) +#define EC_LOG_DBG(fmt, ...) ec_master_dbg_log_line("D", 0, fmt, ##__VA_ARGS__) +#else +#define EC_LOG_DBG(...) \ + { \ + } +#endif + +#if (CONFIG_EC_DBG_LEVEL >= EC_DBG_INFO) +#define EC_LOG_INFO(fmt, ...) ec_master_dbg_log_line("I", 32, fmt, ##__VA_ARGS__) +#else +#define EC_LOG_INFO(...) \ + { \ + } +#endif + +#if (CONFIG_EC_DBG_LEVEL >= EC_DBG_WARNING) +#define EC_LOG_WRN(fmt, ...) ec_master_dbg_log_line("W", 33, fmt, ##__VA_ARGS__) +#else +#define EC_LOG_WRN(...) \ + { \ + } +#endif + +#if (CONFIG_EC_DBG_LEVEL >= EC_DBG_ERROR) +#define EC_LOG_ERR(fmt, ...) ec_master_dbg_log_line("E", 31, fmt, ##__VA_ARGS__) +#else +#define EC_LOG_ERR(...) \ + { \ + } +#endif + +#if (CONFIG_EC_SLAVE_DBG_LEVEL >= EC_DBG_LOG) +#define EC_SLAVE_LOG_DBG(fmt, ...) ec_slave_dbg_log_line("D", 0, fmt, ##__VA_ARGS__) +#else +#define EC_SLAVE_LOG_DBG(...) \ + { \ + } +#endif + +#if (CONFIG_EC_SLAVE_DBG_LEVEL >= EC_DBG_INFO) +#define EC_SLAVE_LOG_INFO(fmt, ...) ec_slave_dbg_log_line("I", 32, fmt, ##__VA_ARGS__) +#else +#define EC_SLAVE_LOG_INFO(...) \ + { \ + } +#endif + +#if (CONFIG_EC_SLAVE_DBG_LEVEL >= EC_DBG_WARNING) +#define EC_SLAVE_LOG_WRN(fmt, ...) ec_slave_dbg_log_line("W", 33, fmt, ##__VA_ARGS__) +#else +#define EC_SLAVE_LOG_WRN(...) \ + { \ + } +#endif + +#if (CONFIG_EC_SLAVE_DBG_LEVEL >= EC_DBG_ERROR) +#define EC_SLAVE_LOG_ERR(fmt, ...) ec_slave_dbg_log_line("E", 31, fmt, ##__VA_ARGS__) +#else +#define EC_SLAVE_LOG_ERR(...) \ + { \ + } +#endif + +#define EC_LOG_RAW(...) CONFIG_EC_PRINTF(__VA_ARGS__) + +#ifndef CONFIG_EC_ASSERT_DISABLE +#define EC_ASSERT(f) \ + do { \ + if (!(f)) { \ + EC_LOG_ERR("ASSERT FAIL [%s] @ %s:%d\r\n", #f, __FILE__, __LINE__); \ + while (1) { \ + } \ + } \ + } while (false) + +#define EC_ASSERT_MSG(f, fmt, ...) \ + do { \ + if (!(f)) { \ + EC_LOG_ERR("ASSERT FAIL [%s] @ %s:%d\r\n", #f, __FILE__, __LINE__); \ + EC_LOG_ERR(fmt "\r\n", ##__VA_ARGS__); \ + while (1) { \ + } \ + } \ + } while (false) +#else +#define EC_ASSERT(f) \ + { \ + } +#define EC_ASSERT_MSG(f, fmt, ...) \ + { \ + } +#endif + +#define ___is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ') +static inline void ec_hexdump(const void *ptr, uint32_t buflen) +{ + unsigned char *buf = (unsigned char *)ptr; + unsigned int i, j; + + (void)buf; + + for (i = 0; i < buflen; i += 16) { + CONFIG_EC_PRINTF("%08x:", i); + + for (j = 0; j < 16; j++) + if (i + j < buflen) { + if ((j % 8) == 0) { + CONFIG_EC_PRINTF(" "); + } + + CONFIG_EC_PRINTF("%02X ", buf[i + j]); + } else + CONFIG_EC_PRINTF(" "); + CONFIG_EC_PRINTF(" "); + + for (j = 0; j < 16; j++) + if (i + j < buflen) + CONFIG_EC_PRINTF("%c", ___is_print(buf[i + j]) ? buf[i + j] : '.'); + CONFIG_EC_PRINTF("\n"); + } +} + +#endif /* EC_LOG_H */ diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_mailbox.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_mailbox.h new file mode 100644 index 00000000..43079d8e --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_mailbox.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef EC_MAILBOX_H +#define EC_MAILBOX_H + +uint8_t *ec_mailbox_fill_send(ec_master_t *master, + uint16_t slave_index, + ec_datagram_t *datagram, + uint8_t type, + uint16_t size); +int ec_mailbox_send(ec_master_t *master, + uint16_t slave_index, + ec_datagram_t *datagram); +int ec_mailbox_read_status(ec_master_t *master, + uint16_t slave_index, + ec_datagram_t *datagram, + uint32_t timeout_us); +int ec_mailbox_receive(ec_master_t *master, + uint16_t slave_index, + ec_datagram_t *datagram, + uint8_t *type, + uint32_t *size, + uint32_t timeout_us); + +#endif \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_master.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_master.h new file mode 100644 index 00000000..4432e13e --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_master.h @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef EC_MASTER_H +#define EC_MASTER_H + +#include +#include +#include +#include + +#include "ec_config.h" +#include "ec_util.h" +#include "ec_list.h" +#include "ec_errno.h" +#include "ec_log.h" +#include "esc_register.h" +#include "ec_def.h" +#include "ec_osal.h" +#include "ec_port.h" +#include "ec_datagram.h" +#include "ec_common.h" +#include "ec_sii.h" +#include "ec_slave.h" +#include "ec_mailbox.h" +#include "ec_coe.h" +#include "ec_cmd.h" +#include "ec_perf.h" +#include "ec_timestamp.h" +#include "ec_version.h" +#include "ec_foe.h" + +/** Netdev statistics. + */ +typedef struct { + uint64_t tx_count; /**< Number of frames sent. */ + uint64_t last_tx_count; /**< Number of frames sent of last statistics cycle. */ + uint64_t rx_count; /**< Number of frames received. */ + uint64_t last_rx_count; /**< Number of frames received of last statistics cycle. */ + uint64_t tx_bytes; /**< Number of bytes sent. */ + uint64_t last_tx_bytes; /**< Number of bytes sent of last statistics cycle. */ + uint64_t rx_bytes; /**< Number of bytes received. */ + uint64_t last_rx_bytes; /**< Number of bytes received of last statistics cycle. */ + uint64_t last_loss; /**< Tx/Rx difference of last statistics cycle. */ + int32_t tx_frame_rates[EC_RATE_COUNT]; /**< Transmit rates in frames/s for different statistics cycle periods.*/ + int32_t rx_frame_rates[EC_RATE_COUNT]; /**< Receive rates in frames/s for different statistics cycle periods.*/ + int32_t tx_byte_rates[EC_RATE_COUNT]; /**< Transmit rates in byte/s for different statistics cycle periods. */ + int32_t rx_byte_rates[EC_RATE_COUNT]; /**< Receive rates in byte/s for different statistics cycle periods. */ + int32_t loss_rates[EC_RATE_COUNT]; /**< Frame loss rates for different statistics cycle periods. */ + uint64_t last_jiffies; /**< Jiffies of last statistic cycle. */ +} ec_netdev_stats_t; + +/** Cyclic statistics. + */ +typedef struct { + unsigned int timeouts; /**< datagram timeouts */ + unsigned int corrupted; /**< corrupted frames */ + unsigned int unmatched; /**< unmatched datagrams (received, but not queued any longer) */ + unsigned long output_jiffies; /**< time of last output */ +} ec_stats_t; + +typedef enum { + EC_ORPHANED, /**< Orphaned phase. The master has no Ethernet device attached. */ + EC_IDLE, /**< Idle phase. An Ethernet device is attached, but the master is not in use, yet. */ + EC_OPERATION /**< Operation phase. The master was requested by a realtime application. */ +} ec_master_phase_t; + +typedef struct { + ec_dlist_t queue; + ec_datagram_t datagrams[CONFIG_EC_MAX_NETDEVS]; +#if CONFIG_EC_MAX_NETDEVS > 1 + uint8_t *send_buffer; +#endif + uint32_t expected_working_counter; + ec_slave_t *slave; +} ec_pdo_datagram_t; + +typedef struct ec_master { + uint8_t index; + ec_netdev_t *netdev[CONFIG_EC_MAX_NETDEVS]; + bool link_state[CONFIG_EC_MAX_NETDEVS]; + uint32_t slaves_responding[CONFIG_EC_MAX_NETDEVS]; + ec_slave_state_t slaves_state[CONFIG_EC_MAX_NETDEVS]; + ec_netdev_stats_t netdev_stats; + ec_stats_t stats; + ec_master_phase_t phase; + bool active; /**< Master is started. */ + bool scan_done; /**< Slave scan is done. */ + + ec_datagram_t main_datagram; /**< Main datagram for slave scan & state change & config & sii */ + + ec_dlist_t datagram_queue; /**< Queue of pending datagrams*/ + ec_dlist_t pdo_datagram_queue; /**< Queue of pdo datagrams*/ + uint8_t datagram_index; + + ec_slave_t *dc_ref_clock; /**< DC reference clock slave. */ + ec_datagram_t dc_ref_sync_datagram; /**< Datagram used for synchronizing the reference clock to the master clock. */ + ec_datagram_t dc_all_sync_datagram; /**< Datagram used for synchronizing all slaves to the dc ref clock. */ + ec_datagram_t systime_diff_mon_datagram; /**< Datagram used for reading the system time difference between master and reference clock. */ + + uint32_t min_systime_diff; + uint32_t max_systime_diff; + uint32_t curr_systime_diff; + uint32_t systime_diff_count; + uint64_t total_systime_diff; + bool systime_diff_enable; + + uint64_t interval; + + ec_slave_t *slaves; + uint32_t slave_count; + +#ifdef CONFIG_EC_PERF_ENABLE + ec_perf_t perf; +#endif + + ec_osal_mutex_t scan_lock; + ec_osal_thread_t scan_thread; + ec_osal_thread_t nonperiod_thread; + ec_osal_sem_t nonperiod_sem; + struct ec_osal_timer *linkdetect_timer; + bool nonperiod_suspend; + + uint8_t pdo_buffer[CONFIG_EC_MAX_NETDEVS][CONFIG_EC_MAX_PDO_BUFSIZE]; + uint32_t actual_pdo_size; + uint32_t expected_working_counter; + uint32_t actual_working_counter; +} ec_master_t; + +int ec_master_init(ec_master_t *master, uint8_t master_index); +void ec_master_deinit(ec_master_t *master); +int ec_master_start(ec_master_t *master, uint32_t period_us); +int ec_master_stop(ec_master_t *master); +int ec_master_queue_ext_datagram(ec_master_t *master, ec_datagram_t *datagram, bool wakep_poll, bool waiter); +uint8_t *ec_master_get_slave_domain(ec_master_t *master, uint32_t slave_index); +uint8_t *ec_master_get_slave_domain_output(ec_master_t *master, uint32_t slave_index); +uint8_t *ec_master_get_slave_domain_input(ec_master_t *master, uint32_t slave_index); +uint32_t ec_master_get_slave_domain_size(ec_master_t *master, uint32_t slave_index); +uint32_t ec_master_get_slave_domain_osize(ec_master_t *master, uint32_t slave_index); +uint32_t ec_master_get_slave_domain_isize(ec_master_t *master, uint32_t slave_index); + +#endif \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_netdev.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_netdev.h new file mode 100644 index 00000000..2641b4f2 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_netdev.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef EC_NETDEV_H +#define EC_NETDEV_H + +#include "phy/chry_phy.h" + +typedef struct ec_master ec_master_t; + +typedef struct ec_netdev { + ec_master_t *master; + struct chry_phy_device phydev; + uint8_t index; + char name[20]; + uint8_t mac_addr[6]; + bool link_state; + uint8_t tx_frame_index; + unsigned long jiffies_poll; + + // Frame statistics + uint64_t tx_count; /**< Number of frames sent. */ + uint64_t last_tx_count; /**< Number of frames sent of last statistics cycle.*/ + uint64_t rx_count; /**< Number of frames received. */ + uint64_t last_rx_count; /**< Number of frames received of last statistics cycle.*/ + uint64_t tx_bytes; /**< Number of bytes sent. */ + uint64_t last_tx_bytes; /**< Number of bytes sent of last statistics cycle.*/ + uint64_t rx_bytes; /**< Number of bytes received. */ + uint64_t last_rx_bytes; /**< Number of bytes received of last statistics cycle.*/ + uint64_t tx_errors; /**< Number of transmit errors. */ + int32_t tx_frame_rates[EC_RATE_COUNT]; /**< Transmit rates in frames/s for different statistics cycle periods.*/ + int32_t rx_frame_rates[EC_RATE_COUNT]; /**< Receive rates in frames/s for different statistics cycle periods.*/ + int32_t tx_byte_rates[EC_RATE_COUNT]; /**< Transmit rates in byte/s for different statistics cycle periods.*/ + int32_t rx_byte_rates[EC_RATE_COUNT]; /**< Receive rates in byte/s for different statistics cycle periods.*/ + +} ec_netdev_t; + +void ec_netdev_clear_stats(ec_netdev_t *netdev); +void ec_netdev_update_stats(ec_netdev_t *netdev); + +ec_netdev_t *ec_netdev_init(uint8_t netdev_index); +void ec_netdev_poll_link_state(ec_netdev_t *netdev); +uint8_t *ec_netdev_get_txbuf(ec_netdev_t *netdev); +int ec_netdev_send(ec_netdev_t *netdev, uint32_t size); +void ec_netdev_receive(ec_netdev_t *netdev, uint8_t *frame, uint32_t size); + +#endif \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_osal.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_osal.h new file mode 100644 index 00000000..618fae7e --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_osal.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef EC_OSAL_H +#define EC_OSAL_H + +#include +#include +#include + +#ifdef __INCLUDE_NUTTX_CONFIG_H +#define CONFIG_EC_OSAL_THREAD_SET_ARGV int argc, char **argv +#define CONFIG_EC_OSAL_THREAD_GET_ARGV ((uintptr_t)strtoul(argv[1], NULL, 16)) +#elif defined(__ZEPHYR__) +#define CONFIG_EC_OSAL_THREAD_SET_ARGV void *p1, void *p2, void *p3 +#define CONFIG_EC_OSAL_THREAD_GET_ARGV ((uintptr_t)p1) +#else +#define CONFIG_EC_OSAL_THREAD_SET_ARGV void *argument +#define CONFIG_EC_OSAL_THREAD_GET_ARGV ((uintptr_t)argument) +#endif + +#define EC_OSAL_WAITING_FOREVER (0xFFFFFFFFU) + +typedef void *ec_osal_thread_t; +typedef void *ec_osal_sem_t; +typedef void *ec_osal_mutex_t; +typedef void (*ec_thread_entry_t)(CONFIG_EC_OSAL_THREAD_SET_ARGV); +typedef void (*ec_timer_handler_t)(void *argument); +struct ec_osal_timer { + ec_timer_handler_t handler; + void *argument; + bool is_period; + uint32_t timeout_ms; + void *timer; +}; + +/* + * Task with smaller priority value indicates higher task priority +*/ +ec_osal_thread_t ec_osal_thread_create(const char *name, uint32_t stack_size, uint32_t prio, ec_thread_entry_t entry, void *args); +void ec_osal_thread_delete(ec_osal_thread_t thread); +void ec_osal_thread_suspend(ec_osal_thread_t thread); +void ec_osal_thread_resume(ec_osal_thread_t thread); + +ec_osal_sem_t ec_osal_sem_create(uint32_t max_count, uint32_t initial_count); +void ec_osal_sem_delete(ec_osal_sem_t sem); +int ec_osal_sem_take(ec_osal_sem_t sem, uint32_t timeout); +int ec_osal_sem_give(ec_osal_sem_t sem); +void ec_osal_sem_reset(ec_osal_sem_t sem); + +ec_osal_mutex_t ec_osal_mutex_create(void); +void ec_osal_mutex_delete(ec_osal_mutex_t mutex); +int ec_osal_mutex_take(ec_osal_mutex_t mutex); +int ec_osal_mutex_give(ec_osal_mutex_t mutex); + +struct ec_osal_timer *ec_osal_timer_create(const char *name, uint32_t timeout_ms, ec_timer_handler_t handler, void *argument, bool is_period); +void ec_osal_timer_delete(struct ec_osal_timer *timer); +void ec_osal_timer_start(struct ec_osal_timer *timer); +void ec_osal_timer_stop(struct ec_osal_timer *timer); + +size_t ec_osal_enter_critical_section(void); +void ec_osal_leave_critical_section(size_t flag); + +void ec_osal_msleep(uint32_t delay); + +void *ec_osal_malloc(size_t size); +void ec_osal_free(void *ptr); + +#endif /* EC_OSAL_H */ diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_perf.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_perf.h new file mode 100644 index 00000000..2ad471ea --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_perf.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef EC_PERF_H +#define EC_PERF_H + +typedef struct { + bool enable; // Enable performance measurement + uint64_t count; // Current measurement count + + uint64_t min_interval; // Minimum interval + uint64_t max_interval; // Maximum interval + int64_t min_jitter; // Minimum jitter + int64_t max_jitter; // Maximum jitter + uint64_t total_interval; // Total interval time + int64_t total_jitter; // Total jitter (for average calculation) + + uint32_t ignore_count; // Number of ignored measurements + uint64_t last_timestamp; // Last interrupt timestamp + uint64_t expected_interval; // Expected interrupt interval +} ec_perf_t; + +void ec_perf_init(ec_perf_t *perf, uint64_t expected_interval_us); +void ec_perf_polling(ec_perf_t *perf); +bool ec_perf_is_complete(ec_perf_t *perf); +void ec_perf_print_statistics(ec_perf_t *perf); + +#endif \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_port.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_port.h new file mode 100644 index 00000000..d0c504be --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_port.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef EC_PORT_H +#define EC_PORT_H + +#include "ec_netdev.h" + +typedef void (*ec_htimer_cb)(void *arg); + +ec_netdev_t *ec_netdev_low_level_init(uint8_t netdev_index); +#ifndef CONFIG_EC_PHY_CUSTOM +void ec_netdev_low_level_link_up(ec_netdev_t *netdev, struct chry_phy_status *status); +#else +void ec_netdev_low_level_poll_link_state(ec_netdev_t *netdev); +#endif +uint8_t *ec_netdev_low_level_get_txbuf(ec_netdev_t *netdev); +int ec_netdev_low_level_output(ec_netdev_t *netdev, uint32_t size); +int ec_netdev_low_level_input(ec_netdev_t *netdev); + +void ec_mdio_low_level_write(struct chry_phy_device *phydev, uint16_t phy_addr, uint16_t regnum, uint16_t val); +uint16_t ec_mdio_low_level_read(struct chry_phy_device *phydev, uint16_t phy_addr, uint16_t regnum); + +void ec_htimer_start(uint32_t us, ec_htimer_cb cb, void *arg); +void ec_htimer_stop(void); + +uint32_t ec_get_cpu_frequency(void); + +#endif \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_sii.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_sii.h new file mode 100644 index 00000000..74b44d8f --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_sii.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef EC_SII_H +#define EC_SII_H + +typedef struct ec_slave ec_slave_t; + +typedef struct ec_sii { + // Non-category data + uint16_t aliasaddr; /**< Configured station alias. */ + uint32_t vendor_id; /**< Vendor ID. */ + uint32_t product_code; /**< Vendor-specific product code. */ + uint32_t revision_number; /**< Revision number. */ + uint32_t serial_number; /**< Serial number. */ + uint16_t boot_rx_mailbox_offset; /**< Bootstrap receive mailbox address. */ + uint16_t boot_rx_mailbox_size; /**< Bootstrap receive mailbox size. */ + uint16_t boot_tx_mailbox_offset; /**< Bootstrap transmit mailbox address. */ + uint16_t boot_tx_mailbox_size; /**< Bootstrap transmit mailbox size. */ + uint16_t std_rx_mailbox_offset; /**< Standard receive mailbox address. */ + uint16_t std_rx_mailbox_size; /**< Standard receive mailbox size. */ + uint16_t std_tx_mailbox_offset; /**< Standard transmit mailbox address. */ + uint16_t std_tx_mailbox_size; /**< Standard transmit mailbox size. */ + uint16_t mailbox_protocols; /**< Supported mailbox protocols. */ + + // General + ec_sii_general_t general; + bool has_general; + + // Strings + char **strings; /**< Strings in SII categories. */ + uint32_t string_count; /**< Number of SII strings. */ +} ec_sii_t; + +int ec_sii_read(ec_master_t *master, uint16_t slave_index, ec_datagram_t *datagram, uint16_t woffset, uint32_t *buf, uint32_t len); +int ec_sii_write(ec_master_t *master, uint16_t slave_index, ec_datagram_t *datagram, uint16_t woffset, const uint16_t *buf, uint32_t len); + +#endif \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_slave.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_slave.h new file mode 100644 index 00000000..6c34d6b2 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_slave.h @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef EC_SALVE_H +#define EC_SALVE_H + +typedef struct ec_master ec_master_t; +typedef struct ec_slave ec_slave_t; + +typedef struct +{ + ec_direction_t dir; + uint32_t logical_start_address; + uint32_t data_size; +} ec_fmmu_info_t; + +typedef struct { + uint16_t physical_start_address; + uint16_t length; + uint8_t control; + uint8_t enable; + ec_pdo_assign_t pdo_assign; + ec_pdo_mapping_t pdo_mapping[CONFIG_EC_PER_SM_MAX_PDOS]; + ec_fmmu_info_t fmmu; + bool fmmu_enable; +} ec_sm_info_t; + +typedef struct { + ec_sync_info_t *sync; /**< Sync manager configuration. */ + uint8_t sync_count; /**< Number of sync managers. */ + uint16_t dc_assign_activate; /**< dc assign control */ + ec_sync_signal_t dc_sync[EC_SYNC_SIGNAL_COUNT]; /**< DC sync signals. */ +} ec_slave_config_t; + +/** EtherCAT slave port descriptor. + */ +typedef enum { + EC_PORT_NOT_IMPLEMENTED, /**< Port is not implemented. */ + EC_PORT_NOT_CONFIGURED, /**< Port is not configured. */ + EC_PORT_EBUS, /**< Port is an E-Bus. */ + EC_PORT_MII /**< Port is a MII. */ +} ec_slave_port_desc_t; + +/** EtherCAT slave port information. + */ +typedef struct { + uint8_t link_up; /**< Link detected. */ + uint8_t loop_closed; /**< Loop closed. */ + uint8_t signal_detected; /**< Detected signal on RX port. */ +} ec_slave_port_link_t; + +typedef struct { + ec_slave_port_desc_t desc; /**< Port descriptors. */ + ec_slave_port_link_t link; /**< Port link status. */ + ec_slave_t *next_slave; /**< Connected slaves. */ + uint32_t receive_time; /**< Port receive times for delay measurement. */ + uint32_t delay_to_next_dc; /**< Delay to next slave with DC support behind this port [ns]. */ +} ec_slave_port_t; + +typedef struct ec_slave { + uint32_t index; /**< Index of the slave in the master slave array. */ + ec_master_t *master; /**< Master owning the slave. */ + ec_netdev_index_t netdev_idx; /**< Index of device the slave responds on. */ + + uint16_t autoinc_address; /**< Auto-increment address. */ + uint16_t station_address; /**< Configured station address. */ + uint16_t effective_alias; /**< Effective alias address. */ + + ec_slave_port_t ports[EC_MAX_PORTS]; /**< Port information. */ + + ec_slave_state_t requested_state; /**< Requested application state. */ + ec_slave_state_t current_state; /**< Current application state. */ + uint32_t alstatus_code; /**< Error code in AL Status register. */ + bool force_update; /**< Force update of the slave. */ + + uint16_t configured_rx_mailbox_offset; /**< Configured receive mailbox offset. */ + uint16_t configured_rx_mailbox_size; /**< Configured receive mailbox size.*/ + uint16_t configured_tx_mailbox_offset; /**< Configured send mailbox offset. */ + uint16_t configured_tx_mailbox_size; /**< Configured send mailbox size. */ + + uint8_t base_type; /**< Slave type. */ + uint8_t base_revision; /**< Revision. */ + uint16_t base_build; /**< Build number. */ + uint8_t base_fmmu_count; /**< Number of supported FMMUs. */ + uint8_t base_sync_count; /**< Number of supported sync managers. */ + uint8_t base_fmmu_bit_operation; /**< FMMU bit operation is supported. */ + uint8_t base_dc_supported; /**< Distributed clocks are supported. */ + ec_slave_dc_range_t base_dc_range; /**< DC range. */ + uint8_t has_dc_system_time; /**< The slave supports the DC system time register. Otherwise it can only be used for delay measurement. */ + uint32_t transmission_delay; /**< DC system time transmission delay (offset from reference clock). */ + + uint32_t logical_start_address; + uint32_t odata_size; + uint32_t idata_size; + uint32_t expected_working_counter; + uint32_t actual_working_counter; + + uint16_t *sii_image; /**< Complete SII image. */ + size_t sii_nwords; /**< Size of the SII contents in words. */ + + ec_sii_t sii; /**< Extracted SII data. */ + + ec_sm_info_t sm_info[EC_MAX_SYNC_MANAGERS]; + uint8_t sm_count; /**< Number of sync managers. */ + + ec_slave_config_t *config; /**< Slave custom configuration. */ +} ec_slave_t; + +void ec_slaves_scanning(ec_master_t *master); +char *ec_slave_get_sii_string(const ec_slave_t *slave, uint32_t index); + +#endif \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_timestamp.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_timestamp.h new file mode 100644 index 00000000..6af7af55 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_timestamp.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef EC_TIMESTAMP_H +#define EC_TIMESTAMP_H + +void ec_timestamp_init(void); +uint64_t ec_timestamp_get_time_ns(void); +uint64_t ec_timestamp_get_time_us(void); + +#define jiffies ec_timestamp_get_time_us() + +#endif \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_util.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_util.h new file mode 100644 index 00000000..97e8a792 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_util.h @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef EC_UTIL_H +#define EC_UTIL_H + +#if defined(__CC_ARM) +#ifndef __USED +#define __USED __attribute__((used)) +#endif +#ifndef __WEAK +#define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED +#define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION +#define __PACKED_UNION __packed union +#endif +#ifndef __ALIGNED +#define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#elif defined(__GNUC__) +#ifndef __USED +#define __USED __attribute__((used)) +#endif +#ifndef __WEAK +#define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED +#define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION +#define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __ALIGNED +#define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#elif defined(__ICCARM__) || defined(__ICCRX__) || defined(__ICCRISCV__) +#if (__VER__ >= 8000000) +#define __ICCARM_V8 1 +#else +#define __ICCARM_V8 0 +#endif + +#ifndef __USED +#if defined(__ICCARM_V8) || defined(__ICCRISCV__) +#define __USED __attribute__((used)) +#else +#define __USED __root +#endif +#endif + +#ifndef __WEAK +#if defined(__ICCARM_V8) || defined(__ICCRISCV__) +#define __WEAK __attribute__((weak)) +#else +#define __WEAK _Pragma("__weak") +#endif +#endif + +#ifndef __PACKED +#if defined(__ICCARM_V8) || defined(__ICCRISCV__) +#define __PACKED __attribute__((packed, aligned(1))) +#else +/* Needs IAR language extensions */ +#define __PACKED __packed +#endif +#endif + +#ifndef __PACKED_STRUCT +#if defined(__ICCARM_V8) || defined(__ICCRISCV__) +#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#else +/* Needs IAR language extensions */ +#define __PACKED_STRUCT __packed struct +#endif +#endif + +#ifndef __PACKED_UNION +#if defined(__ICCARM_V8) || defined(__ICCRISCV__) +#define __PACKED_UNION union __attribute__((packed, aligned(1))) +#else +/* Needs IAR language extensions */ +#define __PACKED_UNION __packed union +#endif +#endif + +#ifndef __ALIGNED +#if defined(__ICCARM_V8) || defined(__ICCRISCV__) +#define __ALIGNED(x) __attribute__((aligned(x))) +#elif (__VER__ >= 7080000) +/* Needs IAR language extensions */ +#define __ALIGNED(x) __attribute__((aligned(x))) +#else +#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. +#define __ALIGNED(x) +#endif +#endif + +#endif + +#ifndef MAX +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif + +#ifndef MIN +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#define EC_ALIGN_UP(size, align) (((size) + (align)-1) & ~((align)-1)) + +#define EC_WRITE_U8(DATA, VAL) \ + do { \ + *((uint8_t *)(DATA)) = ((uint8_t)(VAL)); \ + } while (0) + +#define EC_WRITE_U16(DATA, VAL) \ + do { \ + *((uint16_t *)(DATA)) = ((uint16_t)(VAL)); \ + } while (0) + +#define EC_WRITE_U32(DATA, VAL) \ + do { \ + *((uint32_t *)(DATA)) = ((uint32_t)(VAL)); \ + } while (0) + +#define EC_WRITE_U64(DATA, VAL) \ + do { \ + *((uint64_t *)(DATA)) = ((uint64_t)(VAL)); \ + } while (0) + +#define EC_READ_U8(DATA) \ + ((uint8_t) * ((uint8_t *)(DATA))) + +#define EC_READ_U16(DATA) \ + ((uint16_t) * ((uint16_t *)(DATA))) + +#define EC_READ_U32(DATA) \ + ((uint32_t) * ((uint32_t *)(DATA))) + +#define EC_READ_U64(DATA) \ + ((uint64_t) * ((uint64_t *)(DATA))) + +#define ec_htons(A) ((((uint16_t)(A)&0xff00) >> 8) | \ + (((uint16_t)(A)&0x00ff) << 8)) +#define ec_htonl(A) ((((uint32_t)(A)&0xff000000) >> 24) | \ + (((uint32_t)(A)&0x00ff0000) >> 8) | \ + (((uint32_t)(A)&0x0000ff00) << 8) | \ + (((uint32_t)(A)&0x000000ff) << 24)) + +#endif \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_version.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_version.h new file mode 100644 index 00000000..b0afffe8 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/ec_version.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef EC_VERSION_H +#define EC_VERSION_H + +#define CHERRYECAT_VERSION 0x000100 +#define CHERRYECAT_VERSION_STR "v0.1.0" + +#endif \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/esc_register.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/esc_register.h new file mode 100644 index 00000000..9760549b --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/esc_register.h @@ -0,0 +1,4552 @@ +/* + * Copyright (c) 2021-2025 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef ESC_REGISTER_H +#define ESC_REGISTER_H + +#define __R volatile const /* Define "read-only" permission */ +#define __RW volatile /* Define "read-write" permission */ +#define __W volatile /* Define "write-only" permission */ + +typedef struct { + __R uint8_t TYPE; /* 0x0: Type of EtherCAT controller */ + __R uint8_t REVISION; /* 0x1: Revision of EtherCAT controller */ + __R uint16_t BUILD; /* 0x2: Build of EtherCAT controller */ + __R uint8_t FMMU_NUM; /* 0x4: FMMU supported */ + __R uint8_t SYNCM_NUM; /* 0x5: SyncManagers supported */ + __R uint8_t RAM_SIZE; /* 0x6: RAM Size */ + __R uint8_t PORT_DESC; /* 0x7: Port Descriptor */ + __R uint16_t FEATURE; /* 0x8: ESC Feature supported */ + __R uint8_t RESERVED0[6]; /* 0xA - 0xF: Reserved */ + __R uint16_t STATION_ADDR; /* 0x10: Configured Station Address */ + __RW uint16_t STATION_ALS; /* 0x12: Configured Station Alias */ + __R uint8_t RESERVED1[12]; /* 0x14 - 0x1F: Reserved */ + __R uint8_t REG_WEN; /* 0x20: Register Write Enable */ + __R uint8_t REG_WP; /* 0x21: Register Write Protection */ + __R uint8_t RESERVED2[14]; /* 0x22 - 0x2F: Reserved */ + __R uint8_t ESC_WEN; /* 0x30: ESC Write Enable */ + __R uint8_t ESC_WP; /* 0x31: ESC Write Protection */ + __R uint8_t RESERVED3[14]; /* 0x32 - 0x3F: Reserved */ + __R uint8_t ESC_RST_ECAT; /* 0x40: ESC Reset ECAT */ + __RW uint8_t ESC_RST_PDI; /* 0x41: ESC Reset PDI */ + __R uint8_t RESERVED4[190]; /* 0x42 - 0xFF: Reserved */ + __R uint32_t ESC_DL_CTRL; /* 0x100: ESC DL Control */ + __R uint8_t RESERVED5[4]; /* 0x104 - 0x107: Reserved */ + __R uint16_t PHYSICAL_RW_OFFSET; /* 0x108: Physical Read/Write Offset */ + __R uint8_t RESERVED6[6]; /* 0x10A - 0x10F: Reserved */ + __R uint16_t ESC_DL_STAT; /* 0x110: ESC DL Status */ + __R uint8_t RESERVED7[14]; /* 0x112 - 0x11F: Reserved */ + __RW uint16_t AL_CTRL; /* 0x120: AL Control */ + __R uint8_t RESERVED8[14]; /* 0x122 - 0x12F: Reserved */ + __RW uint16_t AL_STAT; /* 0x130: AL Status */ + __R uint8_t RESERVED9[2]; /* 0x132 - 0x133: Reserved */ + __RW uint16_t AL_STAT_CODE; /* 0x134: AL Status Code */ + __R uint8_t RESERVED10[2]; /* 0x136 - 0x137: Reserved */ + __RW uint8_t RUN_LED_OVRD; /* 0x138: RUN LED Override */ + __RW uint8_t ERR_LED_OVRD; /* 0x139: ERR LED Override */ + __R uint8_t RESERVED11[6]; /* 0x13A - 0x13F: Reserved */ + __R uint8_t PDI_CTRL; /* 0x140: PDI Control */ + __R uint8_t ESC_CFG; /* 0x141: ESC Configuration */ + __R uint8_t RESERVED12[12]; /* 0x142 - 0x14D: Reserved */ + __R uint16_t PDI_INFO; /* 0x14E: PDI Information */ + __R uint8_t PDI_CFG; /* 0x150: PDI Configuration */ + __R uint8_t PDI_SL_CFG; /* 0x151: PDI Sync/Latch[1:0] Configuration */ + __RW uint16_t PDI_EXT_CFG; /* 0x152: PDI Extended Configuration */ + __R uint8_t RESERVED13[172]; /* 0x154 - 0x1FF: Reserved */ + __R uint16_t ECAT_EVT_MSK; /* 0x200: ECAT Event Mask */ + __R uint8_t RESERVED14[2]; /* 0x202 - 0x203: Reserved */ + __RW uint32_t PDI_AL_EVT_MSK; /* 0x204: PDI AL Event Mask */ + __R uint8_t RESERVED15[8]; /* 0x208 - 0x20F: Reserved */ + __R uint16_t ECAT_EVT_REQ; /* 0x210: ECAT Event Request */ + __R uint8_t RESERVED16[14]; /* 0x212 - 0x21F: Reserved */ + __R uint32_t AL_EVT_REQ; /* 0x220: AL Event Request */ + __R uint8_t RESERVED17[220]; /* 0x224 - 0x2FF: Reserved */ + __R uint16_t RX_ERR_CNT[4]; /* 0x300 - 0x306: RX Error Counter */ + __R uint8_t FWD_RX_ERR_CNT[4]; /* 0x308 - 0x30B: Forwarded RX Error Counter */ + __R uint8_t ECAT_PU_ERR_CNT; /* 0x30C: ECAT Processing Unit Error Counter */ + __R uint8_t PDI_ERR_CNT; /* 0x30D: PDI Error Counter */ + __R uint8_t RESERVED18[2]; /* 0x30E - 0x30F: Reserved */ + __R uint8_t LOST_LINK_CNT[4]; /* 0x310 - 0x313: Lost Link Counter */ + __R uint8_t RESERVED19[236]; /* 0x314 - 0x3FF: Reserved */ + __R uint16_t WDG_DIV; /* 0x400: Watchdog Divider */ + __R uint8_t RESERVED20[14]; /* 0x402 - 0x40F: Reserved */ + __R uint16_t WDG_TIME_PDI; /* 0x410: Watchdog Time PDI */ + __R uint8_t RESERVED21[14]; /* 0x412 - 0x41F: Reserved */ + __R uint16_t WDG_TIME_PDAT; /* 0x420: Watchdog Time Process Data */ + __R uint8_t RESERVED22[30]; /* 0x422 - 0x43F: Reserved */ + __RW uint16_t WDG_STAT_PDAT; /* 0x440: Watchdog Status Process Data */ + __R uint8_t WDG_CNT_PDAT; /* 0x442: Watchdog Counter Process Data */ + __R uint8_t WDG_CNT_PDI; /* 0x443: Watchdog Counter PDI */ + __R uint8_t RESERVED23[188]; /* 0x444 - 0x4FF: Reserved */ + __R uint8_t EEPROM_CFG; /* 0x500: EEPROM Configuration */ + __RW uint8_t EEPROM_PDI_ACC_STAT; /* 0x501: EEPROM PDI Access State */ + __RW uint16_t EEPROM_CTRL_STAT; /* 0x502: EEPROM Control/Status */ + __RW uint32_t EEPROM_ADDR; /* 0x504: EEPROM Address */ + __RW uint64_t EEPROM_DATA; /* 0x508: EEPROM Data */ + __RW uint16_t MII_MNG_CS; /* 0x510: MII Management Control/Status */ + __RW uint8_t PHY_ADDR; /* 0x512: PHY Address */ + __RW uint8_t PHY_REG_ADDR; /* 0x513: PHY Register Address */ + __RW uint16_t PHY_DATA; /* 0x514: PHY Data */ + __R uint8_t MIIM_ECAT_ACC_STAT; /* 0x516: MII Management ECAT Access State */ + __RW uint8_t MIIM_PDI_ACC_STAT; /* 0x517: MII Management PDI Access State */ + __RW uint8_t PHY_STAT[4]; /* 0x518 - 0x51B: PHY Port */ + __R uint8_t RESERVED24[228]; /* 0x51C - 0x5FF: Reserved */ + struct { + __R uint32_t LOGIC_START_ADDR; /* 0x600: Logical Start Address */ + __R uint16_t LENGTH; /* 0x604: Length */ + __R uint8_t LOGIC_START_BIT; /* 0x606: Logical Start Bit */ + __R uint8_t LOGIC_STOP_BIT; /* 0x607: Logical Stop Bit */ + __R uint16_t PHYSICAL_START_ADDR; /* 0x608: Physical Start Address */ + __R uint8_t PHYSICAL_START_BIT; /* 0x60A: Physical Start Bit */ + __R uint8_t TYPE; /* 0x60B: Type */ + __R uint8_t ACTIVATE; /* 0x60C: Activate */ + __R uint8_t RESERVED0[3]; /* 0x60D - 0x60F: Reserved */ + } FMMU[8]; + __R uint8_t RESERVED25[384]; /* 0x680 - 0x7FF: Reserved */ + struct { + __R uint16_t PHYSICAL_START_ADDR; /* 0x800: Physical Start Address */ + __R uint16_t LENGTH; /* 0x802: Length */ + __R uint8_t CONTROL; /* 0x804: Control */ + __R uint8_t STATUS; /* 0x805: Status */ + __RW uint8_t ACTIVATE; /* 0x806: Activate */ + __RW uint8_t PDI_CTRL; /* 0x807: PDI Control */ + } SYNCM[8]; + __R uint8_t RESERVED26[192]; /* 0x840 - 0x8FF: Reserved */ + __R uint32_t RCV_TIME[4]; /* 0x900 - 0x90C: Receive Time */ + __RW uint64_t SYS_TIME; /* 0x910: System Time */ + __R uint64_t RCVT_ECAT_PU; /* 0x918: Receive Time ECAT Processing Unit */ + __RW uint64_t SYS_TIME_OFFSET; /* 0x920: System Time Offset */ + __RW uint32_t SYS_TIME_DELAY; /* 0x928: System Time Delay */ + __R uint32_t SYS_TIME_DIFF; /* 0x92C: System Time Difference */ + __RW uint16_t SPD_CNT_START; /* 0x930: Speed Counter Start */ + __R uint16_t SPD_CNT_DIFF; /* 0x932: Speed Counter Diff */ + __RW uint8_t SYS_TIME_DIFF_FD; /* 0x934: System Time Difference Filter Depth */ + __RW uint8_t SPD_CNT_FD; /* 0x935: Speed Counter Filter Depth */ + __R uint8_t RCV_TIME_LM; /* 0x936: Receive Time Latch Mode */ + __R uint8_t RESERVED27[73]; /* 0x937 - 0x97F: Reserved */ + __R uint8_t CYC_UNIT_CTRL; /* 0x980: Cyclic Unit Control */ + __RW uint8_t SYNCO_ACT; /* 0x981: SYNC Out Unit Activation */ + __R uint16_t PULSE_LEN; /* 0x982: Pulse Length of SyncSignals */ + __R uint8_t ACT_STAT; /* 0x984: Activation Status */ + __R uint8_t RESERVED28[9]; /* 0x985 - 0x98D: Reserved */ + __RW uint8_t SYNC0_STAT; /* 0x98E: SYNC0 Status */ + __RW uint8_t SYNC1_STAT; /* 0x98F: SYNC1 Status */ + __RW uint64_t START_TIME_CO; /* 0x990: Start Time Cyclic Operation */ + __R uint64_t NXT_SYNC1_PULSE; /* 0x998: Next SYNC1 Pulse */ + __RW uint32_t SYNC0_CYC_TIME; /* 0x9A0: SYNC0 Cycle Time */ + __RW uint32_t SYNC1_CYC_TIME; /* 0x9A4: SYNC1 Cycle Time */ + __RW uint8_t LATCH0_CTRL; /* 0x9A8: Latch0 Control */ + __RW uint8_t LATCH1_CTRL; /* 0x9A9: Latch1 Control */ + __R uint8_t RESERVED29[4]; /* 0x9AA - 0x9AD: Reserved */ + __R uint8_t LATCH0_STAT; /* 0x9AE: Latch0 Status */ + __R uint8_t LATCH1_STAT; /* 0x9AF: Latch1 Status */ + __RW uint64_t LATCH0_TIME_PE; /* 0x9B0: Latch0 Time Positive Edge */ + __RW uint64_t LATCH0_TIME_NE; /* 0x9B8: Latch0 Time Negative Edge */ + __RW uint64_t LATCH1_TIME_PE; /* 0x9C0: Latch1 Time Positive Edge */ + __RW uint64_t LATCH1_TIME_NE; /* 0x9C8: Latch1 Time Negative Edge */ + __R uint8_t RESERVED30[32]; /* 0x9D0 - 0x9EF: Reserved */ + __R uint32_t ECAT_BUF_CET; /* 0x9F0: EtherCAT Buffer Change Event Time */ + __R uint8_t RESERVED31[4]; /* 0x9F4 - 0x9F7: Reserved */ + __R uint32_t PDI_BUF_SET; /* 0x9F8: PDI Buffer Start Event Time */ + __R uint32_t PDI_BUF_CET; /* 0x9FC: PDI Buffer Change Event Time */ + __R uint8_t RESERVED32[1024]; /* 0xA00 - 0xDFF: Reserved */ + __R uint64_t PID; /* 0xE00: Product ID */ + __R uint64_t VID; /* 0xE08: Vendor ID */ + __R uint8_t RESERVED33[240]; /* 0xE10 - 0xEFF: Reserved */ + __R uint32_t DIO_OUT_DATA; /* 0xF00: Digital I/O Output Data */ + __R uint8_t RESERVED34[12]; /* 0xF04 - 0xF0F: Reserved */ + __RW uint64_t GPO; /* 0xF10: General Purpose Outputs */ + __R uint64_t GPI; /* 0xF18: General Purpose Inputs */ + __R uint8_t RESERVED35[96]; /* 0xF20 - 0xF7F: Reserved */ + __RW uint8_t USER_RAM_BYTE0; /* 0xF80: User Ram Byte 0 */ + __RW uint8_t USER_RAM_BYTE1; /* 0xF81: User Ram Byte 1 */ + __RW uint8_t USER_RAM_BYTE2; /* 0xF82: User Ram Byte 2 */ + __RW uint8_t USER_RAM_BYTE3; /* 0xF83: User Ram Byte 3 */ + __RW uint8_t USER_RAM_BYTE4; /* 0xF84: User Ram Byte 4 */ + __RW uint8_t USER_RAM_BYTE5; /* 0xF85: User Ram Byte 5 */ + __RW uint8_t USER_RAM_BYTE6; /* 0xF86: User Ram Byte 6 */ + __RW uint8_t USER_RAM_BYTE7; /* 0xF87: User Ram Byte 7 */ + __RW uint8_t USER_RAM_BYTE8; /* 0xF88: User Ram Byte 8 */ + __RW uint8_t USER_RAM_BYTE9; /* 0xF89: User Ram Byte 9 */ + __RW uint8_t USER_RAM_BYTE10; /* 0xF8A: User Ram Byte 10 */ + __RW uint8_t USER_RAM_BYTE11; /* 0xF8B: User Ram Byte 11 */ + __R uint8_t RESERVED36[2]; /* 0xF8C - 0xF8D: Reserved */ + __RW uint8_t USER_RAM_BYTE14; /* 0xF8E: User Ram Byte 14 */ + __RW uint8_t USER_RAM_BYTE15; /* 0xF8F: User Ram Byte 15 */ + __R uint8_t RESERVED37[3]; /* 0xF90 - 0xF92: Reserved */ + __RW uint8_t USER_RAM_BYTE19; /* 0xF93: User Ram Byte 19 */ + __R uint8_t RESERVED38[108]; /* 0xF94 - 0xFFF: Reserved */ + __RW uint32_t PDRAM; /* 0x1000: Process Data Ram */ + __R uint8_t RESERVED39[61436]; /* 0x1004 - 0xFFFF: Reserved */ + __RW uint32_t PDRAM_ALS; /* 0x10000: Process Data Ram Alias */ + __R uint8_t RESERVED40[61436]; /* 0x10004 - 0x1EFFF: Reserved */ + __RW uint32_t GPR_CFG0; /* 0x1F000: General Purpose Configure 0 */ + __RW uint32_t GPR_CFG1; /* 0x1F004: General Purpose Configure 1 */ + __RW uint32_t GPR_CFG2; /* 0x1F008: General Purpose Configure 2 */ + __R uint8_t RESERVED41[4]; /* 0x1F00C - 0x1F00F: Reserved */ + __RW uint32_t PHY_CFG0; /* 0x1F010: PHY Configure 0 */ + __RW uint32_t PHY_CFG1; /* 0x1F014: PHY Configure 1 */ + __R uint8_t RESERVED42[8]; /* 0x1F018 - 0x1F01F: Reserved */ + __RW uint32_t GPIO_CTRL; /* 0x1F020: GPIO Output Enable */ + __R uint8_t RESERVED43[12]; /* 0x1F024 - 0x1F02F: Reserved */ + __RW uint32_t GPI_OVERRIDE0; /* 0x1F030: GPI low word Override value */ + __RW uint32_t GPI_OVERRIDE1; /* 0x1F034: GPI high word Override value */ + __R uint32_t GPO_REG0; /* 0x1F038: GPO low word read value */ + __R uint32_t GPO_REG1; /* 0x1F03C: GPO high word read value */ + __R uint32_t GPI_REG0; /* 0x1F040: GPI low word read value */ + __R uint32_t GPI_REG1; /* 0x1F044: GPI high word read value */ + __R uint8_t RESERVED44[24]; /* 0x1F048 - 0x1F05F: Reserved */ + __R uint32_t GPR_STATUS; /* 0x1F060: global status register */ + __R uint8_t RESERVED45[28]; /* 0x1F064 - 0x1F07F: Reserved */ + __RW uint32_t IO_CFG[9]; /* 0x1F080 - 0x1F0A0: CTR IO Configure */ +} ESC_t; + +#define ESCREG_BASE (0x00000000UL) /* Base address of ESC peripheral */ +#define ESCREG ((ESC_t *) ESCREG_BASE) /* Pointer to ESC peripheral */ +#define ESCREG_OF(n) ((size_t)&(n)) /* offset of ESC peripheral */ + +/* Bitfield definition for register: TYPE */ +/* + * TYPE (RO) + * + * Controller type + */ +#define ESC_TYPE_TYPE_MASK (0xFFU) +#define ESC_TYPE_TYPE_SHIFT (0U) +#define ESC_TYPE_TYPE_GET(x) (((uint8_t)(x) & ESC_TYPE_TYPE_MASK) >> ESC_TYPE_TYPE_SHIFT) + +/* Bitfield definition for register: REVISION */ +/* + * X (RO) + * + * major version X + */ +#define ESC_REVISION_X_MASK (0xFFU) +#define ESC_REVISION_X_SHIFT (0U) +#define ESC_REVISION_X_GET(x) (((uint8_t)(x) & ESC_REVISION_X_MASK) >> ESC_REVISION_X_SHIFT) + +/* Bitfield definition for register: BUILD */ +/* + * BUILD (RO) + * + */ +#define ESC_BUILD_BUILD_MASK (0xFF00U) +#define ESC_BUILD_BUILD_SHIFT (8U) +#define ESC_BUILD_BUILD_GET(x) (((uint16_t)(x) & ESC_BUILD_BUILD_MASK) >> ESC_BUILD_BUILD_SHIFT) + +/* + * Y (RO) + * + * minor version Y + */ +#define ESC_BUILD_Y_MASK (0xF0U) +#define ESC_BUILD_Y_SHIFT (4U) +#define ESC_BUILD_Y_GET(x) (((uint16_t)(x) & ESC_BUILD_Y_MASK) >> ESC_BUILD_Y_SHIFT) + +/* + * Z (RO) + * + * maintenance version Z + */ +#define ESC_BUILD_Z_MASK (0xFU) +#define ESC_BUILD_Z_SHIFT (0U) +#define ESC_BUILD_Z_GET(x) (((uint16_t)(x) & ESC_BUILD_Z_MASK) >> ESC_BUILD_Z_SHIFT) + +/* Bitfield definition for register: FMMU_NUM */ +/* + * NUM (RO) + * + * Number of supported FMMU channels (or entities) + */ +#define ESC_FMMU_NUM_NUM_MASK (0xFFU) +#define ESC_FMMU_NUM_NUM_SHIFT (0U) +#define ESC_FMMU_NUM_NUM_GET(x) (((uint8_t)(x) & ESC_FMMU_NUM_NUM_MASK) >> ESC_FMMU_NUM_NUM_SHIFT) + +/* Bitfield definition for register: SYNCM_NUM */ +/* + * NUM (RO) + * + * Number of supported SyncManager channels (or entities) + */ +#define ESC_SYNCM_NUM_NUM_MASK (0xFFU) +#define ESC_SYNCM_NUM_NUM_SHIFT (0U) +#define ESC_SYNCM_NUM_NUM_GET(x) (((uint8_t)(x) & ESC_SYNCM_NUM_NUM_MASK) >> ESC_SYNCM_NUM_NUM_SHIFT) + +/* Bitfield definition for register: RAM_SIZE */ +/* + * SIZE (RO) + * + * Process Data RAM size supported in KByte + */ +#define ESC_RAM_SIZE_SIZE_MASK (0xFFU) +#define ESC_RAM_SIZE_SIZE_SHIFT (0U) +#define ESC_RAM_SIZE_SIZE_GET(x) (((uint8_t)(x) & ESC_RAM_SIZE_SIZE_MASK) >> ESC_RAM_SIZE_SIZE_SHIFT) + +/* Bitfield definition for register: PORT_DESC */ +/* + * PORT3 (RO) + * + * Port configuration: + * 00:Not implemented + * 01:Not configured (SII EEPROM) + * 10:EBUS + * 11:MII/RMII/RGMII + */ +#define ESC_PORT_DESC_PORT3_MASK (0xC0U) +#define ESC_PORT_DESC_PORT3_SHIFT (6U) +#define ESC_PORT_DESC_PORT3_GET(x) (((uint8_t)(x) & ESC_PORT_DESC_PORT3_MASK) >> ESC_PORT_DESC_PORT3_SHIFT) + +/* + * PORT2 (RO) + * + * Port configuration: + * 00:Not implemented + * 01:Not configured (SII EEPROM) + * 10:EBUS + * 11:MII/RMII/RGMII + */ +#define ESC_PORT_DESC_PORT2_MASK (0x30U) +#define ESC_PORT_DESC_PORT2_SHIFT (4U) +#define ESC_PORT_DESC_PORT2_GET(x) (((uint8_t)(x) & ESC_PORT_DESC_PORT2_MASK) >> ESC_PORT_DESC_PORT2_SHIFT) + +/* + * PORT1 (RO) + * + * Port configuration: + * 00:Not implemented + * 01:Not configured (SII EEPROM) + * 10:EBUS + * 11:MII/RMII/RGMII + */ +#define ESC_PORT_DESC_PORT1_MASK (0xCU) +#define ESC_PORT_DESC_PORT1_SHIFT (2U) +#define ESC_PORT_DESC_PORT1_GET(x) (((uint8_t)(x) & ESC_PORT_DESC_PORT1_MASK) >> ESC_PORT_DESC_PORT1_SHIFT) + +/* + * PORT0 (RO) + * + * Port configuration: + * 00:Not implemented + * 01:Not configured (SII EEPROM) + * 10:EBUS + * 11:MII/RMII/RGMII + */ +#define ESC_PORT_DESC_PORT0_MASK (0x3U) +#define ESC_PORT_DESC_PORT0_SHIFT (0U) +#define ESC_PORT_DESC_PORT0_GET(x) (((uint8_t)(x) & ESC_PORT_DESC_PORT0_MASK) >> ESC_PORT_DESC_PORT0_SHIFT) + +/* Bitfield definition for register: FEATURE */ +/* + * FFSC (RO) + * + * Fixed FMMU/SyncManager configuration: + * 0:Variable configuration + * 1:Fixed configuration (refer to documentation of supporting ESCs) + */ +#define ESC_FEATURE_FFSC_MASK (0x800U) +#define ESC_FEATURE_FFSC_SHIFT (11U) +#define ESC_FEATURE_FFSC_GET(x) (((uint16_t)(x) & ESC_FEATURE_FFSC_MASK) >> ESC_FEATURE_FFSC_SHIFT) + +/* + * RWC (RO) + * + * EtherCAT read/write command support(BRW,APRW,FPRW): + * 0:Supported + * 1:Not supported + */ +#define ESC_FEATURE_RWC_MASK (0x400U) +#define ESC_FEATURE_RWC_SHIFT (10U) +#define ESC_FEATURE_RWC_GET(x) (((uint16_t)(x) & ESC_FEATURE_RWC_MASK) >> ESC_FEATURE_RWC_SHIFT) + +/* + * LRW (RO) + * + * EtherCAT LRW command support: + * 0:Supported + * 1:Not supported + */ +#define ESC_FEATURE_LRW_MASK (0x200U) +#define ESC_FEATURE_LRW_SHIFT (9U) +#define ESC_FEATURE_LRW_GET(x) (((uint16_t)(x) & ESC_FEATURE_LRW_MASK) >> ESC_FEATURE_LRW_SHIFT) + +/* + * EDSA (RO) + * + * Enhanced DC SYNC Activation: + * 0:Not available + * 1:Available + * Note:This feature refers to registers 0x981[7:3] and 0x0984 + */ +#define ESC_FEATURE_EDSA_MASK (0x100U) +#define ESC_FEATURE_EDSA_SHIFT (8U) +#define ESC_FEATURE_EDSA_GET(x) (((uint16_t)(x) & ESC_FEATURE_EDSA_MASK) >> ESC_FEATURE_EDSA_SHIFT) + +/* + * SHFE (RO) + * + * Seperate Handling of FCS Errors: + * 0:Not supported + * 1:Supported, frames with wrong FCS and additional nibble will be counted separately in Forwarded RX Error Counter + */ +#define ESC_FEATURE_SHFE_MASK (0x80U) +#define ESC_FEATURE_SHFE_SHIFT (7U) +#define ESC_FEATURE_SHFE_GET(x) (((uint16_t)(x) & ESC_FEATURE_SHFE_MASK) >> ESC_FEATURE_SHFE_SHIFT) + +/* + * ELDM (RO) + * + * Enhanced Link Detection MII: + * 0:Not available + * 1:Available + */ +#define ESC_FEATURE_ELDM_MASK (0x40U) +#define ESC_FEATURE_ELDM_SHIFT (6U) +#define ESC_FEATURE_ELDM_GET(x) (((uint16_t)(x) & ESC_FEATURE_ELDM_MASK) >> ESC_FEATURE_ELDM_SHIFT) + +/* + * DCW (RO) + * + * Distributed Clocks width: + * 0:32 bit + * 1:64 bit + */ +#define ESC_FEATURE_DCW_MASK (0x8U) +#define ESC_FEATURE_DCW_SHIFT (3U) +#define ESC_FEATURE_DCW_GET(x) (((uint16_t)(x) & ESC_FEATURE_DCW_MASK) >> ESC_FEATURE_DCW_SHIFT) + +/* + * DC (RO) + * + * Distributed Clocks: + * 0:Not available + * 1:Available + */ +#define ESC_FEATURE_DC_MASK (0x4U) +#define ESC_FEATURE_DC_SHIFT (2U) +#define ESC_FEATURE_DC_GET(x) (((uint16_t)(x) & ESC_FEATURE_DC_MASK) >> ESC_FEATURE_DC_SHIFT) + +/* + * FMMU (RO) + * + * FMMU Operation: + * 0:Bit oriented + * 1:Byte oriented + */ +#define ESC_FEATURE_FMMU_MASK (0x1U) +#define ESC_FEATURE_FMMU_SHIFT (0U) +#define ESC_FEATURE_FMMU_GET(x) (((uint16_t)(x) & ESC_FEATURE_FMMU_MASK) >> ESC_FEATURE_FMMU_SHIFT) + +/* Bitfield definition for register: STATION_ADDR */ +/* + * ADDR (RO) + * + * Address used for node addressing + * (FPRD/FPWR/FPRW/FRMW commands) + */ +#define ESC_STATION_ADDR_ADDR_MASK (0xFFFFU) +#define ESC_STATION_ADDR_ADDR_SHIFT (0U) +#define ESC_STATION_ADDR_ADDR_GET(x) (((uint16_t)(x) & ESC_STATION_ADDR_ADDR_MASK) >> ESC_STATION_ADDR_ADDR_SHIFT) + +/* Bitfield definition for register: STATION_ALS */ +/* + * ADDR (RW) + * + * Alias Address used for node addressing + * (FPRD/FPWR/FPRW/FRMW commands). + * The use of this alias is activated by Register + * DL Control Bit 0x0100[24]. + * NOTE:EEPROM value is only transferred into this + * register at first EEPROM load after power-on or + * reset. + * ESC20 exception:EEPROM value is transferred + * into this register after each EEPROM reload + * command. + */ +#define ESC_STATION_ALS_ADDR_MASK (0xFFFFU) +#define ESC_STATION_ALS_ADDR_SHIFT (0U) +#define ESC_STATION_ALS_ADDR_SET(x) (((uint16_t)(x) << ESC_STATION_ALS_ADDR_SHIFT) & ESC_STATION_ALS_ADDR_MASK) +#define ESC_STATION_ALS_ADDR_GET(x) (((uint16_t)(x) & ESC_STATION_ALS_ADDR_MASK) >> ESC_STATION_ALS_ADDR_SHIFT) + +/* Bitfield definition for register: REG_WEN */ +/* + * EN (RO) + * + * If register write protection is enabled, this + * register has to be written in the same + * Ethernet frame (value does not matter) + * before other writes to this station are allowed. + * This bit is self-clearing at the beginning of the + * next frame (SOF), or if Register Write + * Protection is disabled. + */ +#define ESC_REG_WEN_EN_MASK (0x1U) +#define ESC_REG_WEN_EN_SHIFT (0U) +#define ESC_REG_WEN_EN_GET(x) (((uint8_t)(x) & ESC_REG_WEN_EN_MASK) >> ESC_REG_WEN_EN_SHIFT) + +/* Bitfield definition for register: REG_WP */ +/* + * WP (RO) + * + * Register write protection: + * 0:Protection disabled + * 1:Protection enabled + * Registers 0x0000:0x0F7F are write-protected, + * except for 0x0020 and 0x0030 + */ +#define ESC_REG_WP_WP_MASK (0x1U) +#define ESC_REG_WP_WP_SHIFT (0U) +#define ESC_REG_WP_WP_GET(x) (((uint8_t)(x) & ESC_REG_WP_WP_MASK) >> ESC_REG_WP_WP_SHIFT) + +/* Bitfield definition for register: ESC_WEN */ +/* + * EN (RO) + * + * If ESC write protection is enabled, this + * register has to be written in the same + * Ethernet frame (value does not matter) + * before other writes to this station are allowed. + * This bit is self-clearing at the beginning of the + * next frame (SOF), or if ESC Write Protection + * is disabled. + */ +#define ESC_ESC_WEN_EN_MASK (0x1U) +#define ESC_ESC_WEN_EN_SHIFT (0U) +#define ESC_ESC_WEN_EN_GET(x) (((uint8_t)(x) & ESC_ESC_WEN_EN_MASK) >> ESC_ESC_WEN_EN_SHIFT) + +/* Bitfield definition for register: ESC_WP */ +/* + * WP (RO) + * + * Write protect: + * 0:Protection disabled + * 1:Protection enabled + * All areas are write-protected, except for 0x0030. + */ +#define ESC_ESC_WP_WP_MASK (0x1U) +#define ESC_ESC_WP_WP_SHIFT (0U) +#define ESC_ESC_WP_WP_GET(x) (((uint8_t)(x) & ESC_ESC_WP_WP_MASK) >> ESC_ESC_WP_WP_SHIFT) + +/* Bitfield definition for register: ESC_RST_ECAT */ +/* + * PR (RO) + * + * Progress of the reset procedure: + * 00:initial/reset state + * 01:after writing 0x52 ('R'), when previous + * state was 00 + * 10:after writing 0x45 ('E'), when previous + * state was 01 + * 11:after writing 0x53 ('S'), when previous + * state was 10. + * This value must not be observed + * because the ESC enters reset when this + * state is reached, resulting in state 00 + */ +#define ESC_ESC_RST_ECAT_PR_MASK (0x3U) +#define ESC_ESC_RST_ECAT_PR_SHIFT (0U) +#define ESC_ESC_RST_ECAT_PR_GET(x) (((uint8_t)(x) & ESC_ESC_RST_ECAT_PR_MASK) >> ESC_ESC_RST_ECAT_PR_SHIFT) + +/* Bitfield definition for register: ESC_RST_PDI */ +/* + * RST (RW) + * + * A reset is asserted after writing the reset + * sequence 0x52 ('R'), 0x45 ('E') and 0x53 ('S') + * in this register with 3 consecutive commands. + * Any other command which does not continue + * the sequence by writing the next expected + * value will cancel the reset procedure + */ +#define ESC_ESC_RST_PDI_RST_MASK (0xFFU) +#define ESC_ESC_RST_PDI_RST_SHIFT (0U) +#define ESC_ESC_RST_PDI_RST_SET(x) (((uint8_t)(x) << ESC_ESC_RST_PDI_RST_SHIFT) & ESC_ESC_RST_PDI_RST_MASK) +#define ESC_ESC_RST_PDI_RST_GET(x) (((uint8_t)(x) & ESC_ESC_RST_PDI_RST_MASK) >> ESC_ESC_RST_PDI_RST_SHIFT) + +/* Bitfield definition for register: ESC_DL_CTRL */ +/* + * SA (RO) + * + * Station alias: + * 0:Ignore Station Alias + * 1:Alias can be used for all configured + * address comm + */ +#define ESC_ESC_DL_CTRL_SA_MASK (0x1000000UL) +#define ESC_ESC_DL_CTRL_SA_SHIFT (24U) +#define ESC_ESC_DL_CTRL_SA_GET(x) (((uint32_t)(x) & ESC_ESC_DL_CTRL_SA_MASK) >> ESC_ESC_DL_CTRL_SA_SHIFT) + +/* + * RFS (RO) + * + * RX FIFO Size (ESC delays start of + * forwarding until FIFO is at least half full). + * RX FIFO Size/RX delay reduction** : + * Value:EBUS:MII: + * 0:-50 ns -40 ns (-80 ns***) + * 1:-40 ns -40 ns (-80 ns***) + * 2:-30 ns -40 ns + * 3:-20 ns -40 ns + * 4:-10 ns no change + * 5:no change no change + * 6:no change no change + * 7:default default + * NOTE:EEPROM value is only taken over at first + * EEPROM load after power-on or reset + */ +#define ESC_ESC_DL_CTRL_RFS_MASK (0x70000UL) +#define ESC_ESC_DL_CTRL_RFS_SHIFT (16U) +#define ESC_ESC_DL_CTRL_RFS_GET(x) (((uint32_t)(x) & ESC_ESC_DL_CTRL_RFS_MASK) >> ESC_ESC_DL_CTRL_RFS_SHIFT) + +/* + * LP3 (RO) + * + * Loop Port 3: + * 00:Auto + * 01:Auto Close + * 10:Open + * 11:Closed + */ +#define ESC_ESC_DL_CTRL_LP3_MASK (0xC000U) +#define ESC_ESC_DL_CTRL_LP3_SHIFT (14U) +#define ESC_ESC_DL_CTRL_LP3_GET(x) (((uint32_t)(x) & ESC_ESC_DL_CTRL_LP3_MASK) >> ESC_ESC_DL_CTRL_LP3_SHIFT) + +/* + * LP2 (RO) + * + * Loop Port 2: + * 00:Auto + * 01:Auto Close + * 10:Open + * 11:Closed + */ +#define ESC_ESC_DL_CTRL_LP2_MASK (0x3000U) +#define ESC_ESC_DL_CTRL_LP2_SHIFT (12U) +#define ESC_ESC_DL_CTRL_LP2_GET(x) (((uint32_t)(x) & ESC_ESC_DL_CTRL_LP2_MASK) >> ESC_ESC_DL_CTRL_LP2_SHIFT) + +/* + * LP1 (RO) + * + * Loop Port 1: + * 00:Auto + * 01:Auto Close + * 10:Open + * 11:Closed + */ +#define ESC_ESC_DL_CTRL_LP1_MASK (0xC00U) +#define ESC_ESC_DL_CTRL_LP1_SHIFT (10U) +#define ESC_ESC_DL_CTRL_LP1_GET(x) (((uint32_t)(x) & ESC_ESC_DL_CTRL_LP1_MASK) >> ESC_ESC_DL_CTRL_LP1_SHIFT) + +/* + * LP0 (RO) + * + * Loop Port 0: + * 00:Auto + * 01:Auto Close + * 10:Open + * 11:Closed + * NOTE: + * Loop open means sending/receiving over this port + * is enabled, loop closed means sending/receiving + * is disabled and frames are forwarded to the next + * open port internally. + * Auto:loop closed at link down, opened at link up + * Auto Close:loop closed at link down, opened with + * writing 01 again after link up (or receiving a valid + * Ethernet frame at the closed port) + * Open:loop open regardless of link state + * Closed:loop closed regardless of link state + */ +#define ESC_ESC_DL_CTRL_LP0_MASK (0x300U) +#define ESC_ESC_DL_CTRL_LP0_SHIFT (8U) +#define ESC_ESC_DL_CTRL_LP0_GET(x) (((uint32_t)(x) & ESC_ESC_DL_CTRL_LP0_MASK) >> ESC_ESC_DL_CTRL_LP0_SHIFT) + +/* + * TU (RO) + * + * Temporary use of settings in + * 0x0100:0x0103[8:15]: + * 0:permanent use + * 1:use for about 1 second, then revert to + * previous settings + */ +#define ESC_ESC_DL_CTRL_TU_MASK (0x2U) +#define ESC_ESC_DL_CTRL_TU_SHIFT (1U) +#define ESC_ESC_DL_CTRL_TU_GET(x) (((uint32_t)(x) & ESC_ESC_DL_CTRL_TU_MASK) >> ESC_ESC_DL_CTRL_TU_SHIFT) + +/* + * FR (RO) + * + * Forwarding rule: + * 0:Forward non-EtherCAT frames: + * EtherCAT frames are processed, + * non-EtherCAT frames are forwarded + * without processing or modification. + * The source MAC address is not + * changed for any frame. + * 1:Destroy non-EtherCAT frames: + * EtherCAT frames are processed, non-EtherCAT frames are destroyed. + * The source MAC address is changed by + * the Processing Unit for every frame + * (SOURCE_MAC[1] is set + */ +#define ESC_ESC_DL_CTRL_FR_MASK (0x1U) +#define ESC_ESC_DL_CTRL_FR_SHIFT (0U) +#define ESC_ESC_DL_CTRL_FR_GET(x) (((uint32_t)(x) & ESC_ESC_DL_CTRL_FR_MASK) >> ESC_ESC_DL_CTRL_FR_SHIFT) + +/* Bitfield definition for register: PHYSICAL_RW_OFFSET */ +/* + * OFFSET (RO) + * + * This register is used for ReadWrite + * commands in Device Addressing mode + * (FPRW, APRW, BRW). + * The internal read address is directly taken + * from the offset address field of the EtherCAT + * datagram header, while the internal write + * address is calculated by adding the Physical + * Read/Write Offset value to the offset address + * field. + * Internal read address = ADR, + * internal write address = ADR + R/W-Offset + */ +#define ESC_PHYSICAL_RW_OFFSET_OFFSET_MASK (0xFFFFU) +#define ESC_PHYSICAL_RW_OFFSET_OFFSET_SHIFT (0U) +#define ESC_PHYSICAL_RW_OFFSET_OFFSET_GET(x) (((uint16_t)(x) & ESC_PHYSICAL_RW_OFFSET_OFFSET_MASK) >> ESC_PHYSICAL_RW_OFFSET_OFFSET_SHIFT) + +/* Bitfield definition for register: ESC_DL_STAT */ +/* + * CP3 (RO) + * + * Communication on Port 3: + * 0:No stable communication + * 1:Communication established + */ +#define ESC_ESC_DL_STAT_CP3_MASK (0x8000U) +#define ESC_ESC_DL_STAT_CP3_SHIFT (15U) +#define ESC_ESC_DL_STAT_CP3_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_CP3_MASK) >> ESC_ESC_DL_STAT_CP3_SHIFT) + +/* + * LP3 (RO) + * + * Loop Port 3: + * 0:Open + * 1:Closed + */ +#define ESC_ESC_DL_STAT_LP3_MASK (0x4000U) +#define ESC_ESC_DL_STAT_LP3_SHIFT (14U) +#define ESC_ESC_DL_STAT_LP3_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_LP3_MASK) >> ESC_ESC_DL_STAT_LP3_SHIFT) + +/* + * CP2 (RO) + * + * Communication on Port 2: + * 0:No stable communication + * 1:Communication established + */ +#define ESC_ESC_DL_STAT_CP2_MASK (0x2000U) +#define ESC_ESC_DL_STAT_CP2_SHIFT (13U) +#define ESC_ESC_DL_STAT_CP2_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_CP2_MASK) >> ESC_ESC_DL_STAT_CP2_SHIFT) + +/* + * LP2 (RO) + * + * Loop Port 2: + * 0:Open + * 1:Closed + */ +#define ESC_ESC_DL_STAT_LP2_MASK (0x1000U) +#define ESC_ESC_DL_STAT_LP2_SHIFT (12U) +#define ESC_ESC_DL_STAT_LP2_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_LP2_MASK) >> ESC_ESC_DL_STAT_LP2_SHIFT) + +/* + * CP1 (RO) + * + * Communication on Port 1: + * 0:No stable communication + * 1:Communication established + */ +#define ESC_ESC_DL_STAT_CP1_MASK (0x800U) +#define ESC_ESC_DL_STAT_CP1_SHIFT (11U) +#define ESC_ESC_DL_STAT_CP1_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_CP1_MASK) >> ESC_ESC_DL_STAT_CP1_SHIFT) + +/* + * LP1 (RO) + * + * Loop Port 1: + * 0:Open + * 1:Closed + */ +#define ESC_ESC_DL_STAT_LP1_MASK (0x400U) +#define ESC_ESC_DL_STAT_LP1_SHIFT (10U) +#define ESC_ESC_DL_STAT_LP1_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_LP1_MASK) >> ESC_ESC_DL_STAT_LP1_SHIFT) + +/* + * CP0 (RO) + * + * Communication on Port 0: + * 0:No stable communication + * 1:Communication established + */ +#define ESC_ESC_DL_STAT_CP0_MASK (0x200U) +#define ESC_ESC_DL_STAT_CP0_SHIFT (9U) +#define ESC_ESC_DL_STAT_CP0_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_CP0_MASK) >> ESC_ESC_DL_STAT_CP0_SHIFT) + +/* + * LP0 (RO) + * + * Loop Port 0: + * 0:Open + * 1:Closed + */ +#define ESC_ESC_DL_STAT_LP0_MASK (0x100U) +#define ESC_ESC_DL_STAT_LP0_SHIFT (8U) +#define ESC_ESC_DL_STAT_LP0_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_LP0_MASK) >> ESC_ESC_DL_STAT_LP0_SHIFT) + +/* + * PLP3 (RO) + * + * Physical link on Port 3: + * 0:No link + * 1:Link detected + */ +#define ESC_ESC_DL_STAT_PLP3_MASK (0x80U) +#define ESC_ESC_DL_STAT_PLP3_SHIFT (7U) +#define ESC_ESC_DL_STAT_PLP3_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_PLP3_MASK) >> ESC_ESC_DL_STAT_PLP3_SHIFT) + +/* + * PLP2 (RO) + * + * Physical link on Port 2: + * 0:No link + * 1:Link detected + */ +#define ESC_ESC_DL_STAT_PLP2_MASK (0x40U) +#define ESC_ESC_DL_STAT_PLP2_SHIFT (6U) +#define ESC_ESC_DL_STAT_PLP2_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_PLP2_MASK) >> ESC_ESC_DL_STAT_PLP2_SHIFT) + +/* + * PLP1 (RO) + * + * Physical link on Port 1: + * 0:No link + * 1:Link detected + */ +#define ESC_ESC_DL_STAT_PLP1_MASK (0x20U) +#define ESC_ESC_DL_STAT_PLP1_SHIFT (5U) +#define ESC_ESC_DL_STAT_PLP1_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_PLP1_MASK) >> ESC_ESC_DL_STAT_PLP1_SHIFT) + +/* + * PLP0 (RO) + * + * Physical link on Port 0: + * 0:No link + * 1:Link detected + */ +#define ESC_ESC_DL_STAT_PLP0_MASK (0x10U) +#define ESC_ESC_DL_STAT_PLP0_SHIFT (4U) +#define ESC_ESC_DL_STAT_PLP0_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_PLP0_MASK) >> ESC_ESC_DL_STAT_PLP0_SHIFT) + +/* + * ELD (RO) + * + * Enhanced Link detection: + * 0:Deactivated for all ports + * 1:Activated for at least one port + * NOTE:EEPROM value is only transferred into this + * register at first EEPROM load after power-on or + * reset + */ +#define ESC_ESC_DL_STAT_ELD_MASK (0x4U) +#define ESC_ESC_DL_STAT_ELD_SHIFT (2U) +#define ESC_ESC_DL_STAT_ELD_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_ELD_MASK) >> ESC_ESC_DL_STAT_ELD_SHIFT) + +/* + * WDS (RO) + * + * PDI Watchdog Status: + * 0:Watchdog expired + * 1:Watchdog reloaded + */ +#define ESC_ESC_DL_STAT_WDS_MASK (0x2U) +#define ESC_ESC_DL_STAT_WDS_SHIFT (1U) +#define ESC_ESC_DL_STAT_WDS_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_WDS_MASK) >> ESC_ESC_DL_STAT_WDS_SHIFT) + +/* + * EPLC (RO) + * + * PDI operational/EEPROM loaded correctly: + * 0:EEPROM not loaded, PDI not + * operational (no access to Process Data + * RAM) + * 1:EEPROM loaded correctly, PDI + * operational (access to Process Data + * RAM) + */ +#define ESC_ESC_DL_STAT_EPLC_MASK (0x1U) +#define ESC_ESC_DL_STAT_EPLC_SHIFT (0U) +#define ESC_ESC_DL_STAT_EPLC_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_EPLC_MASK) >> ESC_ESC_DL_STAT_EPLC_SHIFT) + +/* Bitfield definition for register: AL_CTRL */ +/* + * DI (RW) + * + * Device Identification: + * 0:No request + * 1:Device Identification request + */ +#define ESC_AL_CTRL_DI_MASK (0x20U) +#define ESC_AL_CTRL_DI_SHIFT (5U) +#define ESC_AL_CTRL_DI_SET(x) (((uint16_t)(x) << ESC_AL_CTRL_DI_SHIFT) & ESC_AL_CTRL_DI_MASK) +#define ESC_AL_CTRL_DI_GET(x) (((uint16_t)(x) & ESC_AL_CTRL_DI_MASK) >> ESC_AL_CTRL_DI_SHIFT) + +/* + * EIA (RW) + * + * Error Ind Ack: + * 0:No Ack of Error Ind in AL status register + * 1:Ack of Error Ind in AL status register + */ +#define ESC_AL_CTRL_EIA_MASK (0x10U) +#define ESC_AL_CTRL_EIA_SHIFT (4U) +#define ESC_AL_CTRL_EIA_SET(x) (((uint16_t)(x) << ESC_AL_CTRL_EIA_SHIFT) & ESC_AL_CTRL_EIA_MASK) +#define ESC_AL_CTRL_EIA_GET(x) (((uint16_t)(x) & ESC_AL_CTRL_EIA_MASK) >> ESC_AL_CTRL_EIA_SHIFT) + +/* + * IST (RW) + * + * Initiate State Transition of the Device State + * Machine: + * 1:Request Init State + * 3:Request Bootstrap State + * 2:Request Pre-Operational State + * 4:Request Safe-Operational State + * 8:Request Operational State + */ +#define ESC_AL_CTRL_IST_MASK (0xFU) +#define ESC_AL_CTRL_IST_SHIFT (0U) +#define ESC_AL_CTRL_IST_SET(x) (((uint16_t)(x) << ESC_AL_CTRL_IST_SHIFT) & ESC_AL_CTRL_IST_MASK) +#define ESC_AL_CTRL_IST_GET(x) (((uint16_t)(x) & ESC_AL_CTRL_IST_MASK) >> ESC_AL_CTRL_IST_SHIFT) + +/* Bitfield definition for register: AL_STAT */ +/* + * DI (RW) + * + * Device Identification: + * 0:Device Identification not valid + * 1:Device Identification loaded + */ +#define ESC_AL_STAT_DI_MASK (0x20U) +#define ESC_AL_STAT_DI_SHIFT (5U) +#define ESC_AL_STAT_DI_SET(x) (((uint16_t)(x) << ESC_AL_STAT_DI_SHIFT) & ESC_AL_STAT_DI_MASK) +#define ESC_AL_STAT_DI_GET(x) (((uint16_t)(x) & ESC_AL_STAT_DI_MASK) >> ESC_AL_STAT_DI_SHIFT) + +/* + * EI (RW) + * + * Error Ind: + * 0:Device is in State as requested or Flag + * cleared by command + * 1:Device has not entered requested State + * or changed State as result of a local + * action + */ +#define ESC_AL_STAT_EI_MASK (0x10U) +#define ESC_AL_STAT_EI_SHIFT (4U) +#define ESC_AL_STAT_EI_SET(x) (((uint16_t)(x) << ESC_AL_STAT_EI_SHIFT) & ESC_AL_STAT_EI_MASK) +#define ESC_AL_STAT_EI_GET(x) (((uint16_t)(x) & ESC_AL_STAT_EI_MASK) >> ESC_AL_STAT_EI_SHIFT) + +/* + * AS (RW) + * + * Actual State of the Device State Machine: + * 1:Init State + * 3:Bootstrap State + * 2:Pre-Operational State + * 4:Safe-Operational State + * 8:Operational State + */ +#define ESC_AL_STAT_AS_MASK (0xFU) +#define ESC_AL_STAT_AS_SHIFT (0U) +#define ESC_AL_STAT_AS_SET(x) (((uint16_t)(x) << ESC_AL_STAT_AS_SHIFT) & ESC_AL_STAT_AS_MASK) +#define ESC_AL_STAT_AS_GET(x) (((uint16_t)(x) & ESC_AL_STAT_AS_MASK) >> ESC_AL_STAT_AS_SHIFT) + +/* Bitfield definition for register: AL_STAT_CODE */ +/* + * CODE (RW) + * + * AL Status Code + */ +#define ESC_AL_STAT_CODE_CODE_MASK (0xFFFFU) +#define ESC_AL_STAT_CODE_CODE_SHIFT (0U) +#define ESC_AL_STAT_CODE_CODE_SET(x) (((uint16_t)(x) << ESC_AL_STAT_CODE_CODE_SHIFT) & ESC_AL_STAT_CODE_CODE_MASK) +#define ESC_AL_STAT_CODE_CODE_GET(x) (((uint16_t)(x) & ESC_AL_STAT_CODE_CODE_MASK) >> ESC_AL_STAT_CODE_CODE_SHIFT) + +/* Bitfield definition for register: RUN_LED_OVRD */ +/* + * EN_OVRD (RW) + * + * Enable Override: + * 0:Override disabled + * 1:Override enabled + */ +#define ESC_RUN_LED_OVRD_EN_OVRD_MASK (0x10U) +#define ESC_RUN_LED_OVRD_EN_OVRD_SHIFT (4U) +#define ESC_RUN_LED_OVRD_EN_OVRD_SET(x) (((uint8_t)(x) << ESC_RUN_LED_OVRD_EN_OVRD_SHIFT) & ESC_RUN_LED_OVRD_EN_OVRD_MASK) +#define ESC_RUN_LED_OVRD_EN_OVRD_GET(x) (((uint8_t)(x) & ESC_RUN_LED_OVRD_EN_OVRD_MASK) >> ESC_RUN_LED_OVRD_EN_OVRD_SHIFT) + +/* + * LED_CODE (RW) + * + * LED code: + * 0x0:Off + * 0x1:Flash 1x + * 0x2-0xC:Flash 2x – 12x + * 0xD:Blinking + * 0xE:Flickering + * 0xF:On + */ +#define ESC_RUN_LED_OVRD_LED_CODE_MASK (0xFU) +#define ESC_RUN_LED_OVRD_LED_CODE_SHIFT (0U) +#define ESC_RUN_LED_OVRD_LED_CODE_SET(x) (((uint8_t)(x) << ESC_RUN_LED_OVRD_LED_CODE_SHIFT) & ESC_RUN_LED_OVRD_LED_CODE_MASK) +#define ESC_RUN_LED_OVRD_LED_CODE_GET(x) (((uint8_t)(x) & ESC_RUN_LED_OVRD_LED_CODE_MASK) >> ESC_RUN_LED_OVRD_LED_CODE_SHIFT) + +/* Bitfield definition for register: ERR_LED_OVRD */ +/* + * EN_OVRD (RW) + * + * Enable Override: + * 0:Override disabled + * 1:Override enabled + */ +#define ESC_ERR_LED_OVRD_EN_OVRD_MASK (0x10U) +#define ESC_ERR_LED_OVRD_EN_OVRD_SHIFT (4U) +#define ESC_ERR_LED_OVRD_EN_OVRD_SET(x) (((uint8_t)(x) << ESC_ERR_LED_OVRD_EN_OVRD_SHIFT) & ESC_ERR_LED_OVRD_EN_OVRD_MASK) +#define ESC_ERR_LED_OVRD_EN_OVRD_GET(x) (((uint8_t)(x) & ESC_ERR_LED_OVRD_EN_OVRD_MASK) >> ESC_ERR_LED_OVRD_EN_OVRD_SHIFT) + +/* + * LED_CODE (RW) + * + * LED code: + * 0x0:Off + * 0x1-0xC:Flash 1x – 12x + * 0xD:Blinking + * 0xE:Flickering + * 0xF:On + */ +#define ESC_ERR_LED_OVRD_LED_CODE_MASK (0xFU) +#define ESC_ERR_LED_OVRD_LED_CODE_SHIFT (0U) +#define ESC_ERR_LED_OVRD_LED_CODE_SET(x) (((uint8_t)(x) << ESC_ERR_LED_OVRD_LED_CODE_SHIFT) & ESC_ERR_LED_OVRD_LED_CODE_MASK) +#define ESC_ERR_LED_OVRD_LED_CODE_GET(x) (((uint8_t)(x) & ESC_ERR_LED_OVRD_LED_CODE_MASK) >> ESC_ERR_LED_OVRD_LED_CODE_SHIFT) + +/* Bitfield definition for register: PDI_CTRL */ +/* + * PDI (RO) + * + * Process data interface: + * 0x00:Interface deactivated (no PDI) + * 0x01:4 Digital Input + * 0x02:4 Digital Output + * 0x03:2 Digital Input and 2 Digital Output + * 0x04:Digital I/O + * 0x05:SPI Slave + * 0x06:Oversampling I/O + * 0x07:EtherCAT Bridge (port 3) + * 0x08:16 Bit asynchronous Microcontroller + * interface + * 0x09:8 Bit asynchronous Microcontroller + * interface + * 0x0A:16 Bit synchronous Microcontroller + * interface + * 0x0B:8 Bit synchronous Microcontroller + * interface + * 0x10:32 Digital Input and 0 Digital Output + * 0x11:24 Digital Input and 8 Digital Output + * 0x12:16 Digital Input and 16 Digital Output + * 0x13:8 Digital Input and 24 Digital Output + * 0x14:0 Digital Input and 32 Digital Output + * 0x80:On-chip bus + * Others:Reserved + */ +#define ESC_PDI_CTRL_PDI_MASK (0xFFU) +#define ESC_PDI_CTRL_PDI_SHIFT (0U) +#define ESC_PDI_CTRL_PDI_GET(x) (((uint8_t)(x) & ESC_PDI_CTRL_PDI_MASK) >> ESC_PDI_CTRL_PDI_SHIFT) + +/* Bitfield definition for register: ESC_CFG */ +/* + * ELP3 (RO) + * + * Enhanced Link port 3: + * 0:disabled (if bit 1=0) + * 1:enabled + */ +#define ESC_ESC_CFG_ELP3_MASK (0x80U) +#define ESC_ESC_CFG_ELP3_SHIFT (7U) +#define ESC_ESC_CFG_ELP3_GET(x) (((uint8_t)(x) & ESC_ESC_CFG_ELP3_MASK) >> ESC_ESC_CFG_ELP3_SHIFT) + +/* + * ELP2 (RO) + * + * Enhanced Link port 2: + * 0:disabled (if bit 1=0) + * 1:enabled + */ +#define ESC_ESC_CFG_ELP2_MASK (0x40U) +#define ESC_ESC_CFG_ELP2_SHIFT (6U) +#define ESC_ESC_CFG_ELP2_GET(x) (((uint8_t)(x) & ESC_ESC_CFG_ELP2_MASK) >> ESC_ESC_CFG_ELP2_SHIFT) + +/* + * ELP1 (RO) + * + * Enhanced Link port 1: + * 0:disabled (if bit 1=0) + * 1:enabled + */ +#define ESC_ESC_CFG_ELP1_MASK (0x20U) +#define ESC_ESC_CFG_ELP1_SHIFT (5U) +#define ESC_ESC_CFG_ELP1_GET(x) (((uint8_t)(x) & ESC_ESC_CFG_ELP1_MASK) >> ESC_ESC_CFG_ELP1_SHIFT) + +/* + * ELP0 (RO) + * + * Enhanced Link port 0: + * 0:disabled (if bit 1=0) + * 1:enabled + */ +#define ESC_ESC_CFG_ELP0_MASK (0x10U) +#define ESC_ESC_CFG_ELP0_SHIFT (4U) +#define ESC_ESC_CFG_ELP0_GET(x) (((uint8_t)(x) & ESC_ESC_CFG_ELP0_MASK) >> ESC_ESC_CFG_ELP0_SHIFT) + +/* + * CDLIU (RO) + * + * Distributed Clocks Latch In Unit: + * 0:disabled (power saving) + * 1:enabled + */ +#define ESC_ESC_CFG_CDLIU_MASK (0x8U) +#define ESC_ESC_CFG_CDLIU_SHIFT (3U) +#define ESC_ESC_CFG_CDLIU_GET(x) (((uint8_t)(x) & ESC_ESC_CFG_CDLIU_MASK) >> ESC_ESC_CFG_CDLIU_SHIFT) + +/* + * DCSOU (RO) + * + * Distributed Clocks SYNC Out Unit: + * 0:disabled (power saving) + * 1:enabled + */ +#define ESC_ESC_CFG_DCSOU_MASK (0x4U) +#define ESC_ESC_CFG_DCSOU_SHIFT (2U) +#define ESC_ESC_CFG_DCSOU_GET(x) (((uint8_t)(x) & ESC_ESC_CFG_DCSOU_MASK) >> ESC_ESC_CFG_DCSOU_SHIFT) + +/* + * ELDAP (RO) + * + * Enhanced Link detection all ports: + * 0:disabled (if bits [7:4]=0) + * 1:enabled at all ports (overrides bits [7:4]) + */ +#define ESC_ESC_CFG_ELDAP_MASK (0x2U) +#define ESC_ESC_CFG_ELDAP_SHIFT (1U) +#define ESC_ESC_CFG_ELDAP_GET(x) (((uint8_t)(x) & ESC_ESC_CFG_ELDAP_MASK) >> ESC_ESC_CFG_ELDAP_SHIFT) + +/* + * DEV_EMU (RO) + * + * Device emulation (control of AL status): + * 0:AL status register has to be set by PDI + * 1:AL status register will be set to value + * written to AL control register + */ +#define ESC_ESC_CFG_DEV_EMU_MASK (0x1U) +#define ESC_ESC_CFG_DEV_EMU_SHIFT (0U) +#define ESC_ESC_CFG_DEV_EMU_GET(x) (((uint8_t)(x) & ESC_ESC_CFG_DEV_EMU_MASK) >> ESC_ESC_CFG_DEV_EMU_SHIFT) + +/* Bitfield definition for register: PDI_INFO */ +/* + * PDICN (RO) + * + * PDI configuration invalid: + * 0:PDI configuration ok + * 1:PDI configuration invalid + */ +#define ESC_PDI_INFO_PDICN_MASK (0x8U) +#define ESC_PDI_INFO_PDICN_SHIFT (3U) +#define ESC_PDI_INFO_PDICN_GET(x) (((uint16_t)(x) & ESC_PDI_INFO_PDICN_MASK) >> ESC_PDI_INFO_PDICN_SHIFT) + +/* + * PDIA (RO) + * + * PDI active: + * 0:PDI not active + * 1:PDI active + */ +#define ESC_PDI_INFO_PDIA_MASK (0x4U) +#define ESC_PDI_INFO_PDIA_SHIFT (2U) +#define ESC_PDI_INFO_PDIA_GET(x) (((uint16_t)(x) & ESC_PDI_INFO_PDIA_MASK) >> ESC_PDI_INFO_PDIA_SHIFT) + +/* + * ECLFE (RO) + * + * ESC configuration area loaded from + * EEPROM: + * 0:not loaded + * 1:loaded + */ +#define ESC_PDI_INFO_ECLFE_MASK (0x2U) +#define ESC_PDI_INFO_ECLFE_SHIFT (1U) +#define ESC_PDI_INFO_ECLFE_GET(x) (((uint16_t)(x) & ESC_PDI_INFO_ECLFE_MASK) >> ESC_PDI_INFO_ECLFE_SHIFT) + +/* + * PFABW (RO) + * + * DI function acknowledge by write: + * 0:Disabled + * 1:Enabled + */ +#define ESC_PDI_INFO_PFABW_MASK (0x1U) +#define ESC_PDI_INFO_PFABW_SHIFT (0U) +#define ESC_PDI_INFO_PFABW_GET(x) (((uint16_t)(x) & ESC_PDI_INFO_PFABW_MASK) >> ESC_PDI_INFO_PFABW_SHIFT) + +/* Bitfield definition for register: PDI_CFG */ +/* + * BUS (RO) + * + * On-chip bus: + * 000:Intel® Avalon® + * 001:AXI® + * 010:Xilinx® PLB v4.6 + * 100:Xilinx OPB + * others:reserved + */ +#define ESC_PDI_CFG_BUS_MASK (0xE0U) +#define ESC_PDI_CFG_BUS_SHIFT (5U) +#define ESC_PDI_CFG_BUS_GET(x) (((uint8_t)(x) & ESC_PDI_CFG_BUS_MASK) >> ESC_PDI_CFG_BUS_SHIFT) + +/* + * CLK (RO) + * + * On-chip bus clock: + * 0:asynchronous + * 1-31:synchronous multiplication factor + * (N * 25 MHz) + */ +#define ESC_PDI_CFG_CLK_MASK (0x1FU) +#define ESC_PDI_CFG_CLK_SHIFT (0U) +#define ESC_PDI_CFG_CLK_GET(x) (((uint8_t)(x) & ESC_PDI_CFG_CLK_MASK) >> ESC_PDI_CFG_CLK_SHIFT) + +/* Bitfield definition for register: PDI_SL_CFG */ +/* + * SYNC1_MAER (RO) + * + * SYNC1 mapped to AL Event Request + * register 0x0220[3]: + * 0:Disabled + * 1:Enabled + */ +#define ESC_PDI_SL_CFG_SYNC1_MAER_MASK (0x80U) +#define ESC_PDI_SL_CFG_SYNC1_MAER_SHIFT (7U) +#define ESC_PDI_SL_CFG_SYNC1_MAER_GET(x) (((uint8_t)(x) & ESC_PDI_SL_CFG_SYNC1_MAER_MASK) >> ESC_PDI_SL_CFG_SYNC1_MAER_SHIFT) + +/* + * SYNC1_CFG (RO) + * + * SYNC1/LATCH1 configuration*: + * 0:LATCH1 input + * 1:SYNC1 output + */ +#define ESC_PDI_SL_CFG_SYNC1_CFG_MASK (0x40U) +#define ESC_PDI_SL_CFG_SYNC1_CFG_SHIFT (6U) +#define ESC_PDI_SL_CFG_SYNC1_CFG_GET(x) (((uint8_t)(x) & ESC_PDI_SL_CFG_SYNC1_CFG_MASK) >> ESC_PDI_SL_CFG_SYNC1_CFG_SHIFT) + +/* + * SYNC1_ODP (RO) + * + * SYNC1 output driver/polarity: + * 00:Push-Pull active low + * 01:Open Drain (active low) + * 10:Push-Pull active high + * 11:Open Source (active high) + */ +#define ESC_PDI_SL_CFG_SYNC1_ODP_MASK (0x30U) +#define ESC_PDI_SL_CFG_SYNC1_ODP_SHIFT (4U) +#define ESC_PDI_SL_CFG_SYNC1_ODP_GET(x) (((uint8_t)(x) & ESC_PDI_SL_CFG_SYNC1_ODP_MASK) >> ESC_PDI_SL_CFG_SYNC1_ODP_SHIFT) + +/* + * SYNC0_MAER (RO) + * + * SYNC0 mapped to AL Event Request + * register 0x0220[2]: + * 0:Disabled + * 1:Enabled + */ +#define ESC_PDI_SL_CFG_SYNC0_MAER_MASK (0x8U) +#define ESC_PDI_SL_CFG_SYNC0_MAER_SHIFT (3U) +#define ESC_PDI_SL_CFG_SYNC0_MAER_GET(x) (((uint8_t)(x) & ESC_PDI_SL_CFG_SYNC0_MAER_MASK) >> ESC_PDI_SL_CFG_SYNC0_MAER_SHIFT) + +/* + * SYNC0_CFG (RO) + * + * SYNC0/LATCH0 configuration*: + * 0:LATCH0 Input + * 1:SYNC0 Output + */ +#define ESC_PDI_SL_CFG_SYNC0_CFG_MASK (0x4U) +#define ESC_PDI_SL_CFG_SYNC0_CFG_SHIFT (2U) +#define ESC_PDI_SL_CFG_SYNC0_CFG_GET(x) (((uint8_t)(x) & ESC_PDI_SL_CFG_SYNC0_CFG_MASK) >> ESC_PDI_SL_CFG_SYNC0_CFG_SHIFT) + +/* + * SYNC0_ODP (RO) + * + * SYNC0 output driver/polarity: + * 00:Push-Pull active low + * 01:Open Drain (active low) + * 10:Push-Pull active high + * 11:Open Source (active high) + */ +#define ESC_PDI_SL_CFG_SYNC0_ODP_MASK (0x3U) +#define ESC_PDI_SL_CFG_SYNC0_ODP_SHIFT (0U) +#define ESC_PDI_SL_CFG_SYNC0_ODP_GET(x) (((uint8_t)(x) & ESC_PDI_SL_CFG_SYNC0_ODP_MASK) >> ESC_PDI_SL_CFG_SYNC0_ODP_SHIFT) + +/* Bitfield definition for register: PDI_EXT_CFG */ +/* + * OCBST (RW) + * + * On-chip bus sub-type for AXI: + * 000:AXI3 + * 001:AXI4 + * 010:AXI4 LITE + * others:reserved + */ +#define ESC_PDI_EXT_CFG_OCBST_MASK (0x700U) +#define ESC_PDI_EXT_CFG_OCBST_SHIFT (8U) +#define ESC_PDI_EXT_CFG_OCBST_SET(x) (((uint16_t)(x) << ESC_PDI_EXT_CFG_OCBST_SHIFT) & ESC_PDI_EXT_CFG_OCBST_MASK) +#define ESC_PDI_EXT_CFG_OCBST_GET(x) (((uint16_t)(x) & ESC_PDI_EXT_CFG_OCBST_MASK) >> ESC_PDI_EXT_CFG_OCBST_SHIFT) + +/* + * RPS (RO) + * + * Read prefetch size (in cycles of PDI width): + * 0:4 cycles + * 1:1 cycle (typical) + * 2:2 cycles + * 3:Reserved + */ +#define ESC_PDI_EXT_CFG_RPS_MASK (0x3U) +#define ESC_PDI_EXT_CFG_RPS_SHIFT (0U) +#define ESC_PDI_EXT_CFG_RPS_GET(x) (((uint16_t)(x) & ESC_PDI_EXT_CFG_RPS_MASK) >> ESC_PDI_EXT_CFG_RPS_SHIFT) + +/* Bitfield definition for register: ECAT_EVT_MSK */ +/* + * MASK (RO) + * + * ECAT Event masking of the ECAT Event + * Request Events for mapping into ECAT event + * field of EtherCAT frames: + * 0:Corresponding ECAT Event Request + * register bit is not mapped + * 1:Corresponding ECAT Event Request + * register bit is mapped + */ +#define ESC_ECAT_EVT_MSK_MASK_MASK (0xFFFFU) +#define ESC_ECAT_EVT_MSK_MASK_SHIFT (0U) +#define ESC_ECAT_EVT_MSK_MASK_GET(x) (((uint16_t)(x) & ESC_ECAT_EVT_MSK_MASK_MASK) >> ESC_ECAT_EVT_MSK_MASK_SHIFT) + +/* Bitfield definition for register: PDI_AL_EVT_MSK */ +/* + * MASK (RW) + * + * AL Event masking of the AL Event Request + * register Events for mapping to PDI IRQ + * signal: + * 0:Corresponding AL Event Request + * register bit is not mapped + * 1:Corresponding AL Event Request + * register bit is mapped + */ +#define ESC_PDI_AL_EVT_MSK_MASK_MASK (0xFFFFFFFFUL) +#define ESC_PDI_AL_EVT_MSK_MASK_SHIFT (0U) +#define ESC_PDI_AL_EVT_MSK_MASK_SET(x) (((uint32_t)(x) << ESC_PDI_AL_EVT_MSK_MASK_SHIFT) & ESC_PDI_AL_EVT_MSK_MASK_MASK) +#define ESC_PDI_AL_EVT_MSK_MASK_GET(x) (((uint32_t)(x) & ESC_PDI_AL_EVT_MSK_MASK_MASK) >> ESC_PDI_AL_EVT_MSK_MASK_SHIFT) + +/* Bitfield definition for register: ECAT_EVT_REQ */ +/* + * MV (RO) + * + * Mirrors values of each SyncManager Status: + * 0:No Sync Channel 0 event + * 1:Sync Channel 0 event pending + * 0:No Sync Channel 1 event + * 1:Sync Channel 1 event pending + * … + * 0:No Sync Channel 7 event + * 1:Sync Channel 7 event pending + */ +#define ESC_ECAT_EVT_REQ_MV_MASK (0xFF0U) +#define ESC_ECAT_EVT_REQ_MV_SHIFT (4U) +#define ESC_ECAT_EVT_REQ_MV_GET(x) (((uint16_t)(x) & ESC_ECAT_EVT_REQ_MV_MASK) >> ESC_ECAT_EVT_REQ_MV_SHIFT) + +/* + * ALS_EVT (RO) + * + * AL Status event: + * 0:No change in AL Status + * 1:AL Status change + * (Bit is cleared by reading out AL Status + * 0x0130:0x0131 from ECAT) + */ +#define ESC_ECAT_EVT_REQ_ALS_EVT_MASK (0x8U) +#define ESC_ECAT_EVT_REQ_ALS_EVT_SHIFT (3U) +#define ESC_ECAT_EVT_REQ_ALS_EVT_GET(x) (((uint16_t)(x) & ESC_ECAT_EVT_REQ_ALS_EVT_MASK) >> ESC_ECAT_EVT_REQ_ALS_EVT_SHIFT) + +/* + * DLS_EVT (RO) + * + * DL Status event: + * 0:No change in DL Status + * 1:DL Status change + * (Bit is cleared by reading out DL Status + * 0x0110:0x0111 from ECAT) + */ +#define ESC_ECAT_EVT_REQ_DLS_EVT_MASK (0x4U) +#define ESC_ECAT_EVT_REQ_DLS_EVT_SHIFT (2U) +#define ESC_ECAT_EVT_REQ_DLS_EVT_GET(x) (((uint16_t)(x) & ESC_ECAT_EVT_REQ_DLS_EVT_MASK) >> ESC_ECAT_EVT_REQ_DLS_EVT_SHIFT) + +/* + * DCL_EVT (RO) + * + * DC Latch event: + * 0:No change on DC Latch Inputs + * 1:At least one change on DC Latch Inputs + * (Bit is cleared by reading DC Latch event + * times from ECAT for ECAT-controlled Latch + * Units, so that Latch 0/1 Status + * 0x09AE:0x09AF indicates no event) + */ +#define ESC_ECAT_EVT_REQ_DCL_EVT_MASK (0x1U) +#define ESC_ECAT_EVT_REQ_DCL_EVT_SHIFT (0U) +#define ESC_ECAT_EVT_REQ_DCL_EVT_GET(x) (((uint16_t)(x) & ESC_ECAT_EVT_REQ_DCL_EVT_MASK) >> ESC_ECAT_EVT_REQ_DCL_EVT_SHIFT) + +/* Bitfield definition for register: AL_EVT_REQ */ +/* + * SM_INT (RO) + * + * SyncManager interrupts (SyncManager + * register offset 0x5, bit [0] or [1]): + * 0:No SyncManager 0 interrupt + * 1:SyncManager 0 interrupt pending + * 0:No SyncManager 1 interrupt + * 1:SyncManager 1 interrupt pending + * … + * 0:No SyncManager 15 interrupt + * 1:SyncManager 15 interrupt pending + */ +#define ESC_AL_EVT_REQ_SM_INT_MASK (0xFFFF00UL) +#define ESC_AL_EVT_REQ_SM_INT_SHIFT (8U) +#define ESC_AL_EVT_REQ_SM_INT_GET(x) (((uint32_t)(x) & ESC_AL_EVT_REQ_SM_INT_MASK) >> ESC_AL_EVT_REQ_SM_INT_SHIFT) + +/* + * WDG_PD (RO) + * + * Watchdog Process Data: + * 0:Has not expired + * 1:Has expired + * (Bit is cleared by reading Watchdog Status + * Process Data 0x0440 from PDI) + */ +#define ESC_AL_EVT_REQ_WDG_PD_MASK (0x40U) +#define ESC_AL_EVT_REQ_WDG_PD_SHIFT (6U) +#define ESC_AL_EVT_REQ_WDG_PD_GET(x) (((uint32_t)(x) & ESC_AL_EVT_REQ_WDG_PD_MASK) >> ESC_AL_EVT_REQ_WDG_PD_SHIFT) + +/* + * EE_EMU (RO) + * + * EEPROM Emulation: + * 0:No command pending + * 1:EEPROM command pending + * (Bit is cleared by acknowledging the + * command in EEPROM Control/Status + * register 0x0502:0x0503[10:8] from PDI) + */ +#define ESC_AL_EVT_REQ_EE_EMU_MASK (0x20U) +#define ESC_AL_EVT_REQ_EE_EMU_SHIFT (5U) +#define ESC_AL_EVT_REQ_EE_EMU_GET(x) (((uint32_t)(x) & ESC_AL_EVT_REQ_EE_EMU_MASK) >> ESC_AL_EVT_REQ_EE_EMU_SHIFT) + +/* + * SM_ACT (RO) + * + * SyncManager activation register + * (SyncManager register offset 0x6) changed: + * 0:No change in any SyncManager + * 1:At least one SyncManager changed + * (Bit is cleared by reading SyncManager + * Activation registers 0x0806 etc. from PDI) + */ +#define ESC_AL_EVT_REQ_SM_ACT_MASK (0x10U) +#define ESC_AL_EVT_REQ_SM_ACT_SHIFT (4U) +#define ESC_AL_EVT_REQ_SM_ACT_GET(x) (((uint32_t)(x) & ESC_AL_EVT_REQ_SM_ACT_MASK) >> ESC_AL_EVT_REQ_SM_ACT_SHIFT) + +/* + * ST_DC_SYNC1 (RO) + * + * State of DC SYNC1 (if register + * 0x0151[7]=1): + * (Bit is cleared by reading of SYNC1 status + * 0x098F from PDI, use only in Acknowledge + * mode) + */ +#define ESC_AL_EVT_REQ_ST_DC_SYNC1_MASK (0x8U) +#define ESC_AL_EVT_REQ_ST_DC_SYNC1_SHIFT (3U) +#define ESC_AL_EVT_REQ_ST_DC_SYNC1_GET(x) (((uint32_t)(x) & ESC_AL_EVT_REQ_ST_DC_SYNC1_MASK) >> ESC_AL_EVT_REQ_ST_DC_SYNC1_SHIFT) + +/* + * ST_DC_SYNC0 (RO) + * + * State of DC SYNC0 (if register + * 0x0151[3]=1): + * (Bit is cleared by reading SYNC0 status + * 0x098E from PDI, use only in Acknowledge + * mode) + */ +#define ESC_AL_EVT_REQ_ST_DC_SYNC0_MASK (0x4U) +#define ESC_AL_EVT_REQ_ST_DC_SYNC0_SHIFT (2U) +#define ESC_AL_EVT_REQ_ST_DC_SYNC0_GET(x) (((uint32_t)(x) & ESC_AL_EVT_REQ_ST_DC_SYNC0_MASK) >> ESC_AL_EVT_REQ_ST_DC_SYNC0_SHIFT) + +/* + * DCL_EVT (RO) + * + * DC Latch event: + * 0:No change on DC Latch Inputs + * 1:At least one change on DC Latch Inputs + * (Bit is cleared by reading DC Latch event + * times from PDI, so that Latch 0/1 Status + * 0x09AE:0x09AF indicates no event. Available + * if Latch Unit is PDI-controlled) + */ +#define ESC_AL_EVT_REQ_DCL_EVT_MASK (0x2U) +#define ESC_AL_EVT_REQ_DCL_EVT_SHIFT (1U) +#define ESC_AL_EVT_REQ_DCL_EVT_GET(x) (((uint32_t)(x) & ESC_AL_EVT_REQ_DCL_EVT_MASK) >> ESC_AL_EVT_REQ_DCL_EVT_SHIFT) + +/* + * ALC_EVT (RO) + * + * AL Control event: + * 0:No AL Control Register change + * 1:AL Control Register has been written3 + * (Bit is cleared by reading AL Control register + * 0x0120:0x0121 from PDI) + */ +#define ESC_AL_EVT_REQ_ALC_EVT_MASK (0x1U) +#define ESC_AL_EVT_REQ_ALC_EVT_SHIFT (0U) +#define ESC_AL_EVT_REQ_ALC_EVT_GET(x) (((uint32_t)(x) & ESC_AL_EVT_REQ_ALC_EVT_MASK) >> ESC_AL_EVT_REQ_ALC_EVT_SHIFT) + +/* Bitfield definition for register array: RX_ERR_CNT */ +/* + * RX_ERR (RO) + * + * RX Error counter of Port y (counting is + * stopped when 0xFF is reached). + */ +#define ESC_RX_ERR_CNT_RX_ERR_MASK (0xFF00U) +#define ESC_RX_ERR_CNT_RX_ERR_SHIFT (8U) +#define ESC_RX_ERR_CNT_RX_ERR_GET(x) (((uint16_t)(x) & ESC_RX_ERR_CNT_RX_ERR_MASK) >> ESC_RX_ERR_CNT_RX_ERR_SHIFT) + +/* + * IVD_FRM (RO) + * + * Invalid frame counter of Port y (counting is + * stopped when 0xFF is reached). + */ +#define ESC_RX_ERR_CNT_IVD_FRM_MASK (0xFFU) +#define ESC_RX_ERR_CNT_IVD_FRM_SHIFT (0U) +#define ESC_RX_ERR_CNT_IVD_FRM_GET(x) (((uint16_t)(x) & ESC_RX_ERR_CNT_IVD_FRM_MASK) >> ESC_RX_ERR_CNT_IVD_FRM_SHIFT) + +/* Bitfield definition for register array: FWD_RX_ERR_CNT */ +/* + * ERR_CNT (RO) + * + * Forwarded error counter of Port y (counting is + * stopped when 0xFF is reached). + */ +#define ESC_FWD_RX_ERR_CNT_ERR_CNT_MASK (0xFFU) +#define ESC_FWD_RX_ERR_CNT_ERR_CNT_SHIFT (0U) +#define ESC_FWD_RX_ERR_CNT_ERR_CNT_GET(x) (((uint8_t)(x) & ESC_FWD_RX_ERR_CNT_ERR_CNT_MASK) >> ESC_FWD_RX_ERR_CNT_ERR_CNT_SHIFT) + +/* Bitfield definition for register: ECAT_PU_ERR_CNT */ +/* + * CNT (RO) + * + * ECAT Processing Unit error counter + * (counting is stopped when 0xFF is reached). + * Counts errors of frames passing the + * Processing Unit. + */ +#define ESC_ECAT_PU_ERR_CNT_CNT_MASK (0xFFU) +#define ESC_ECAT_PU_ERR_CNT_CNT_SHIFT (0U) +#define ESC_ECAT_PU_ERR_CNT_CNT_GET(x) (((uint8_t)(x) & ESC_ECAT_PU_ERR_CNT_CNT_MASK) >> ESC_ECAT_PU_ERR_CNT_CNT_SHIFT) + +/* Bitfield definition for register: PDI_ERR_CNT */ +/* + * CNT (RO) + * + * PDI Error counter (counting is stopped when + * 0xFF is reached). Counts if a PDI access has + * an interface error. + */ +#define ESC_PDI_ERR_CNT_CNT_MASK (0xFFU) +#define ESC_PDI_ERR_CNT_CNT_SHIFT (0U) +#define ESC_PDI_ERR_CNT_CNT_GET(x) (((uint8_t)(x) & ESC_PDI_ERR_CNT_CNT_MASK) >> ESC_PDI_ERR_CNT_CNT_SHIFT) + +/* Bitfield definition for register array: LOST_LINK_CNT */ +/* + * CNT (RO) + * + * Lost Link counter of Port y (counting is + * stopped when 0xff is reached). Counts only if + * port is open and loop is Auto. + */ +#define ESC_LOST_LINK_CNT_CNT_MASK (0xFFU) +#define ESC_LOST_LINK_CNT_CNT_SHIFT (0U) +#define ESC_LOST_LINK_CNT_CNT_GET(x) (((uint8_t)(x) & ESC_LOST_LINK_CNT_CNT_MASK) >> ESC_LOST_LINK_CNT_CNT_SHIFT) + +/* Bitfield definition for register: WDG_DIV */ +/* + * DIV (RO) + * + * Watchdog divider:Number of 25 MHz tics + * (minus 2) that represent the basic watchdog + * increment. (Default value is 100µs = 2498) + */ +#define ESC_WDG_DIV_DIV_MASK (0xFFFFU) +#define ESC_WDG_DIV_DIV_SHIFT (0U) +#define ESC_WDG_DIV_DIV_GET(x) (((uint16_t)(x) & ESC_WDG_DIV_DIV_MASK) >> ESC_WDG_DIV_DIV_SHIFT) + +/* Bitfield definition for register: WDG_TIME_PDI */ +/* + * TIME (RO) + * + * Watchdog Time PDI:number of basic + * watchdog increments + * (Default value with Watchdog divider 100µs + * means 100ms Watchdog) + */ +#define ESC_WDG_TIME_PDI_TIME_MASK (0xFFFFU) +#define ESC_WDG_TIME_PDI_TIME_SHIFT (0U) +#define ESC_WDG_TIME_PDI_TIME_GET(x) (((uint16_t)(x) & ESC_WDG_TIME_PDI_TIME_MASK) >> ESC_WDG_TIME_PDI_TIME_SHIFT) + +/* Bitfield definition for register: WDG_TIME_PDAT */ +/* + * TIME (RO) + * + * Watchdog Time Process Data:number of + * basic watchdog increments + * (Default value with Watchdog divider 100µs + * means 100ms Watchdog) + */ +#define ESC_WDG_TIME_PDAT_TIME_MASK (0xFFFFU) +#define ESC_WDG_TIME_PDAT_TIME_SHIFT (0U) +#define ESC_WDG_TIME_PDAT_TIME_GET(x) (((uint16_t)(x) & ESC_WDG_TIME_PDAT_TIME_MASK) >> ESC_WDG_TIME_PDAT_TIME_SHIFT) + +/* Bitfield definition for register: WDG_STAT_PDAT */ +/* + * ST (RW) + * + * Watchdog Status of Process Data (triggered + * by SyncManagers) + * 0:Watchdog Process Data expired + * 1:Watchdog Process Data is active or + * disabled + */ +#define ESC_WDG_STAT_PDAT_ST_MASK (0x1U) +#define ESC_WDG_STAT_PDAT_ST_SHIFT (0U) +#define ESC_WDG_STAT_PDAT_ST_SET(x) (((uint16_t)(x) << ESC_WDG_STAT_PDAT_ST_SHIFT) & ESC_WDG_STAT_PDAT_ST_MASK) +#define ESC_WDG_STAT_PDAT_ST_GET(x) (((uint16_t)(x) & ESC_WDG_STAT_PDAT_ST_MASK) >> ESC_WDG_STAT_PDAT_ST_SHIFT) + +/* Bitfield definition for register: WDG_CNT_PDAT */ +/* + * CNT (RO) + * + * Watchdog Counter Process Data (counting is + * stopped when 0xFF is reached). Counts if + * Process Data Watchdog expires. + */ +#define ESC_WDG_CNT_PDAT_CNT_MASK (0xFFU) +#define ESC_WDG_CNT_PDAT_CNT_SHIFT (0U) +#define ESC_WDG_CNT_PDAT_CNT_GET(x) (((uint8_t)(x) & ESC_WDG_CNT_PDAT_CNT_MASK) >> ESC_WDG_CNT_PDAT_CNT_SHIFT) + +/* Bitfield definition for register: WDG_CNT_PDI */ +/* + * CNT (RO) + * + * Watchdog PDI counter (counting is stopped + * when 0xFF is reached). Counts if PDI + * Watchdog expires. + */ +#define ESC_WDG_CNT_PDI_CNT_MASK (0xFFU) +#define ESC_WDG_CNT_PDI_CNT_SHIFT (0U) +#define ESC_WDG_CNT_PDI_CNT_GET(x) (((uint8_t)(x) & ESC_WDG_CNT_PDI_CNT_MASK) >> ESC_WDG_CNT_PDI_CNT_SHIFT) + +/* Bitfield definition for register: EEPROM_CFG */ +/* + * FORCE_ECAT (RO) + * + * Force ECAT access: + * 0:Do not change Bit 0x0501[0] + * 1:Reset Bit 0x0501[0] to 0 + */ +#define ESC_EEPROM_CFG_FORCE_ECAT_MASK (0x2U) +#define ESC_EEPROM_CFG_FORCE_ECAT_SHIFT (1U) +#define ESC_EEPROM_CFG_FORCE_ECAT_GET(x) (((uint8_t)(x) & ESC_EEPROM_CFG_FORCE_ECAT_MASK) >> ESC_EEPROM_CFG_FORCE_ECAT_SHIFT) + +/* + * PDI (RO) + * + * EEPROM control is offered to PDI: + * 0:no + * 1:yes (PDI has EEPROM control) + */ +#define ESC_EEPROM_CFG_PDI_MASK (0x1U) +#define ESC_EEPROM_CFG_PDI_SHIFT (0U) +#define ESC_EEPROM_CFG_PDI_GET(x) (((uint8_t)(x) & ESC_EEPROM_CFG_PDI_MASK) >> ESC_EEPROM_CFG_PDI_SHIFT) + +/* Bitfield definition for register: EEPROM_PDI_ACC_STAT */ +/* + * ACCESS (RW) + * + * Access to EEPROM: + * 0:PDI releases EEPROM access + * 1:PDI takes EEPROM access (PDI has + * EEPROM control) + */ +#define ESC_EEPROM_PDI_ACC_STAT_ACCESS_MASK (0x1U) +#define ESC_EEPROM_PDI_ACC_STAT_ACCESS_SHIFT (0U) +#define ESC_EEPROM_PDI_ACC_STAT_ACCESS_SET(x) (((uint8_t)(x) << ESC_EEPROM_PDI_ACC_STAT_ACCESS_SHIFT) & ESC_EEPROM_PDI_ACC_STAT_ACCESS_MASK) +#define ESC_EEPROM_PDI_ACC_STAT_ACCESS_GET(x) (((uint8_t)(x) & ESC_EEPROM_PDI_ACC_STAT_ACCESS_MASK) >> ESC_EEPROM_PDI_ACC_STAT_ACCESS_SHIFT) + +/* Bitfield definition for register: EEPROM_CTRL_STAT */ +/* + * BUSY (RO) + * + * Busy: + * 0:EEPROM Interface is idle + * 1:EEPROM Interface is busy + */ +#define ESC_EEPROM_CTRL_STAT_BUSY_MASK (0x8000U) +#define ESC_EEPROM_CTRL_STAT_BUSY_SHIFT (15U) +#define ESC_EEPROM_CTRL_STAT_BUSY_GET(x) (((uint16_t)(x) & ESC_EEPROM_CTRL_STAT_BUSY_MASK) >> ESC_EEPROM_CTRL_STAT_BUSY_SHIFT) + +/* + * ERR_WEN (RO) + * + * Error Write Enable*3 + * : + * 0:No error + * 1:Write Command without Write enable + */ +#define ESC_EEPROM_CTRL_STAT_ERR_WEN_MASK (0x4000U) +#define ESC_EEPROM_CTRL_STAT_ERR_WEN_SHIFT (14U) +#define ESC_EEPROM_CTRL_STAT_ERR_WEN_GET(x) (((uint16_t)(x) & ESC_EEPROM_CTRL_STAT_ERR_WEN_MASK) >> ESC_EEPROM_CTRL_STAT_ERR_WEN_SHIFT) + +/* + * ERR_ACK_CMD (RW) + * + * Error Acknowledge/Command*3 + * : + * 0:No error + * 1:Missing EEPROM acknowledge or invalid + * command + * EEPROM emulation only:PDI writes 1 if a temporary + * failure has occurred. + */ +#define ESC_EEPROM_CTRL_STAT_ERR_ACK_CMD_MASK (0x2000U) +#define ESC_EEPROM_CTRL_STAT_ERR_ACK_CMD_SHIFT (13U) +#define ESC_EEPROM_CTRL_STAT_ERR_ACK_CMD_SET(x) (((uint16_t)(x) << ESC_EEPROM_CTRL_STAT_ERR_ACK_CMD_SHIFT) & ESC_EEPROM_CTRL_STAT_ERR_ACK_CMD_MASK) +#define ESC_EEPROM_CTRL_STAT_ERR_ACK_CMD_GET(x) (((uint16_t)(x) & ESC_EEPROM_CTRL_STAT_ERR_ACK_CMD_MASK) >> ESC_EEPROM_CTRL_STAT_ERR_ACK_CMD_SHIFT) + +/* + * EE_LDS (RO) + * + * EEPROM loading status: + * 0:EEPROM loaded, device information ok + * 1:EEPROM not loaded, device information not + * available (EEPROM loading in progress or + * finished with a failure) + */ +#define ESC_EEPROM_CTRL_STAT_EE_LDS_MASK (0x1000U) +#define ESC_EEPROM_CTRL_STAT_EE_LDS_SHIFT (12U) +#define ESC_EEPROM_CTRL_STAT_EE_LDS_GET(x) (((uint16_t)(x) & ESC_EEPROM_CTRL_STAT_EE_LDS_MASK) >> ESC_EEPROM_CTRL_STAT_EE_LDS_SHIFT) + +/* + * CKSM_ERR (RW) + * + * Checksum Error in ESC Configuration Area: + * 0:Checksum ok + * 1:Checksum error + * EEPROM emulation for IP Core only:PDI writes 1 if a + * CRC failure has occurred for a reload command. + */ +#define ESC_EEPROM_CTRL_STAT_CKSM_ERR_MASK (0x800U) +#define ESC_EEPROM_CTRL_STAT_CKSM_ERR_SHIFT (11U) +#define ESC_EEPROM_CTRL_STAT_CKSM_ERR_SET(x) (((uint16_t)(x) << ESC_EEPROM_CTRL_STAT_CKSM_ERR_SHIFT) & ESC_EEPROM_CTRL_STAT_CKSM_ERR_MASK) +#define ESC_EEPROM_CTRL_STAT_CKSM_ERR_GET(x) (((uint16_t)(x) & ESC_EEPROM_CTRL_STAT_CKSM_ERR_MASK) >> ESC_EEPROM_CTRL_STAT_CKSM_ERR_SHIFT) + +/* + * CMD (RW) + * + * Command register*2: + * Write:Initiate command. + * Read:Currently executed command + * Commands: + * 000:No command/EEPROM idle (clear error bits) + * 001:Read + * 010:Write + * 100:Reload + * Others:Reserved/invalid commands (do not issue) + * EEPROM emulation only:after execution, PDI writes + * command value to indicate operation is ready. + */ +#define ESC_EEPROM_CTRL_STAT_CMD_MASK (0x700U) +#define ESC_EEPROM_CTRL_STAT_CMD_SHIFT (8U) +#define ESC_EEPROM_CTRL_STAT_CMD_SET(x) (((uint16_t)(x) << ESC_EEPROM_CTRL_STAT_CMD_SHIFT) & ESC_EEPROM_CTRL_STAT_CMD_MASK) +#define ESC_EEPROM_CTRL_STAT_CMD_GET(x) (((uint16_t)(x) & ESC_EEPROM_CTRL_STAT_CMD_MASK) >> ESC_EEPROM_CTRL_STAT_CMD_SHIFT) + +/* + * EE_ALGM (RO) + * + * Selected EEPROM Algorithm: + * 0:1 address byte (1Kbit – 16Kbit EEPROMs) + * 1:2 address bytes (32Kbit – 4 Mbit EEPROMs) + */ +#define ESC_EEPROM_CTRL_STAT_EE_ALGM_MASK (0x80U) +#define ESC_EEPROM_CTRL_STAT_EE_ALGM_SHIFT (7U) +#define ESC_EEPROM_CTRL_STAT_EE_ALGM_GET(x) (((uint16_t)(x) & ESC_EEPROM_CTRL_STAT_EE_ALGM_MASK) >> ESC_EEPROM_CTRL_STAT_EE_ALGM_SHIFT) + +/* + * NUM_RD_BYTE (RO) + * + * Supported number of EEPROM read bytes: + * 0:4 Bytes + * 1:8 Bytes + */ +#define ESC_EEPROM_CTRL_STAT_NUM_RD_BYTE_MASK (0x40U) +#define ESC_EEPROM_CTRL_STAT_NUM_RD_BYTE_SHIFT (6U) +#define ESC_EEPROM_CTRL_STAT_NUM_RD_BYTE_GET(x) (((uint16_t)(x) & ESC_EEPROM_CTRL_STAT_NUM_RD_BYTE_MASK) >> ESC_EEPROM_CTRL_STAT_NUM_RD_BYTE_SHIFT) + +/* + * EE_EMU (RO) + * + * EPROM emulation: + * 0:Normal operation (I²C interface used) + * 1:PDI emulates EEPROM (I²C not used) + */ +#define ESC_EEPROM_CTRL_STAT_EE_EMU_MASK (0x20U) +#define ESC_EEPROM_CTRL_STAT_EE_EMU_SHIFT (5U) +#define ESC_EEPROM_CTRL_STAT_EE_EMU_GET(x) (((uint16_t)(x) & ESC_EEPROM_CTRL_STAT_EE_EMU_MASK) >> ESC_EEPROM_CTRL_STAT_EE_EMU_SHIFT) + +/* + * ECAT_WEN (RO) + * + * ECAT write enable*2 + * : + * 0:Write requests are disabled + * 1:Write requests are enabled + * This bit is always 1 if PDI has EEPROM control. + */ +#define ESC_EEPROM_CTRL_STAT_ECAT_WEN_MASK (0x1U) +#define ESC_EEPROM_CTRL_STAT_ECAT_WEN_SHIFT (0U) +#define ESC_EEPROM_CTRL_STAT_ECAT_WEN_GET(x) (((uint16_t)(x) & ESC_EEPROM_CTRL_STAT_ECAT_WEN_MASK) >> ESC_EEPROM_CTRL_STAT_ECAT_WEN_SHIFT) + +/* Bitfield definition for register: EEPROM_ADDR */ +/* + * ADDR (RW) + * + * EEPROM Address + * 0:First word (= 16 bit) + * 1:Second word + * … + * Actually used EEPROM Address bits: + * 9-0: EEPROM size up to 16 Kbit + * 17-0: EEPROM size 32 Kbit – 4 Mbit + * 31-0: EEPROM Emulation + */ +#define ESC_EEPROM_ADDR_ADDR_MASK (0xFFFFFFFFUL) +#define ESC_EEPROM_ADDR_ADDR_SHIFT (0U) +#define ESC_EEPROM_ADDR_ADDR_SET(x) (((uint32_t)(x) << ESC_EEPROM_ADDR_ADDR_SHIFT) & ESC_EEPROM_ADDR_ADDR_MASK) +#define ESC_EEPROM_ADDR_ADDR_GET(x) (((uint32_t)(x) & ESC_EEPROM_ADDR_ADDR_MASK) >> ESC_EEPROM_ADDR_ADDR_SHIFT) + +/* Bitfield definition for register: EEPROM_DATA */ +/* + * HI (RW) + * + * EEPROM Read data (data read from + * EEPROM, higher bytes) + */ +#define ESC_EEPROM_DATA_HI_MASK (0xFFFFFFFFFFFF0000ULL) +#define ESC_EEPROM_DATA_HI_SHIFT (16U) +#define ESC_EEPROM_DATA_HI_SET(x) (((uint64_t)(x) << ESC_EEPROM_DATA_HI_SHIFT) & ESC_EEPROM_DATA_HI_MASK) +#define ESC_EEPROM_DATA_HI_GET(x) (((uint64_t)(x) & ESC_EEPROM_DATA_HI_MASK) >> ESC_EEPROM_DATA_HI_SHIFT) + +/* + * LO (RW) + * + * EEPROM Write data (data to be written to + * EEPROM) or + * EEPROM Read data (data read from + * EEPROM, lower bytes) + */ +#define ESC_EEPROM_DATA_LO_MASK (0xFFFFU) +#define ESC_EEPROM_DATA_LO_SHIFT (0U) +#define ESC_EEPROM_DATA_LO_SET(x) (((uint64_t)(x) << ESC_EEPROM_DATA_LO_SHIFT) & ESC_EEPROM_DATA_LO_MASK) +#define ESC_EEPROM_DATA_LO_GET(x) (((uint64_t)(x) & ESC_EEPROM_DATA_LO_MASK) >> ESC_EEPROM_DATA_LO_SHIFT) + +/* Bitfield definition for register: MII_MNG_CS */ +/* + * BUSY (RO) + * + * Busy: + * 0:MII Management Interface is idle + * 1:MII Management Interface is busy + */ +#define ESC_MII_MNG_CS_BUSY_MASK (0x8000U) +#define ESC_MII_MNG_CS_BUSY_SHIFT (15U) +#define ESC_MII_MNG_CS_BUSY_GET(x) (((uint16_t)(x) & ESC_MII_MNG_CS_BUSY_MASK) >> ESC_MII_MNG_CS_BUSY_SHIFT) + +/* + * CMD_ERR (RO) + * + * Command error: + * 0:Last Command was successful + * 1:Invalid command or write command + * without Write Enable + * Cleared by executing a valid command or by + * writing “00” to Command register bits [9:8]. + */ +#define ESC_MII_MNG_CS_CMD_ERR_MASK (0x4000U) +#define ESC_MII_MNG_CS_CMD_ERR_SHIFT (14U) +#define ESC_MII_MNG_CS_CMD_ERR_GET(x) (((uint16_t)(x) & ESC_MII_MNG_CS_CMD_ERR_MASK) >> ESC_MII_MNG_CS_CMD_ERR_SHIFT) + +/* + * RD_ERR (RO) + * + * Read error: + * 0:No read error + * 1:Read error occurred (PHY or register + * not available) + * Cleared by writing to register 0x0511 + */ +#define ESC_MII_MNG_CS_RD_ERR_MASK (0x2000U) +#define ESC_MII_MNG_CS_RD_ERR_SHIFT (13U) +#define ESC_MII_MNG_CS_RD_ERR_GET(x) (((uint16_t)(x) & ESC_MII_MNG_CS_RD_ERR_MASK) >> ESC_MII_MNG_CS_RD_ERR_SHIFT) + +/* + * CMD (RW) + * + * Command register*: + * Write:Initiate command. + * Read:Currently executed command + * 00:No command/MI idle (clear error bits) + * 01:Read + * 10:Write + * Others:Reserved/invalid command (do not + * issue) + */ +#define ESC_MII_MNG_CS_CMD_MASK (0x300U) +#define ESC_MII_MNG_CS_CMD_SHIFT (8U) +#define ESC_MII_MNG_CS_CMD_SET(x) (((uint16_t)(x) << ESC_MII_MNG_CS_CMD_SHIFT) & ESC_MII_MNG_CS_CMD_MASK) +#define ESC_MII_MNG_CS_CMD_GET(x) (((uint16_t)(x) & ESC_MII_MNG_CS_CMD_MASK) >> ESC_MII_MNG_CS_CMD_SHIFT) + +/* + * PHY_ADDR (RO) + * + * PHY address of port 0 + * (this is equal to the PHY address offset, if the + * PHY addresses are consecutive) + * IP Core since V3.0.0/3.00c: + * Translation 0x0512[7]=0: + * Register 0x0510[7:3] shows PHY address of + * port 0 + * Translation 0x0512[7]=1: + * Register 0x0510[7:3] shows the PHY address + * which will be used for port 0-3 as requested + * by 0x0512[4:0] (valid values 0-3) + */ +#define ESC_MII_MNG_CS_PHY_ADDR_MASK (0xF8U) +#define ESC_MII_MNG_CS_PHY_ADDR_SHIFT (3U) +#define ESC_MII_MNG_CS_PHY_ADDR_GET(x) (((uint16_t)(x) & ESC_MII_MNG_CS_PHY_ADDR_MASK) >> ESC_MII_MNG_CS_PHY_ADDR_SHIFT) + +/* + * LINK_DC (RO) + * + * MI link detection and configuration: + * 0:Disabled for all ports + * 1:Enabled for at least one MII port, refer + * to PHY Port Status (0x0518 ff.) for + * details + */ +#define ESC_MII_MNG_CS_LINK_DC_MASK (0x4U) +#define ESC_MII_MNG_CS_LINK_DC_SHIFT (2U) +#define ESC_MII_MNG_CS_LINK_DC_GET(x) (((uint16_t)(x) & ESC_MII_MNG_CS_LINK_DC_MASK) >> ESC_MII_MNG_CS_LINK_DC_SHIFT) + +/* + * PDI (RO) + * + * Management Interface can be controlled by + * PDI (registers 0x0516-0x0517): + * 0:Only ECAT control + * 1:PDI control possible + */ +#define ESC_MII_MNG_CS_PDI_MASK (0x2U) +#define ESC_MII_MNG_CS_PDI_SHIFT (1U) +#define ESC_MII_MNG_CS_PDI_GET(x) (((uint16_t)(x) & ESC_MII_MNG_CS_PDI_MASK) >> ESC_MII_MNG_CS_PDI_SHIFT) + +/* + * WEN (RO) + * + * Write enable*: + * 0:Write disabled + * 1:Write enabled + * This bit is always 1 if PDI has MI control. + * ET1100-0000/-0001 exception: + * Bit is not always 1 if PDI has MI control, and + * bit is writable by PDI. + */ +#define ESC_MII_MNG_CS_WEN_MASK (0x1U) +#define ESC_MII_MNG_CS_WEN_SHIFT (0U) +#define ESC_MII_MNG_CS_WEN_GET(x) (((uint16_t)(x) & ESC_MII_MNG_CS_WEN_MASK) >> ESC_MII_MNG_CS_WEN_SHIFT) + +/* Bitfield definition for register: PHY_ADDR */ +/* + * SHOW (RW) + * + * Target PHY Address translation: + * 0:Enabled + * 1:Disabled + * Refer to 0x0512[4:0] and 0x0510[7:3] for + * details. + */ +#define ESC_PHY_ADDR_SHOW_MASK (0x80U) +#define ESC_PHY_ADDR_SHOW_SHIFT (7U) +#define ESC_PHY_ADDR_SHOW_SET(x) (((uint8_t)(x) << ESC_PHY_ADDR_SHOW_SHIFT) & ESC_PHY_ADDR_SHOW_MASK) +#define ESC_PHY_ADDR_SHOW_GET(x) (((uint8_t)(x) & ESC_PHY_ADDR_SHOW_MASK) >> ESC_PHY_ADDR_SHOW_SHIFT) + +/* + * ADDR (RW) + * + * Target PHY Address + * Translation 0x0512[7]=0: + * 0-3:Target PHY Addresses 0-3 are used + * to access the PHYs at port 0-3, when + * the PHY addresses are properly + * configured + * 4-31:The configured PHY address of port 0 + * (PHY address offset) is added to the + * Target PHY Address values 4-31 + * when accessing a PHY + * Translation 0x0512[7]=1: + * 0-31:Target PHY Addresses is used when + * accessing a PHY without translation + */ +#define ESC_PHY_ADDR_ADDR_MASK (0x1FU) +#define ESC_PHY_ADDR_ADDR_SHIFT (0U) +#define ESC_PHY_ADDR_ADDR_SET(x) (((uint8_t)(x) << ESC_PHY_ADDR_ADDR_SHIFT) & ESC_PHY_ADDR_ADDR_MASK) +#define ESC_PHY_ADDR_ADDR_GET(x) (((uint8_t)(x) & ESC_PHY_ADDR_ADDR_MASK) >> ESC_PHY_ADDR_ADDR_SHIFT) + +/* Bitfield definition for register: PHY_REG_ADDR */ +/* + * ADDR (RW) + * + * Address of PHY Register that shall be + * read/written + */ +#define ESC_PHY_REG_ADDR_ADDR_MASK (0x1FU) +#define ESC_PHY_REG_ADDR_ADDR_SHIFT (0U) +#define ESC_PHY_REG_ADDR_ADDR_SET(x) (((uint8_t)(x) << ESC_PHY_REG_ADDR_ADDR_SHIFT) & ESC_PHY_REG_ADDR_ADDR_MASK) +#define ESC_PHY_REG_ADDR_ADDR_GET(x) (((uint8_t)(x) & ESC_PHY_REG_ADDR_ADDR_MASK) >> ESC_PHY_REG_ADDR_ADDR_SHIFT) + +/* Bitfield definition for register: PHY_DATA */ +/* + * DATA (RW) + * + * PHY Read/Write Data + */ +#define ESC_PHY_DATA_DATA_MASK (0xFFFFU) +#define ESC_PHY_DATA_DATA_SHIFT (0U) +#define ESC_PHY_DATA_DATA_SET(x) (((uint16_t)(x) << ESC_PHY_DATA_DATA_SHIFT) & ESC_PHY_DATA_DATA_MASK) +#define ESC_PHY_DATA_DATA_GET(x) (((uint16_t)(x) & ESC_PHY_DATA_DATA_MASK) >> ESC_PHY_DATA_DATA_SHIFT) + +/* Bitfield definition for register: MIIM_ECAT_ACC_STAT */ +/* + * ACC (RO) + * + * Access to MII management: + * 0:ECAT enables PDI takeover of MII + * management interface + * 1:ECAT claims exclusive access to MII + * management interface + */ +#define ESC_MIIM_ECAT_ACC_STAT_ACC_MASK (0x1U) +#define ESC_MIIM_ECAT_ACC_STAT_ACC_SHIFT (0U) +#define ESC_MIIM_ECAT_ACC_STAT_ACC_GET(x) (((uint8_t)(x) & ESC_MIIM_ECAT_ACC_STAT_ACC_MASK) >> ESC_MIIM_ECAT_ACC_STAT_ACC_SHIFT) + +/* Bitfield definition for register: MIIM_PDI_ACC_STAT */ +/* + * FORCE (RO) + * + * Force PDI Access State: + * 0:Do not change Bit 0x0517[0] + * 1:Reset Bit 0x0517[0] to 0 + */ +#define ESC_MIIM_PDI_ACC_STAT_FORCE_MASK (0x2U) +#define ESC_MIIM_PDI_ACC_STAT_FORCE_SHIFT (1U) +#define ESC_MIIM_PDI_ACC_STAT_FORCE_GET(x) (((uint8_t)(x) & ESC_MIIM_PDI_ACC_STAT_FORCE_MASK) >> ESC_MIIM_PDI_ACC_STAT_FORCE_SHIFT) + +/* + * ACC (RW) + * + * Access to MII management: + * 0:ECAT has access to MII management + * 1:PDI has access to MII management + */ +#define ESC_MIIM_PDI_ACC_STAT_ACC_MASK (0x1U) +#define ESC_MIIM_PDI_ACC_STAT_ACC_SHIFT (0U) +#define ESC_MIIM_PDI_ACC_STAT_ACC_SET(x) (((uint8_t)(x) << ESC_MIIM_PDI_ACC_STAT_ACC_SHIFT) & ESC_MIIM_PDI_ACC_STAT_ACC_MASK) +#define ESC_MIIM_PDI_ACC_STAT_ACC_GET(x) (((uint8_t)(x) & ESC_MIIM_PDI_ACC_STAT_ACC_MASK) >> ESC_MIIM_PDI_ACC_STAT_ACC_SHIFT) + +/* Bitfield definition for register array: PHY_STAT */ +/* + * PCU (RW) + * + * PHY configuration updated: + * 0:No update + * 1:PHY configuration was updated + * Cleared by writing any value to at least one + * of the PHY Port y Status registers. + */ +#define ESC_PHY_STAT_PCU_MASK (0x20U) +#define ESC_PHY_STAT_PCU_SHIFT (5U) +#define ESC_PHY_STAT_PCU_SET(x) (((uint8_t)(x) << ESC_PHY_STAT_PCU_SHIFT) & ESC_PHY_STAT_PCU_MASK) +#define ESC_PHY_STAT_PCU_GET(x) (((uint8_t)(x) & ESC_PHY_STAT_PCU_MASK) >> ESC_PHY_STAT_PCU_SHIFT) + +/* + * LPE (RO) + * + * Link partner error: + * 0:No error detected + * 1:Link partner error + */ +#define ESC_PHY_STAT_LPE_MASK (0x10U) +#define ESC_PHY_STAT_LPE_SHIFT (4U) +#define ESC_PHY_STAT_LPE_GET(x) (((uint8_t)(x) & ESC_PHY_STAT_LPE_MASK) >> ESC_PHY_STAT_LPE_SHIFT) + +/* + * RE (RW) + * + * Read error: + * 0:No read error occurred + * 1:A read error has occurred + * Cleared by writing any value to at least one + * of the PHY Port y Status registers. + */ +#define ESC_PHY_STAT_RE_MASK (0x8U) +#define ESC_PHY_STAT_RE_SHIFT (3U) +#define ESC_PHY_STAT_RE_SET(x) (((uint8_t)(x) << ESC_PHY_STAT_RE_SHIFT) & ESC_PHY_STAT_RE_MASK) +#define ESC_PHY_STAT_RE_GET(x) (((uint8_t)(x) & ESC_PHY_STAT_RE_MASK) >> ESC_PHY_STAT_RE_SHIFT) + +/* + * LSE (RO) + * + * Link status error: + * 0:No error + * 1:Link error, link inhibited + */ +#define ESC_PHY_STAT_LSE_MASK (0x4U) +#define ESC_PHY_STAT_LSE_SHIFT (2U) +#define ESC_PHY_STAT_LSE_GET(x) (((uint8_t)(x) & ESC_PHY_STAT_LSE_MASK) >> ESC_PHY_STAT_LSE_SHIFT) + +/* + * LS (RO) + * + * Link status (100 Mbit/s, Full Duplex, Auto + * negotiation): + * 0:No link + * 1:Link detected + */ +#define ESC_PHY_STAT_LS_MASK (0x2U) +#define ESC_PHY_STAT_LS_SHIFT (1U) +#define ESC_PHY_STAT_LS_GET(x) (((uint8_t)(x) & ESC_PHY_STAT_LS_MASK) >> ESC_PHY_STAT_LS_SHIFT) + +/* + * PLS (RO) + * + * Physical link status (PHY status register 1.2): + * 0:No physical link + * 1:Physical link detected + */ +#define ESC_PHY_STAT_PLS_MASK (0x1U) +#define ESC_PHY_STAT_PLS_SHIFT (0U) +#define ESC_PHY_STAT_PLS_GET(x) (((uint8_t)(x) & ESC_PHY_STAT_PLS_MASK) >> ESC_PHY_STAT_PLS_SHIFT) + +/* Bitfield definition for register of struct array FMMU: LOGIC_START_ADDR */ +/* + * ADDR (RO) + * + * Logical start address within the EtherCAT + * Address Space. + */ +#define ESC_FMMU_LOGIC_START_ADDR_ADDR_MASK (0xFFFFFFFFUL) +#define ESC_FMMU_LOGIC_START_ADDR_ADDR_SHIFT (0U) +#define ESC_FMMU_LOGIC_START_ADDR_ADDR_GET(x) (((uint32_t)(x) & ESC_FMMU_LOGIC_START_ADDR_ADDR_MASK) >> ESC_FMMU_LOGIC_START_ADDR_ADDR_SHIFT) + +/* Bitfield definition for register of struct array FMMU: LENGTH */ +/* + * OFFSET (RO) + * + * Offset from the first logical FMMU byte to the + * last FMMU byte + 1 (e.g., if two bytes are + * used, then this parameter shall contain 2) + */ +#define ESC_FMMU_LENGTH_OFFSET_MASK (0xFFFFU) +#define ESC_FMMU_LENGTH_OFFSET_SHIFT (0U) +#define ESC_FMMU_LENGTH_OFFSET_GET(x) (((uint16_t)(x) & ESC_FMMU_LENGTH_OFFSET_MASK) >> ESC_FMMU_LENGTH_OFFSET_SHIFT) + +/* Bitfield definition for register of struct array FMMU: LOGIC_START_BIT */ +/* + * START (RO) + * + * Logical starting bit that shall be mapped (bits + * are counted from least significant bit 0 to + * most significant bit 7) + */ +#define ESC_FMMU_LOGIC_START_BIT_START_MASK (0x7U) +#define ESC_FMMU_LOGIC_START_BIT_START_SHIFT (0U) +#define ESC_FMMU_LOGIC_START_BIT_START_GET(x) (((uint8_t)(x) & ESC_FMMU_LOGIC_START_BIT_START_MASK) >> ESC_FMMU_LOGIC_START_BIT_START_SHIFT) + +/* Bitfield definition for register of struct array FMMU: LOGIC_STOP_BIT */ +/* + * STOP (RO) + * + * Last logical bit that shall be mapped (bits are + * counted from least significant bit 0 to most + * significant bit 7) + */ +#define ESC_FMMU_LOGIC_STOP_BIT_STOP_MASK (0x7U) +#define ESC_FMMU_LOGIC_STOP_BIT_STOP_SHIFT (0U) +#define ESC_FMMU_LOGIC_STOP_BIT_STOP_GET(x) (((uint8_t)(x) & ESC_FMMU_LOGIC_STOP_BIT_STOP_MASK) >> ESC_FMMU_LOGIC_STOP_BIT_STOP_SHIFT) + +/* Bitfield definition for register of struct array FMMU: PHYSICAL_START_ADDR */ +/* + * ADDR (RO) + * + * Physical Start Address (mapped to logical + * Start address) + */ +#define ESC_FMMU_PHYSICAL_START_ADDR_ADDR_MASK (0xFFFFU) +#define ESC_FMMU_PHYSICAL_START_ADDR_ADDR_SHIFT (0U) +#define ESC_FMMU_PHYSICAL_START_ADDR_ADDR_GET(x) (((uint16_t)(x) & ESC_FMMU_PHYSICAL_START_ADDR_ADDR_MASK) >> ESC_FMMU_PHYSICAL_START_ADDR_ADDR_SHIFT) + +/* Bitfield definition for register of struct array FMMU: PHYSICAL_START_BIT */ +/* + * START (RO) + * + * Physical starting bit as target of logical start + * bit mapping (bits are counted from least + * significant bit 0 to most significant bit 7) + */ +#define ESC_FMMU_PHYSICAL_START_BIT_START_MASK (0x7U) +#define ESC_FMMU_PHYSICAL_START_BIT_START_SHIFT (0U) +#define ESC_FMMU_PHYSICAL_START_BIT_START_GET(x) (((uint8_t)(x) & ESC_FMMU_PHYSICAL_START_BIT_START_MASK) >> ESC_FMMU_PHYSICAL_START_BIT_START_SHIFT) + +/* Bitfield definition for register of struct array FMMU: TYPE */ +/* + * MAP_WR (RO) + * + * 0:Ignore mapping for write accesses + * 1:Use mapping for write accesses + */ +#define ESC_FMMU_TYPE_MAP_WR_MASK (0x2U) +#define ESC_FMMU_TYPE_MAP_WR_SHIFT (1U) +#define ESC_FMMU_TYPE_MAP_WR_GET(x) (((uint8_t)(x) & ESC_FMMU_TYPE_MAP_WR_MASK) >> ESC_FMMU_TYPE_MAP_WR_SHIFT) + +/* + * MAP_RD (RO) + * + * 0:Ignore mapping for read accesses + * 1:Use mapping for read accesses + */ +#define ESC_FMMU_TYPE_MAP_RD_MASK (0x1U) +#define ESC_FMMU_TYPE_MAP_RD_SHIFT (0U) +#define ESC_FMMU_TYPE_MAP_RD_GET(x) (((uint8_t)(x) & ESC_FMMU_TYPE_MAP_RD_MASK) >> ESC_FMMU_TYPE_MAP_RD_SHIFT) + +/* Bitfield definition for register of struct array FMMU: ACTIVATE */ +/* + * ACT (RO) + * + * 0:FMMU deactivated + * 1:FMMU activated. FMMU checks + * logically addressed blocks to be + * mapped according to configured + * mapping + */ +#define ESC_FMMU_ACTIVATE_ACT_MASK (0x1U) +#define ESC_FMMU_ACTIVATE_ACT_SHIFT (0U) +#define ESC_FMMU_ACTIVATE_ACT_GET(x) (((uint8_t)(x) & ESC_FMMU_ACTIVATE_ACT_MASK) >> ESC_FMMU_ACTIVATE_ACT_SHIFT) + +/* Bitfield definition for register of struct array SYNCM: PHYSICAL_START_ADDR */ +/* + * ADDR (RO) + * + * First byte that will be handled by + * SyncManager + */ +#define ESC_SYNCM_PHYSICAL_START_ADDR_ADDR_MASK (0xFFFFU) +#define ESC_SYNCM_PHYSICAL_START_ADDR_ADDR_SHIFT (0U) +#define ESC_SYNCM_PHYSICAL_START_ADDR_ADDR_GET(x) (((uint16_t)(x) & ESC_SYNCM_PHYSICAL_START_ADDR_ADDR_MASK) >> ESC_SYNCM_PHYSICAL_START_ADDR_ADDR_SHIFT) + +/* Bitfield definition for register of struct array SYNCM: LENGTH */ +/* + * LEN (RO) + * + * Number of bytes assigned to SyncManager + * (shall be greater than 1, otherwise + * SyncManager is not activated. If set to 1, only + * Watchdog Trigger is generated if configured) + */ +#define ESC_SYNCM_LENGTH_LEN_MASK (0xFFFFU) +#define ESC_SYNCM_LENGTH_LEN_SHIFT (0U) +#define ESC_SYNCM_LENGTH_LEN_GET(x) (((uint16_t)(x) & ESC_SYNCM_LENGTH_LEN_MASK) >> ESC_SYNCM_LENGTH_LEN_SHIFT) + +/* Bitfield definition for register of struct array SYNCM: CONTROL */ +/* + * WDG_TRG_EN (RO) + * + * Watchdog Trigger Enable: + * 0:Disabled + * 1:Enabled + */ +#define ESC_SYNCM_CONTROL_WDG_TRG_EN_MASK (0x40U) +#define ESC_SYNCM_CONTROL_WDG_TRG_EN_SHIFT (6U) +#define ESC_SYNCM_CONTROL_WDG_TRG_EN_GET(x) (((uint8_t)(x) & ESC_SYNCM_CONTROL_WDG_TRG_EN_MASK) >> ESC_SYNCM_CONTROL_WDG_TRG_EN_SHIFT) + +/* + * INT_AL (RO) + * + * Interrupt in AL Event Request Register: + * 0:Disabled + * 1:Enabled + */ +#define ESC_SYNCM_CONTROL_INT_AL_MASK (0x20U) +#define ESC_SYNCM_CONTROL_INT_AL_SHIFT (5U) +#define ESC_SYNCM_CONTROL_INT_AL_GET(x) (((uint8_t)(x) & ESC_SYNCM_CONTROL_INT_AL_MASK) >> ESC_SYNCM_CONTROL_INT_AL_SHIFT) + +/* + * INT_ECAT (RO) + * + * Interrupt in ECAT Event Request Register: + * 0:Disabled + * 1:Enabled + */ +#define ESC_SYNCM_CONTROL_INT_ECAT_MASK (0x10U) +#define ESC_SYNCM_CONTROL_INT_ECAT_SHIFT (4U) +#define ESC_SYNCM_CONTROL_INT_ECAT_GET(x) (((uint8_t)(x) & ESC_SYNCM_CONTROL_INT_ECAT_MASK) >> ESC_SYNCM_CONTROL_INT_ECAT_SHIFT) + +/* + * DIR (RO) + * + * Direction: + * 00:Read:ECAT read access, PDI write + * access. + * 01:Write:ECAT write access, PDI read + * access. + * 10:Reserved + * 11:Reserved + */ +#define ESC_SYNCM_CONTROL_DIR_MASK (0xCU) +#define ESC_SYNCM_CONTROL_DIR_SHIFT (2U) +#define ESC_SYNCM_CONTROL_DIR_GET(x) (((uint8_t)(x) & ESC_SYNCM_CONTROL_DIR_MASK) >> ESC_SYNCM_CONTROL_DIR_SHIFT) + +/* + * OP_MODE (RO) + * + * Operation Mode: + * 00:Buffered (3 buffer mode) + * 01:Reserved + * 10:Mailbox (Single buffer mode) + * 11:Reserved + */ +#define ESC_SYNCM_CONTROL_OP_MODE_MASK (0x3U) +#define ESC_SYNCM_CONTROL_OP_MODE_SHIFT (0U) +#define ESC_SYNCM_CONTROL_OP_MODE_GET(x) (((uint8_t)(x) & ESC_SYNCM_CONTROL_OP_MODE_MASK) >> ESC_SYNCM_CONTROL_OP_MODE_SHIFT) + +/* Bitfield definition for register of struct array SYNCM: STATUS */ +/* + * WB_INUSE (RO) + * + * Write buffer in use (opened) + */ +#define ESC_SYNCM_STATUS_WB_INUSE_MASK (0x80U) +#define ESC_SYNCM_STATUS_WB_INUSE_SHIFT (7U) +#define ESC_SYNCM_STATUS_WB_INUSE_GET(x) (((uint8_t)(x) & ESC_SYNCM_STATUS_WB_INUSE_MASK) >> ESC_SYNCM_STATUS_WB_INUSE_SHIFT) + +/* + * RB_INUSE (RO) + * + * Read buffer in use (opened) + */ +#define ESC_SYNCM_STATUS_RB_INUSE_MASK (0x40U) +#define ESC_SYNCM_STATUS_RB_INUSE_SHIFT (6U) +#define ESC_SYNCM_STATUS_RB_INUSE_GET(x) (((uint8_t)(x) & ESC_SYNCM_STATUS_RB_INUSE_MASK) >> ESC_SYNCM_STATUS_RB_INUSE_SHIFT) + +/* + * BUF_MODE (RO) + * + * Buffered mode:buffer status (last written + * buffer): + * 00:1 + * st buffer + * 01:2 + * nd buffer + * 10:3 + * rd buffer + * 11:(no buffer written) + * Mailbox mode:reserved + */ +#define ESC_SYNCM_STATUS_BUF_MODE_MASK (0x30U) +#define ESC_SYNCM_STATUS_BUF_MODE_SHIFT (4U) +#define ESC_SYNCM_STATUS_BUF_MODE_GET(x) (((uint8_t)(x) & ESC_SYNCM_STATUS_BUF_MODE_MASK) >> ESC_SYNCM_STATUS_BUF_MODE_SHIFT) + +/* + * MBX_MODE (RO) + * + * Mailbox mode:mailbox status: + * 0:Mailbox empty + * 1:Mailbox full + * Buffered mode:reserved + */ +#define ESC_SYNCM_STATUS_MBX_MODE_MASK (0x8U) +#define ESC_SYNCM_STATUS_MBX_MODE_SHIFT (3U) +#define ESC_SYNCM_STATUS_MBX_MODE_GET(x) (((uint8_t)(x) & ESC_SYNCM_STATUS_MBX_MODE_MASK) >> ESC_SYNCM_STATUS_MBX_MODE_SHIFT) + +/* + * INT_RD (RO) + * + * Interrupt Read: + * 1:Interrupt after buffer was completely and + * successfully read + * 0:Interrupt cleared after first byte of buffer + * was written + * NOTE:This interrupt is signalled to the writing + * side if enabled in the SM Control register + */ +#define ESC_SYNCM_STATUS_INT_RD_MASK (0x2U) +#define ESC_SYNCM_STATUS_INT_RD_SHIFT (1U) +#define ESC_SYNCM_STATUS_INT_RD_GET(x) (((uint8_t)(x) & ESC_SYNCM_STATUS_INT_RD_MASK) >> ESC_SYNCM_STATUS_INT_RD_SHIFT) + +/* + * INT_WR (RO) + * + * Interrupt Write: + * 1:Interrupt after buffer was completely and + * successfully written + * 0:Interrupt cleared after first byte of buffer + * was read + * NOTE:This interrupt is signalled to the reading + * side if enabled in the SM Control register + */ +#define ESC_SYNCM_STATUS_INT_WR_MASK (0x1U) +#define ESC_SYNCM_STATUS_INT_WR_SHIFT (0U) +#define ESC_SYNCM_STATUS_INT_WR_GET(x) (((uint8_t)(x) & ESC_SYNCM_STATUS_INT_WR_MASK) >> ESC_SYNCM_STATUS_INT_WR_SHIFT) + +/* Bitfield definition for register of struct array SYNCM: ACTIVATE */ +/* + * LATCH_PDI (RO) + * + * Latch Event PDI: + * 0:No + * 1:Generate Latch events when PDI issues + * a buffer exchange or when PDI + * accesses buffer start address + */ +#define ESC_SYNCM_ACTIVATE_LATCH_PDI_MASK (0x80U) +#define ESC_SYNCM_ACTIVATE_LATCH_PDI_SHIFT (7U) +#define ESC_SYNCM_ACTIVATE_LATCH_PDI_GET(x) (((uint8_t)(x) & ESC_SYNCM_ACTIVATE_LATCH_PDI_MASK) >> ESC_SYNCM_ACTIVATE_LATCH_PDI_SHIFT) + +/* + * LATCH_ECAT (RO) + * + * Latch Event ECAT: + * 0:No + * 1:Generate Latch event when EtherCAT + * master issues a buffer exchange + */ +#define ESC_SYNCM_ACTIVATE_LATCH_ECAT_MASK (0x40U) +#define ESC_SYNCM_ACTIVATE_LATCH_ECAT_SHIFT (6U) +#define ESC_SYNCM_ACTIVATE_LATCH_ECAT_GET(x) (((uint8_t)(x) & ESC_SYNCM_ACTIVATE_LATCH_ECAT_MASK) >> ESC_SYNCM_ACTIVATE_LATCH_ECAT_SHIFT) + +/* + * REPEAT (RO) + * + * Repeat Request: + * A toggle of Repeat Request means that a + * mailbox retry is needed (primarily used in + * conjunction with ECAT Read Mailbox) + */ +#define ESC_SYNCM_ACTIVATE_REPEAT_MASK (0x2U) +#define ESC_SYNCM_ACTIVATE_REPEAT_SHIFT (1U) +#define ESC_SYNCM_ACTIVATE_REPEAT_GET(x) (((uint8_t)(x) & ESC_SYNCM_ACTIVATE_REPEAT_MASK) >> ESC_SYNCM_ACTIVATE_REPEAT_SHIFT) + +/* + * EN (RW) + * + * SyncManager Enable/Disable: + * 0:Disable:Access to Memory without + * SyncManager control + * 1:Enable:SyncManager is active and + * controls Memory area set in + * configuration + */ +#define ESC_SYNCM_ACTIVATE_EN_MASK (0x1U) +#define ESC_SYNCM_ACTIVATE_EN_SHIFT (0U) +#define ESC_SYNCM_ACTIVATE_EN_SET(x) (((uint8_t)(x) << ESC_SYNCM_ACTIVATE_EN_SHIFT) & ESC_SYNCM_ACTIVATE_EN_MASK) +#define ESC_SYNCM_ACTIVATE_EN_GET(x) (((uint8_t)(x) & ESC_SYNCM_ACTIVATE_EN_MASK) >> ESC_SYNCM_ACTIVATE_EN_SHIFT) + +/* Bitfield definition for register of struct array SYNCM: PDI_CTRL */ +/* + * REPEAT_ACK (RW) + * + * Repeat Ack: + * If this is set to the same value as that set by + * Repeat Request, the PDI acknowledges the + * execution of a previous set Repeat request. + */ +#define ESC_SYNCM_PDI_CTRL_REPEAT_ACK_MASK (0x2U) +#define ESC_SYNCM_PDI_CTRL_REPEAT_ACK_SHIFT (1U) +#define ESC_SYNCM_PDI_CTRL_REPEAT_ACK_SET(x) (((uint8_t)(x) << ESC_SYNCM_PDI_CTRL_REPEAT_ACK_SHIFT) & ESC_SYNCM_PDI_CTRL_REPEAT_ACK_MASK) +#define ESC_SYNCM_PDI_CTRL_REPEAT_ACK_GET(x) (((uint8_t)(x) & ESC_SYNCM_PDI_CTRL_REPEAT_ACK_MASK) >> ESC_SYNCM_PDI_CTRL_REPEAT_ACK_SHIFT) + +/* + * DEACT (RW) + * + * Deactivate SyncManager: + * Read: + * 0:Normal operation, SyncManager + * activated. + * 1:SyncManager deactivated and reset. + * SyncManager locks access to Memory + * area. + * Write: + * 0:Activate SyncManager + * 1:Request SyncManager deactivation + * NOTE:Writing 1 is delayed until the end of the + * frame, which is currently processed. + */ +#define ESC_SYNCM_PDI_CTRL_DEACT_MASK (0x1U) +#define ESC_SYNCM_PDI_CTRL_DEACT_SHIFT (0U) +#define ESC_SYNCM_PDI_CTRL_DEACT_SET(x) (((uint8_t)(x) << ESC_SYNCM_PDI_CTRL_DEACT_SHIFT) & ESC_SYNCM_PDI_CTRL_DEACT_MASK) +#define ESC_SYNCM_PDI_CTRL_DEACT_GET(x) (((uint8_t)(x) & ESC_SYNCM_PDI_CTRL_DEACT_MASK) >> ESC_SYNCM_PDI_CTRL_DEACT_SHIFT) + +/* Bitfield definition for register array: RCV_TIME */ +/* + * LT (RO) + * + * Local time at the beginning of the last receive + * frame containing a write access to register + * 0x0900. + */ +#define ESC_RCV_TIME_LT_MASK (0xFFFFFF00UL) +#define ESC_RCV_TIME_LT_SHIFT (8U) +#define ESC_RCV_TIME_LT_GET(x) (((uint32_t)(x) & ESC_RCV_TIME_LT_MASK) >> ESC_RCV_TIME_LT_SHIFT) + +/* + * REQ (RO) + * + * Write: + * A write access to register 0x0900 with + * BWR or FPWR latches the local time at + * the beginning of the receive frame (start + * first bit of preamble) at each port. + * Write (ESC20, ET1200 exception): + * A write access latches the local time at + * the beginning of the receive frame at + * port 0. It enables the time stamping at + * the other ports. + * Read: + * Local time at the beginning of the last + * receive frame containing a write access + * to this register. + * NOTE:FPWR requires an address match for + * accessing this register like any FPWR command. + * All write commands with address match will + * increment the working counter (e.g., APWR), but + * they will not trigger receive time latching. + */ +#define ESC_RCV_TIME_REQ_MASK (0xFFU) +#define ESC_RCV_TIME_REQ_SHIFT (0U) +#define ESC_RCV_TIME_REQ_GET(x) (((uint32_t)(x) & ESC_RCV_TIME_REQ_MASK) >> ESC_RCV_TIME_REQ_SHIFT) + +/* Bitfield definition for register: SYS_TIME */ +/* + * ST (RW) + * + */ +#define ESC_SYS_TIME_ST_MASK (0xFFFFFFFFFFFFFFFFULL) +#define ESC_SYS_TIME_ST_SHIFT (0U) +#define ESC_SYS_TIME_ST_SET(x) (((uint64_t)(x) << ESC_SYS_TIME_ST_SHIFT) & ESC_SYS_TIME_ST_MASK) +#define ESC_SYS_TIME_ST_GET(x) (((uint64_t)(x) & ESC_SYS_TIME_ST_MASK) >> ESC_SYS_TIME_ST_SHIFT) + +/* Bitfield definition for register: RCVT_ECAT_PU */ +/* + * LT (RO) + * + * Local time at the beginning of a frame (start + * first bit of preamble) received at the ECAT + * Processing Unit containing a write access to + * register 0x0900 + * NOTE:E.g., if port 0 is open, this register reflects + * the Receive Time Port 0 as a 64 Bit value. + * Any valid EtherCAT write access to register + * 0x0900 triggers latching, not only BWR/FPWR + * commands as with register 0x0900. + */ +#define ESC_RCVT_ECAT_PU_LT_MASK (0xFFFFFFFFFFFFFFFFULL) +#define ESC_RCVT_ECAT_PU_LT_SHIFT (0U) +#define ESC_RCVT_ECAT_PU_LT_GET(x) (((uint64_t)(x) & ESC_RCVT_ECAT_PU_LT_MASK) >> ESC_RCVT_ECAT_PU_LT_SHIFT) + +/* Bitfield definition for register: SYS_TIME_OFFSET */ +/* + * OFFSET (RW) + * + * Difference between local time and System + * Time. Offset is added to the local time. + */ +#define ESC_SYS_TIME_OFFSET_OFFSET_MASK (0xFFFFFFFFFFFFFFFFULL) +#define ESC_SYS_TIME_OFFSET_OFFSET_SHIFT (0U) +#define ESC_SYS_TIME_OFFSET_OFFSET_SET(x) (((uint64_t)(x) << ESC_SYS_TIME_OFFSET_OFFSET_SHIFT) & ESC_SYS_TIME_OFFSET_OFFSET_MASK) +#define ESC_SYS_TIME_OFFSET_OFFSET_GET(x) (((uint64_t)(x) & ESC_SYS_TIME_OFFSET_OFFSET_MASK) >> ESC_SYS_TIME_OFFSET_OFFSET_SHIFT) + +/* Bitfield definition for register: SYS_TIME_DELAY */ +/* + * DLY (RW) + * + * Delay between Reference Clock and the + * ESC + */ +#define ESC_SYS_TIME_DELAY_DLY_MASK (0xFFFFFFFFUL) +#define ESC_SYS_TIME_DELAY_DLY_SHIFT (0U) +#define ESC_SYS_TIME_DELAY_DLY_SET(x) (((uint32_t)(x) << ESC_SYS_TIME_DELAY_DLY_SHIFT) & ESC_SYS_TIME_DELAY_DLY_MASK) +#define ESC_SYS_TIME_DELAY_DLY_GET(x) (((uint32_t)(x) & ESC_SYS_TIME_DELAY_DLY_MASK) >> ESC_SYS_TIME_DELAY_DLY_SHIFT) + +/* Bitfield definition for register: SYS_TIME_DIFF */ +/* + * DIFF (RO) + * + * 0:Local copy of System Time less than + * received System Time + * 1:Local copy of System Time greater than + * or equal to received System Time + */ +#define ESC_SYS_TIME_DIFF_DIFF_MASK (0x80000000UL) +#define ESC_SYS_TIME_DIFF_DIFF_SHIFT (31U) +#define ESC_SYS_TIME_DIFF_DIFF_GET(x) (((uint32_t)(x) & ESC_SYS_TIME_DIFF_DIFF_MASK) >> ESC_SYS_TIME_DIFF_DIFF_SHIFT) + +/* + * NUM (RO) + * + * Mean difference between local copy of + * System Time and received System Time + * values + * Difference = Received System Time – + * local copy of System Time + */ +#define ESC_SYS_TIME_DIFF_NUM_MASK (0x7FFFFFFFUL) +#define ESC_SYS_TIME_DIFF_NUM_SHIFT (0U) +#define ESC_SYS_TIME_DIFF_NUM_GET(x) (((uint32_t)(x) & ESC_SYS_TIME_DIFF_NUM_MASK) >> ESC_SYS_TIME_DIFF_NUM_SHIFT) + +/* Bitfield definition for register: SPD_CNT_START */ +/* + * BW (RW) + * + * Bandwidth for adjustment of local copy of + * System Time (larger values → smaller + * bandwidth and smoother adjustment) + * A write access resets System Time + * Difference (0x092C:0x092F) and Speed + * Counter Diff (0x0932:0x0933). + * Valid values:0x0080 to 0x3FFF + */ +#define ESC_SPD_CNT_START_BW_MASK (0x7FFFU) +#define ESC_SPD_CNT_START_BW_SHIFT (0U) +#define ESC_SPD_CNT_START_BW_SET(x) (((uint16_t)(x) << ESC_SPD_CNT_START_BW_SHIFT) & ESC_SPD_CNT_START_BW_MASK) +#define ESC_SPD_CNT_START_BW_GET(x) (((uint16_t)(x) & ESC_SPD_CNT_START_BW_MASK) >> ESC_SPD_CNT_START_BW_SHIFT) + +/* Bitfield definition for register: SPD_CNT_DIFF */ +/* + * DIFF (RO) + * + * Representation of the deviation between + * local clock period and Reference Clock's + * clock period (representation:two's + * complement) + * Range:±(Speed Counter Start – 0x7F) + */ +#define ESC_SPD_CNT_DIFF_DIFF_MASK (0xFFFFU) +#define ESC_SPD_CNT_DIFF_DIFF_SHIFT (0U) +#define ESC_SPD_CNT_DIFF_DIFF_GET(x) (((uint16_t)(x) & ESC_SPD_CNT_DIFF_DIFF_MASK) >> ESC_SPD_CNT_DIFF_DIFF_SHIFT) + +/* Bitfield definition for register: SYS_TIME_DIFF_FD */ +/* + * DEPTH (RW) + * + * Filter depth for averaging the received + * System Time deviation + * IP Core since V2.2.0/V2.02a: + * A write access resets System Time + * Difference (0x092C:0x092F) + */ +#define ESC_SYS_TIME_DIFF_FD_DEPTH_MASK (0xFU) +#define ESC_SYS_TIME_DIFF_FD_DEPTH_SHIFT (0U) +#define ESC_SYS_TIME_DIFF_FD_DEPTH_SET(x) (((uint8_t)(x) << ESC_SYS_TIME_DIFF_FD_DEPTH_SHIFT) & ESC_SYS_TIME_DIFF_FD_DEPTH_MASK) +#define ESC_SYS_TIME_DIFF_FD_DEPTH_GET(x) (((uint8_t)(x) & ESC_SYS_TIME_DIFF_FD_DEPTH_MASK) >> ESC_SYS_TIME_DIFF_FD_DEPTH_SHIFT) + +/* Bitfield definition for register: SPD_CNT_FD */ +/* + * DEPTH (RW) + * + * Filter depth for averaging the clock period + * deviation + * IP Core since V2.2.0/V2.02a: + * A write access resets the internal speed + * counter filter + */ +#define ESC_SPD_CNT_FD_DEPTH_MASK (0xFU) +#define ESC_SPD_CNT_FD_DEPTH_SHIFT (0U) +#define ESC_SPD_CNT_FD_DEPTH_SET(x) (((uint8_t)(x) << ESC_SPD_CNT_FD_DEPTH_SHIFT) & ESC_SPD_CNT_FD_DEPTH_MASK) +#define ESC_SPD_CNT_FD_DEPTH_GET(x) (((uint8_t)(x) & ESC_SPD_CNT_FD_DEPTH_MASK) >> ESC_SPD_CNT_FD_DEPTH_SHIFT) + +/* Bitfield definition for register: RCV_TIME_LM */ +/* + * LATCH_MODE (RO) + * + * Receive Time Latch Mode: + * 0:Forwarding mode (used if frames are + * entering the ESC at port 0 first): + * Receive time stamps of ports 1-3 are + * enabled after the write access to + * 0x0900, so the following frame at ports + * 1-3 will be time stamped (this is typically + * the write frame to 0x0900 coming back + * from the network behind the ESC). + * 1:Reverse mode (used if frames are + * entering ESC at port 1-3 first): + * Receive time stamps of ports 1-3 are + * immediately taken over from the internal + * hidden time stamp registers, so the + * previous frame entering the ESC at + * ports 1-3 will be time stamped when the + * write frame to 0x0900 enters port 0 (the + * previous frame at ports 1-3 is typically + * the write frame to 0x0900 coming from + * the master, which will enable time + * stamp + */ +#define ESC_RCV_TIME_LM_LATCH_MODE_MASK (0x1U) +#define ESC_RCV_TIME_LM_LATCH_MODE_SHIFT (0U) +#define ESC_RCV_TIME_LM_LATCH_MODE_GET(x) (((uint8_t)(x) & ESC_RCV_TIME_LM_LATCH_MODE_MASK) >> ESC_RCV_TIME_LM_LATCH_MODE_SHIFT) + +/* Bitfield definition for register: CYC_UNIT_CTRL */ +/* + * LATCHI1 (RO) + * + * Latch In unit 1: + * 0:ECAT-controlled + * 1:PDI-controlled + * NOTE:Latch interrupt is routed to ECAT/PDI + * depending on this setting + */ +#define ESC_CYC_UNIT_CTRL_LATCHI1_MASK (0x20U) +#define ESC_CYC_UNIT_CTRL_LATCHI1_SHIFT (5U) +#define ESC_CYC_UNIT_CTRL_LATCHI1_GET(x) (((uint8_t)(x) & ESC_CYC_UNIT_CTRL_LATCHI1_MASK) >> ESC_CYC_UNIT_CTRL_LATCHI1_SHIFT) + +/* + * LATCHI0 (RO) + * + * Latch In unit 0: + * 0:ECAT-controlled + * 1:PDI-controlled + * NOTE:Latch interrupt is routed to ECAT/PDI + * depending on this setting. + * Always 1 (PDI-controlled) if System Time is PDIcontrolled. + */ +#define ESC_CYC_UNIT_CTRL_LATCHI0_MASK (0x10U) +#define ESC_CYC_UNIT_CTRL_LATCHI0_SHIFT (4U) +#define ESC_CYC_UNIT_CTRL_LATCHI0_GET(x) (((uint8_t)(x) & ESC_CYC_UNIT_CTRL_LATCHI0_MASK) >> ESC_CYC_UNIT_CTRL_LATCHI0_SHIFT) + +/* + * SYNCO (RO) + * + * Cyclic Unit and SYNC0 out unit control: + * 0:ECAT-controlled + * 1:PDI-controlled + */ +#define ESC_CYC_UNIT_CTRL_SYNCO_MASK (0x1U) +#define ESC_CYC_UNIT_CTRL_SYNCO_SHIFT (0U) +#define ESC_CYC_UNIT_CTRL_SYNCO_GET(x) (((uint8_t)(x) & ESC_CYC_UNIT_CTRL_SYNCO_MASK) >> ESC_CYC_UNIT_CTRL_SYNCO_SHIFT) + +/* Bitfield definition for register: SYNCO_ACT */ +/* + * SSDP (RW) + * + * SyncSignal debug pulse (Vasily bit): + * 0:Deactivated + * 1:Immediately generate one ping only on + * SYNC0-1 according to 0x0981[2:1 for + * debugging + * This bit is self-clearing, always read 0. + * All pulses are generated at the same time, + * the cycle time is ignored. The configured + * pulse length is used. + */ +#define ESC_SYNCO_ACT_SSDP_MASK (0x80U) +#define ESC_SYNCO_ACT_SSDP_SHIFT (7U) +#define ESC_SYNCO_ACT_SSDP_SET(x) (((uint8_t)(x) << ESC_SYNCO_ACT_SSDP_SHIFT) & ESC_SYNCO_ACT_SSDP_MASK) +#define ESC_SYNCO_ACT_SSDP_GET(x) (((uint8_t)(x) & ESC_SYNCO_ACT_SSDP_MASK) >> ESC_SYNCO_ACT_SSDP_SHIFT) + +/* + * NFC (RW) + * + * Near future configuration (approx.): + * 0:½ DC width future (231 ns or 263 ns) + * 1:~2.1 sec. future (231 ns) + */ +#define ESC_SYNCO_ACT_NFC_MASK (0x40U) +#define ESC_SYNCO_ACT_NFC_SHIFT (6U) +#define ESC_SYNCO_ACT_NFC_SET(x) (((uint8_t)(x) << ESC_SYNCO_ACT_NFC_SHIFT) & ESC_SYNCO_ACT_NFC_MASK) +#define ESC_SYNCO_ACT_NFC_GET(x) (((uint8_t)(x) & ESC_SYNCO_ACT_NFC_MASK) >> ESC_SYNCO_ACT_NFC_SHIFT) + +/* + * STPC (RW) + * + * Start Time plausibility check: + * 0:Disabled. SyncSignal generation if Start + * Time is reached. + * 1:Immediate SyncSignal generation if + * Start Time is outside near future (see + * 0x0981[6]) + */ +#define ESC_SYNCO_ACT_STPC_MASK (0x20U) +#define ESC_SYNCO_ACT_STPC_SHIFT (5U) +#define ESC_SYNCO_ACT_STPC_SET(x) (((uint8_t)(x) << ESC_SYNCO_ACT_STPC_SHIFT) & ESC_SYNCO_ACT_STPC_MASK) +#define ESC_SYNCO_ACT_STPC_GET(x) (((uint8_t)(x) & ESC_SYNCO_ACT_STPC_MASK) >> ESC_SYNCO_ACT_STPC_SHIFT) + +/* + * EXT (RW) + * + * Extension of Start Time Cyclic Operation + * (0x0990:0x0993): + * 0:No extension + * 1:Extend 32 bit written Start Time to 64 bit + */ +#define ESC_SYNCO_ACT_EXT_MASK (0x10U) +#define ESC_SYNCO_ACT_EXT_SHIFT (4U) +#define ESC_SYNCO_ACT_EXT_SET(x) (((uint8_t)(x) << ESC_SYNCO_ACT_EXT_SHIFT) & ESC_SYNCO_ACT_EXT_MASK) +#define ESC_SYNCO_ACT_EXT_GET(x) (((uint8_t)(x) & ESC_SYNCO_ACT_EXT_MASK) >> ESC_SYNCO_ACT_EXT_SHIFT) + +/* + * AC (RW) + * + * Auto-activation by writing Start Time Cyclic + * Operation (0x0990:0x0997): + * 0:Disabled + * 1:Auto-activation enabled. 0x0981[0] is + * set automatically after Start Time is + * written. + */ +#define ESC_SYNCO_ACT_AC_MASK (0x8U) +#define ESC_SYNCO_ACT_AC_SHIFT (3U) +#define ESC_SYNCO_ACT_AC_SET(x) (((uint8_t)(x) << ESC_SYNCO_ACT_AC_SHIFT) & ESC_SYNCO_ACT_AC_MASK) +#define ESC_SYNCO_ACT_AC_GET(x) (((uint8_t)(x) & ESC_SYNCO_ACT_AC_MASK) >> ESC_SYNCO_ACT_AC_SHIFT) + +/* + * SYNC1_GEN (RW) + * + * SYNC1 generation: + * 0:Deactivated + * 1:SYNC1 pulse is generated + */ +#define ESC_SYNCO_ACT_SYNC1_GEN_MASK (0x4U) +#define ESC_SYNCO_ACT_SYNC1_GEN_SHIFT (2U) +#define ESC_SYNCO_ACT_SYNC1_GEN_SET(x) (((uint8_t)(x) << ESC_SYNCO_ACT_SYNC1_GEN_SHIFT) & ESC_SYNCO_ACT_SYNC1_GEN_MASK) +#define ESC_SYNCO_ACT_SYNC1_GEN_GET(x) (((uint8_t)(x) & ESC_SYNCO_ACT_SYNC1_GEN_MASK) >> ESC_SYNCO_ACT_SYNC1_GEN_SHIFT) + +/* + * SYNC0_GEN (RW) + * + * SYNC0 generation: + * 0:Deactivated + * 1:SYNC0 pulse is generated + */ +#define ESC_SYNCO_ACT_SYNC0_GEN_MASK (0x2U) +#define ESC_SYNCO_ACT_SYNC0_GEN_SHIFT (1U) +#define ESC_SYNCO_ACT_SYNC0_GEN_SET(x) (((uint8_t)(x) << ESC_SYNCO_ACT_SYNC0_GEN_SHIFT) & ESC_SYNCO_ACT_SYNC0_GEN_MASK) +#define ESC_SYNCO_ACT_SYNC0_GEN_GET(x) (((uint8_t)(x) & ESC_SYNCO_ACT_SYNC0_GEN_MASK) >> ESC_SYNCO_ACT_SYNC0_GEN_SHIFT) + +/* + * SOUA (RW) + * + * Sync Out Unit activation: + * 0:Deactivated + * 1:Activated + */ +#define ESC_SYNCO_ACT_SOUA_MASK (0x1U) +#define ESC_SYNCO_ACT_SOUA_SHIFT (0U) +#define ESC_SYNCO_ACT_SOUA_SET(x) (((uint8_t)(x) << ESC_SYNCO_ACT_SOUA_SHIFT) & ESC_SYNCO_ACT_SOUA_MASK) +#define ESC_SYNCO_ACT_SOUA_GET(x) (((uint8_t)(x) & ESC_SYNCO_ACT_SOUA_MASK) >> ESC_SYNCO_ACT_SOUA_SHIFT) + +/* Bitfield definition for register: PULSE_LEN */ +/* + * LEN (RO) + * + * Pulse length of SyncSignals (in Units of + * 10ns) + * 0:Acknowledge mode:SyncSignal will be + * cleared by reading SYNC[1:0] Status + * register + */ +#define ESC_PULSE_LEN_LEN_MASK (0xFFFFU) +#define ESC_PULSE_LEN_LEN_SHIFT (0U) +#define ESC_PULSE_LEN_LEN_GET(x) (((uint16_t)(x) & ESC_PULSE_LEN_LEN_MASK) >> ESC_PULSE_LEN_LEN_SHIFT) + +/* Bitfield definition for register: ACT_STAT */ +/* + * CHK_RSLT (RO) + * + * Start Time Cyclic Operation (0x0990:0x0997) + * plausibility check result when Sync Out Unit + * was activated: + * 0:Start Time was within near future + * 1:Start Time was out of near future + * (0x0981[6]) + */ +#define ESC_ACT_STAT_CHK_RSLT_MASK (0x4U) +#define ESC_ACT_STAT_CHK_RSLT_SHIFT (2U) +#define ESC_ACT_STAT_CHK_RSLT_GET(x) (((uint8_t)(x) & ESC_ACT_STAT_CHK_RSLT_MASK) >> ESC_ACT_STAT_CHK_RSLT_SHIFT) + +/* + * SYNC1 (RO) + * + * SYNC1 activation state: + * 0:First SYNC1 pulse is not pending + * 1:First SYNC1 pulse is pending + */ +#define ESC_ACT_STAT_SYNC1_MASK (0x2U) +#define ESC_ACT_STAT_SYNC1_SHIFT (1U) +#define ESC_ACT_STAT_SYNC1_GET(x) (((uint8_t)(x) & ESC_ACT_STAT_SYNC1_MASK) >> ESC_ACT_STAT_SYNC1_SHIFT) + +/* + * SYNC0 (RO) + * + * SYNC0 activation state: + * 0:First SYNC0 pulse is not pending + * 1:First SYNC0 pulse is pending + */ +#define ESC_ACT_STAT_SYNC0_MASK (0x1U) +#define ESC_ACT_STAT_SYNC0_SHIFT (0U) +#define ESC_ACT_STAT_SYNC0_GET(x) (((uint8_t)(x) & ESC_ACT_STAT_SYNC0_MASK) >> ESC_ACT_STAT_SYNC0_SHIFT) + +/* Bitfield definition for register: SYNC0_STAT */ +/* + * ACK (RW) + * + * SYNC0 state for Acknowledge mode. + * SYNC0 in Acknowledge mode is cleared by + * reading this register from PDI, use only in + * Acknowledge mode + */ +#define ESC_SYNC0_STAT_ACK_MASK (0x1U) +#define ESC_SYNC0_STAT_ACK_SHIFT (0U) +#define ESC_SYNC0_STAT_ACK_SET(x) (((uint8_t)(x) << ESC_SYNC0_STAT_ACK_SHIFT) & ESC_SYNC0_STAT_ACK_MASK) +#define ESC_SYNC0_STAT_ACK_GET(x) (((uint8_t)(x) & ESC_SYNC0_STAT_ACK_MASK) >> ESC_SYNC0_STAT_ACK_SHIFT) + +/* Bitfield definition for register: SYNC1_STAT */ +/* + * ACK (RW) + * + * SYNC1 state for Acknowledge mode. + * SYNC1 in Acknowledge mode is cleared by + * reading this register from PDI, use only in + * Acknowledge mode + */ +#define ESC_SYNC1_STAT_ACK_MASK (0x1U) +#define ESC_SYNC1_STAT_ACK_SHIFT (0U) +#define ESC_SYNC1_STAT_ACK_SET(x) (((uint8_t)(x) << ESC_SYNC1_STAT_ACK_SHIFT) & ESC_SYNC1_STAT_ACK_MASK) +#define ESC_SYNC1_STAT_ACK_GET(x) (((uint8_t)(x) & ESC_SYNC1_STAT_ACK_MASK) >> ESC_SYNC1_STAT_ACK_SHIFT) + +/* Bitfield definition for register: START_TIME_CO */ +/* + * ST (RW) + * + * Write:Start time (System time) of cyclic + * operation in ns + * Read:System time of next SYNC0 pulse in + * ns + */ +#define ESC_START_TIME_CO_ST_MASK (0xFFFFFFFFFFFFFFFFULL) +#define ESC_START_TIME_CO_ST_SHIFT (0U) +#define ESC_START_TIME_CO_ST_SET(x) (((uint64_t)(x) << ESC_START_TIME_CO_ST_SHIFT) & ESC_START_TIME_CO_ST_MASK) +#define ESC_START_TIME_CO_ST_GET(x) (((uint64_t)(x) & ESC_START_TIME_CO_ST_MASK) >> ESC_START_TIME_CO_ST_SHIFT) + +/* Bitfield definition for register: NXT_SYNC1_PULSE */ +/* + * TIME (RO) + * + * System time of next SYNC1 pulse in ns + */ +#define ESC_NXT_SYNC1_PULSE_TIME_MASK (0xFFFFFFFFFFFFFFFFULL) +#define ESC_NXT_SYNC1_PULSE_TIME_SHIFT (0U) +#define ESC_NXT_SYNC1_PULSE_TIME_GET(x) (((uint64_t)(x) & ESC_NXT_SYNC1_PULSE_TIME_MASK) >> ESC_NXT_SYNC1_PULSE_TIME_SHIFT) + +/* Bitfield definition for register: SYNC0_CYC_TIME */ +/* + * CYC (RW) + * + * Time between two consecutive SYNC0 + * pulses in ns. + * 0:Single shot mode, generate only one + * SYNC0 pulse. + */ +#define ESC_SYNC0_CYC_TIME_CYC_MASK (0xFFFFFFFFUL) +#define ESC_SYNC0_CYC_TIME_CYC_SHIFT (0U) +#define ESC_SYNC0_CYC_TIME_CYC_SET(x) (((uint32_t)(x) << ESC_SYNC0_CYC_TIME_CYC_SHIFT) & ESC_SYNC0_CYC_TIME_CYC_MASK) +#define ESC_SYNC0_CYC_TIME_CYC_GET(x) (((uint32_t)(x) & ESC_SYNC0_CYC_TIME_CYC_MASK) >> ESC_SYNC0_CYC_TIME_CYC_SHIFT) + +/* Bitfield definition for register: SYNC1_CYC_TIME */ +/* + * CYC (RW) + * + * Time between SYNC0 pulse and SYNC1 + * pulse in ns + */ +#define ESC_SYNC1_CYC_TIME_CYC_MASK (0xFFFFFFFFUL) +#define ESC_SYNC1_CYC_TIME_CYC_SHIFT (0U) +#define ESC_SYNC1_CYC_TIME_CYC_SET(x) (((uint32_t)(x) << ESC_SYNC1_CYC_TIME_CYC_SHIFT) & ESC_SYNC1_CYC_TIME_CYC_MASK) +#define ESC_SYNC1_CYC_TIME_CYC_GET(x) (((uint32_t)(x) & ESC_SYNC1_CYC_TIME_CYC_MASK) >> ESC_SYNC1_CYC_TIME_CYC_SHIFT) + +/* Bitfield definition for register: LATCH0_CTRL */ +/* + * NEG_EDGE (RW) + * + * Latch0 negative edge: + * 0:Continuous Latch active + * 1:Single event (only first event active) + */ +#define ESC_LATCH0_CTRL_NEG_EDGE_MASK (0x2U) +#define ESC_LATCH0_CTRL_NEG_EDGE_SHIFT (1U) +#define ESC_LATCH0_CTRL_NEG_EDGE_SET(x) (((uint8_t)(x) << ESC_LATCH0_CTRL_NEG_EDGE_SHIFT) & ESC_LATCH0_CTRL_NEG_EDGE_MASK) +#define ESC_LATCH0_CTRL_NEG_EDGE_GET(x) (((uint8_t)(x) & ESC_LATCH0_CTRL_NEG_EDGE_MASK) >> ESC_LATCH0_CTRL_NEG_EDGE_SHIFT) + +/* + * POS_EDGE (RW) + * + * Latch0 positive edge: + * 0:Continuous Latch active + * 1:Single event (only first event active) + */ +#define ESC_LATCH0_CTRL_POS_EDGE_MASK (0x1U) +#define ESC_LATCH0_CTRL_POS_EDGE_SHIFT (0U) +#define ESC_LATCH0_CTRL_POS_EDGE_SET(x) (((uint8_t)(x) << ESC_LATCH0_CTRL_POS_EDGE_SHIFT) & ESC_LATCH0_CTRL_POS_EDGE_MASK) +#define ESC_LATCH0_CTRL_POS_EDGE_GET(x) (((uint8_t)(x) & ESC_LATCH0_CTRL_POS_EDGE_MASK) >> ESC_LATCH0_CTRL_POS_EDGE_SHIFT) + +/* Bitfield definition for register: LATCH1_CTRL */ +/* + * NEG_EDGE (RW) + * + * Latch1 negative edge: + * 0:Continuous Latch active + * 1:Single event (only first event active) + */ +#define ESC_LATCH1_CTRL_NEG_EDGE_MASK (0x2U) +#define ESC_LATCH1_CTRL_NEG_EDGE_SHIFT (1U) +#define ESC_LATCH1_CTRL_NEG_EDGE_SET(x) (((uint8_t)(x) << ESC_LATCH1_CTRL_NEG_EDGE_SHIFT) & ESC_LATCH1_CTRL_NEG_EDGE_MASK) +#define ESC_LATCH1_CTRL_NEG_EDGE_GET(x) (((uint8_t)(x) & ESC_LATCH1_CTRL_NEG_EDGE_MASK) >> ESC_LATCH1_CTRL_NEG_EDGE_SHIFT) + +/* + * POS_EDGE (RW) + * + * Latch1 positive edge: + * 0:Continuous Latch active + * 1:Single event (only first event active) + */ +#define ESC_LATCH1_CTRL_POS_EDGE_MASK (0x1U) +#define ESC_LATCH1_CTRL_POS_EDGE_SHIFT (0U) +#define ESC_LATCH1_CTRL_POS_EDGE_SET(x) (((uint8_t)(x) << ESC_LATCH1_CTRL_POS_EDGE_SHIFT) & ESC_LATCH1_CTRL_POS_EDGE_MASK) +#define ESC_LATCH1_CTRL_POS_EDGE_GET(x) (((uint8_t)(x) & ESC_LATCH1_CTRL_POS_EDGE_MASK) >> ESC_LATCH1_CTRL_POS_EDGE_SHIFT) + +/* Bitfield definition for register: LATCH0_STAT */ +/* + * PIN_STAT (RO) + * + * Latch0 pin state + */ +#define ESC_LATCH0_STAT_PIN_STAT_MASK (0x4U) +#define ESC_LATCH0_STAT_PIN_STAT_SHIFT (2U) +#define ESC_LATCH0_STAT_PIN_STAT_GET(x) (((uint8_t)(x) & ESC_LATCH0_STAT_PIN_STAT_MASK) >> ESC_LATCH0_STAT_PIN_STAT_SHIFT) + +/* + * NEG_EDGE (RO) + * + * Event Latch0 negative edge. + * 0:Negative edge not detected or + * continuous mode + * 1:Negative edge detected in single event + * mode only. + * Flag cleared by reading out Latch0 Time + * Negative Edge. + */ +#define ESC_LATCH0_STAT_NEG_EDGE_MASK (0x2U) +#define ESC_LATCH0_STAT_NEG_EDGE_SHIFT (1U) +#define ESC_LATCH0_STAT_NEG_EDGE_GET(x) (((uint8_t)(x) & ESC_LATCH0_STAT_NEG_EDGE_MASK) >> ESC_LATCH0_STAT_NEG_EDGE_SHIFT) + +/* + * POS_EDGE (RO) + * + * Event Latch0 positive edge. + * 0:Positive edge not detected or + * continuous mode + * 1:Positive edge detected in single event + * mode only. + * Flag cleared by reading out Latch0 Time + * Positive Edge. + */ +#define ESC_LATCH0_STAT_POS_EDGE_MASK (0x1U) +#define ESC_LATCH0_STAT_POS_EDGE_SHIFT (0U) +#define ESC_LATCH0_STAT_POS_EDGE_GET(x) (((uint8_t)(x) & ESC_LATCH0_STAT_POS_EDGE_MASK) >> ESC_LATCH0_STAT_POS_EDGE_SHIFT) + +/* Bitfield definition for register: LATCH1_STAT */ +/* + * PIN_STAT (RO) + * + * Latch1 pin state + */ +#define ESC_LATCH1_STAT_PIN_STAT_MASK (0x4U) +#define ESC_LATCH1_STAT_PIN_STAT_SHIFT (2U) +#define ESC_LATCH1_STAT_PIN_STAT_GET(x) (((uint8_t)(x) & ESC_LATCH1_STAT_PIN_STAT_MASK) >> ESC_LATCH1_STAT_PIN_STAT_SHIFT) + +/* + * NEG_EDGE (RO) + * + * Event Latch1 negative edge. + * 0:Negative edge not detected or + * continuous mode + * 1:Negative edge detected in single event + * mode only. + * Flag cleared by reading out Latch1 Time + * Negative Edge. + */ +#define ESC_LATCH1_STAT_NEG_EDGE_MASK (0x2U) +#define ESC_LATCH1_STAT_NEG_EDGE_SHIFT (1U) +#define ESC_LATCH1_STAT_NEG_EDGE_GET(x) (((uint8_t)(x) & ESC_LATCH1_STAT_NEG_EDGE_MASK) >> ESC_LATCH1_STAT_NEG_EDGE_SHIFT) + +/* + * POS_EDGE (RO) + * + * Event Latch1 positive edge. + * 0:Positive edge not detected or + * continuous mode + * 1:Positive edge detected in single event + * mode only. + * Flag cleared by reading out Latch1 Time + * Positive Edge. + */ +#define ESC_LATCH1_STAT_POS_EDGE_MASK (0x1U) +#define ESC_LATCH1_STAT_POS_EDGE_SHIFT (0U) +#define ESC_LATCH1_STAT_POS_EDGE_GET(x) (((uint8_t)(x) & ESC_LATCH1_STAT_POS_EDGE_MASK) >> ESC_LATCH1_STAT_POS_EDGE_SHIFT) + +/* Bitfield definition for register: LATCH0_TIME_PE */ +/* + * TIME (RW) + * + * System time at the positive edge of the + * Latch0 signal. + */ +#define ESC_LATCH0_TIME_PE_TIME_MASK (0xFFFFFFFFFFFFFFFFULL) +#define ESC_LATCH0_TIME_PE_TIME_SHIFT (0U) +#define ESC_LATCH0_TIME_PE_TIME_SET(x) (((uint64_t)(x) << ESC_LATCH0_TIME_PE_TIME_SHIFT) & ESC_LATCH0_TIME_PE_TIME_MASK) +#define ESC_LATCH0_TIME_PE_TIME_GET(x) (((uint64_t)(x) & ESC_LATCH0_TIME_PE_TIME_MASK) >> ESC_LATCH0_TIME_PE_TIME_SHIFT) + +/* Bitfield definition for register: LATCH0_TIME_NE */ +/* + * TIME (RW) + * + * System time at the negative edge of the + * Latch0 signal. + */ +#define ESC_LATCH0_TIME_NE_TIME_MASK (0xFFFFFFFFFFFFFFFFULL) +#define ESC_LATCH0_TIME_NE_TIME_SHIFT (0U) +#define ESC_LATCH0_TIME_NE_TIME_SET(x) (((uint64_t)(x) << ESC_LATCH0_TIME_NE_TIME_SHIFT) & ESC_LATCH0_TIME_NE_TIME_MASK) +#define ESC_LATCH0_TIME_NE_TIME_GET(x) (((uint64_t)(x) & ESC_LATCH0_TIME_NE_TIME_MASK) >> ESC_LATCH0_TIME_NE_TIME_SHIFT) + +/* Bitfield definition for register: LATCH1_TIME_PE */ +/* + * TIME (RW) + * + * System time at the positive edge of the + * Latch1 signal. + */ +#define ESC_LATCH1_TIME_PE_TIME_MASK (0xFFFFFFFFFFFFFFFFULL) +#define ESC_LATCH1_TIME_PE_TIME_SHIFT (0U) +#define ESC_LATCH1_TIME_PE_TIME_SET(x) (((uint64_t)(x) << ESC_LATCH1_TIME_PE_TIME_SHIFT) & ESC_LATCH1_TIME_PE_TIME_MASK) +#define ESC_LATCH1_TIME_PE_TIME_GET(x) (((uint64_t)(x) & ESC_LATCH1_TIME_PE_TIME_MASK) >> ESC_LATCH1_TIME_PE_TIME_SHIFT) + +/* Bitfield definition for register: LATCH1_TIME_NE */ +/* + * TIME (RW) + * + * System time at the negative edge of the + * Latch1 signal. + */ +#define ESC_LATCH1_TIME_NE_TIME_MASK (0xFFFFFFFFFFFFFFFFULL) +#define ESC_LATCH1_TIME_NE_TIME_SHIFT (0U) +#define ESC_LATCH1_TIME_NE_TIME_SET(x) (((uint64_t)(x) << ESC_LATCH1_TIME_NE_TIME_SHIFT) & ESC_LATCH1_TIME_NE_TIME_MASK) +#define ESC_LATCH1_TIME_NE_TIME_GET(x) (((uint64_t)(x) & ESC_LATCH1_TIME_NE_TIME_MASK) >> ESC_LATCH1_TIME_NE_TIME_SHIFT) + +/* Bitfield definition for register: ECAT_BUF_CET */ +/* + * TIME (RO) + * + * Local time at the beginning of the frame + * which causes at least one SyncManager to + * assert an ECAT event + */ +#define ESC_ECAT_BUF_CET_TIME_MASK (0xFFFFFFFFUL) +#define ESC_ECAT_BUF_CET_TIME_SHIFT (0U) +#define ESC_ECAT_BUF_CET_TIME_GET(x) (((uint32_t)(x) & ESC_ECAT_BUF_CET_TIME_MASK) >> ESC_ECAT_BUF_CET_TIME_SHIFT) + +/* Bitfield definition for register: PDI_BUF_SET */ +/* + * TIME (RO) + * + * Local time when at least one SyncManager + * asserts a PDI buffer start event + */ +#define ESC_PDI_BUF_SET_TIME_MASK (0xFFFFFFFFUL) +#define ESC_PDI_BUF_SET_TIME_SHIFT (0U) +#define ESC_PDI_BUF_SET_TIME_GET(x) (((uint32_t)(x) & ESC_PDI_BUF_SET_TIME_MASK) >> ESC_PDI_BUF_SET_TIME_SHIFT) + +/* Bitfield definition for register: PDI_BUF_CET */ +/* + * TIME (RO) + * + * Local time when at least one SyncManager + * asserts a PDI buffer change event + */ +#define ESC_PDI_BUF_CET_TIME_MASK (0xFFFFFFFFUL) +#define ESC_PDI_BUF_CET_TIME_SHIFT (0U) +#define ESC_PDI_BUF_CET_TIME_GET(x) (((uint32_t)(x) & ESC_PDI_BUF_CET_TIME_MASK) >> ESC_PDI_BUF_CET_TIME_SHIFT) + +/* Bitfield definition for register: PID */ +/* + * PID (RO) + * + * Product ID + */ +#define ESC_PID_PID_MASK (0xFFFFFFFFFFFFFFFFULL) +#define ESC_PID_PID_SHIFT (0U) +#define ESC_PID_PID_GET(x) (((uint64_t)(x) & ESC_PID_PID_MASK) >> ESC_PID_PID_SHIFT) + +/* Bitfield definition for register: VID */ +/* + * VID (RO) + * + * Vendor ID: + * 23-0: Company + * 31-24: Department + * NOTE:Test Vendor IDs have [31:28]=0xE + */ +#define ESC_VID_VID_MASK (0xFFFFFFFFFFFFFFFFULL) +#define ESC_VID_VID_SHIFT (0U) +#define ESC_VID_VID_GET(x) (((uint64_t)(x) & ESC_VID_VID_MASK) >> ESC_VID_VID_SHIFT) + +/* Bitfield definition for register: DIO_OUT_DATA */ +/* + * OD (RO) + * + * Output Data + */ +#define ESC_DIO_OUT_DATA_OD_MASK (0xFFFFFFFFUL) +#define ESC_DIO_OUT_DATA_OD_SHIFT (0U) +#define ESC_DIO_OUT_DATA_OD_GET(x) (((uint32_t)(x) & ESC_DIO_OUT_DATA_OD_MASK) >> ESC_DIO_OUT_DATA_OD_SHIFT) + +/* Bitfield definition for register: GPO */ +/* + * GPOD (RW) + * + * General Purpose Output Data + */ +#define ESC_GPO_GPOD_MASK (0xFFFFFFFFFFFFFFFFULL) +#define ESC_GPO_GPOD_SHIFT (0U) +#define ESC_GPO_GPOD_SET(x) (((uint64_t)(x) << ESC_GPO_GPOD_SHIFT) & ESC_GPO_GPOD_MASK) +#define ESC_GPO_GPOD_GET(x) (((uint64_t)(x) & ESC_GPO_GPOD_MASK) >> ESC_GPO_GPOD_SHIFT) + +/* Bitfield definition for register: GPI */ +/* + * GPID (RO) + * + * General Purpose Input Data + */ +#define ESC_GPI_GPID_MASK (0xFFFFFFFFFFFFFFFFULL) +#define ESC_GPI_GPID_SHIFT (0U) +#define ESC_GPI_GPID_GET(x) (((uint64_t)(x) & ESC_GPI_GPID_MASK) >> ESC_GPI_GPID_SHIFT) + +/* Bitfield definition for register: USER_RAM_BYTE0 */ +/* + * EXTF (RW) + * + * Number of extended feature bits + */ +#define ESC_USER_RAM_BYTE0_EXTF_MASK (0xFFU) +#define ESC_USER_RAM_BYTE0_EXTF_SHIFT (0U) +#define ESC_USER_RAM_BYTE0_EXTF_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE0_EXTF_SHIFT) & ESC_USER_RAM_BYTE0_EXTF_MASK) +#define ESC_USER_RAM_BYTE0_EXTF_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE0_EXTF_MASK) >> ESC_USER_RAM_BYTE0_EXTF_SHIFT) + +/* Bitfield definition for register: USER_RAM_BYTE1 */ +/* + * PRWO (RW) + * + * Physical Read/Write Offset (0x0108:0x0109) + */ +#define ESC_USER_RAM_BYTE1_PRWO_MASK (0x80U) +#define ESC_USER_RAM_BYTE1_PRWO_SHIFT (7U) +#define ESC_USER_RAM_BYTE1_PRWO_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE1_PRWO_SHIFT) & ESC_USER_RAM_BYTE1_PRWO_MASK) +#define ESC_USER_RAM_BYTE1_PRWO_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE1_PRWO_MASK) >> ESC_USER_RAM_BYTE1_PRWO_SHIFT) + +/* + * AEMW (RW) + * + * AL Event Mask writable (0x0204:0x0207) + */ +#define ESC_USER_RAM_BYTE1_AEMW_MASK (0x40U) +#define ESC_USER_RAM_BYTE1_AEMW_SHIFT (6U) +#define ESC_USER_RAM_BYTE1_AEMW_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE1_AEMW_SHIFT) & ESC_USER_RAM_BYTE1_AEMW_MASK) +#define ESC_USER_RAM_BYTE1_AEMW_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE1_AEMW_MASK) >> ESC_USER_RAM_BYTE1_AEMW_SHIFT) + +/* + * GPO (RW) + * + * General Purpose Outputs (0x0F10:0x0F17) + */ +#define ESC_USER_RAM_BYTE1_GPO_MASK (0x20U) +#define ESC_USER_RAM_BYTE1_GPO_SHIFT (5U) +#define ESC_USER_RAM_BYTE1_GPO_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE1_GPO_SHIFT) & ESC_USER_RAM_BYTE1_GPO_MASK) +#define ESC_USER_RAM_BYTE1_GPO_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE1_GPO_MASK) >> ESC_USER_RAM_BYTE1_GPO_SHIFT) + +/* + * GPI (RW) + * + * General Purpose Inputs (0x0F18:0x0F1F) + */ +#define ESC_USER_RAM_BYTE1_GPI_MASK (0x10U) +#define ESC_USER_RAM_BYTE1_GPI_SHIFT (4U) +#define ESC_USER_RAM_BYTE1_GPI_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE1_GPI_SHIFT) & ESC_USER_RAM_BYTE1_GPI_MASK) +#define ESC_USER_RAM_BYTE1_GPI_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE1_GPI_MASK) >> ESC_USER_RAM_BYTE1_GPI_SHIFT) + +/* + * CSA (RW) + * + * Configured Station Alias (0x0012:0x0013) + */ +#define ESC_USER_RAM_BYTE1_CSA_MASK (0x8U) +#define ESC_USER_RAM_BYTE1_CSA_SHIFT (3U) +#define ESC_USER_RAM_BYTE1_CSA_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE1_CSA_SHIFT) & ESC_USER_RAM_BYTE1_CSA_MASK) +#define ESC_USER_RAM_BYTE1_CSA_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE1_CSA_MASK) >> ESC_USER_RAM_BYTE1_CSA_SHIFT) + +/* + * EIM (RW) + * + * ECAT Interrupt Mask (0x0200:0x0201) + */ +#define ESC_USER_RAM_BYTE1_EIM_MASK (0x4U) +#define ESC_USER_RAM_BYTE1_EIM_SHIFT (2U) +#define ESC_USER_RAM_BYTE1_EIM_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE1_EIM_SHIFT) & ESC_USER_RAM_BYTE1_EIM_MASK) +#define ESC_USER_RAM_BYTE1_EIM_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE1_EIM_MASK) >> ESC_USER_RAM_BYTE1_EIM_SHIFT) + +/* + * ALSCR (RW) + * + * AL Status Code Register (0x0134:0x0135) + */ +#define ESC_USER_RAM_BYTE1_ALSCR_MASK (0x2U) +#define ESC_USER_RAM_BYTE1_ALSCR_SHIFT (1U) +#define ESC_USER_RAM_BYTE1_ALSCR_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE1_ALSCR_SHIFT) & ESC_USER_RAM_BYTE1_ALSCR_MASK) +#define ESC_USER_RAM_BYTE1_ALSCR_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE1_ALSCR_MASK) >> ESC_USER_RAM_BYTE1_ALSCR_SHIFT) + +/* + * EDLCR (RW) + * + * Extended DL Control Register (0x0102:0x0103) + */ +#define ESC_USER_RAM_BYTE1_EDLCR_MASK (0x1U) +#define ESC_USER_RAM_BYTE1_EDLCR_SHIFT (0U) +#define ESC_USER_RAM_BYTE1_EDLCR_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE1_EDLCR_SHIFT) & ESC_USER_RAM_BYTE1_EDLCR_MASK) +#define ESC_USER_RAM_BYTE1_EDLCR_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE1_EDLCR_MASK) >> ESC_USER_RAM_BYTE1_EDLCR_SHIFT) + +/* Bitfield definition for register: USER_RAM_BYTE2 */ +/* + * ESCFG (RW) + * + * EEPROM Size configurable (0x0502[7]): + * 0:EEPROM Size fixed to sizes up to 16 Kbit + * 1:EEPROM Size configurable + */ +#define ESC_USER_RAM_BYTE2_ESCFG_MASK (0x80U) +#define ESC_USER_RAM_BYTE2_ESCFG_SHIFT (7U) +#define ESC_USER_RAM_BYTE2_ESCFG_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE2_ESCFG_SHIFT) & ESC_USER_RAM_BYTE2_ESCFG_MASK) +#define ESC_USER_RAM_BYTE2_ESCFG_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE2_ESCFG_MASK) >> ESC_USER_RAM_BYTE2_ESCFG_SHIFT) + +/* + * EPUPEC (RW) + * + * ECAT Processing Unit/PDI Error Counter + * (0x030C:0x030D) + */ +#define ESC_USER_RAM_BYTE2_EPUPEC_MASK (0x40U) +#define ESC_USER_RAM_BYTE2_EPUPEC_SHIFT (6U) +#define ESC_USER_RAM_BYTE2_EPUPEC_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE2_EPUPEC_SHIFT) & ESC_USER_RAM_BYTE2_EPUPEC_MASK) +#define ESC_USER_RAM_BYTE2_EPUPEC_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE2_EPUPEC_MASK) >> ESC_USER_RAM_BYTE2_EPUPEC_SHIFT) + +/* + * DCSMET (RW) + * + * DC SyncManager Event Times (0x09F0:0x09FF) + */ +#define ESC_USER_RAM_BYTE2_DCSMET_MASK (0x20U) +#define ESC_USER_RAM_BYTE2_DCSMET_SHIFT (5U) +#define ESC_USER_RAM_BYTE2_DCSMET_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE2_DCSMET_SHIFT) & ESC_USER_RAM_BYTE2_DCSMET_MASK) +#define ESC_USER_RAM_BYTE2_DCSMET_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE2_DCSMET_MASK) >> ESC_USER_RAM_BYTE2_DCSMET_SHIFT) + +/* + * RESET (RW) + * + * Reset (0x0040:0x0041) + */ +#define ESC_USER_RAM_BYTE2_RESET_MASK (0x8U) +#define ESC_USER_RAM_BYTE2_RESET_SHIFT (3U) +#define ESC_USER_RAM_BYTE2_RESET_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE2_RESET_SHIFT) & ESC_USER_RAM_BYTE2_RESET_MASK) +#define ESC_USER_RAM_BYTE2_RESET_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE2_RESET_MASK) >> ESC_USER_RAM_BYTE2_RESET_SHIFT) + +/* + * WP (RW) + * + * Write Protection (0x0020:0x0031) + */ +#define ESC_USER_RAM_BYTE2_WP_MASK (0x4U) +#define ESC_USER_RAM_BYTE2_WP_SHIFT (2U) +#define ESC_USER_RAM_BYTE2_WP_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE2_WP_SHIFT) & ESC_USER_RAM_BYTE2_WP_MASK) +#define ESC_USER_RAM_BYTE2_WP_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE2_WP_MASK) >> ESC_USER_RAM_BYTE2_WP_SHIFT) + +/* + * WDGCNT (RW) + * + * Watchdog counters (0x0442:0x0443) + */ +#define ESC_USER_RAM_BYTE2_WDGCNT_MASK (0x2U) +#define ESC_USER_RAM_BYTE2_WDGCNT_SHIFT (1U) +#define ESC_USER_RAM_BYTE2_WDGCNT_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE2_WDGCNT_SHIFT) & ESC_USER_RAM_BYTE2_WDGCNT_MASK) +#define ESC_USER_RAM_BYTE2_WDGCNT_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE2_WDGCNT_MASK) >> ESC_USER_RAM_BYTE2_WDGCNT_SHIFT) + +/* + * WDW (RW) + * + * Watchdog divider writable (0x0400:0x0401) and + * Watchdog PDI (0x0410:0x0411) + */ +#define ESC_USER_RAM_BYTE2_WDW_MASK (0x1U) +#define ESC_USER_RAM_BYTE2_WDW_SHIFT (0U) +#define ESC_USER_RAM_BYTE2_WDW_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE2_WDW_SHIFT) & ESC_USER_RAM_BYTE2_WDW_MASK) +#define ESC_USER_RAM_BYTE2_WDW_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE2_WDW_MASK) >> ESC_USER_RAM_BYTE2_WDW_SHIFT) + +/* Bitfield definition for register: USER_RAM_BYTE3 */ +/* + * RLED (RW) + * + * Run LED (DEV_STATE LED) + */ +#define ESC_USER_RAM_BYTE3_RLED_MASK (0x80U) +#define ESC_USER_RAM_BYTE3_RLED_SHIFT (7U) +#define ESC_USER_RAM_BYTE3_RLED_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE3_RLED_SHIFT) & ESC_USER_RAM_BYTE3_RLED_MASK) +#define ESC_USER_RAM_BYTE3_RLED_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE3_RLED_MASK) >> ESC_USER_RAM_BYTE3_RLED_SHIFT) + +/* + * ELDE (RW) + * + * Enhanced Link Detection EBUS + */ +#define ESC_USER_RAM_BYTE3_ELDE_MASK (0x40U) +#define ESC_USER_RAM_BYTE3_ELDE_SHIFT (6U) +#define ESC_USER_RAM_BYTE3_ELDE_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE3_ELDE_SHIFT) & ESC_USER_RAM_BYTE3_ELDE_MASK) +#define ESC_USER_RAM_BYTE3_ELDE_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE3_ELDE_MASK) >> ESC_USER_RAM_BYTE3_ELDE_SHIFT) + +/* + * ELDM (RW) + * + * Enhanced Link Detection MII + */ +#define ESC_USER_RAM_BYTE3_ELDM_MASK (0x20U) +#define ESC_USER_RAM_BYTE3_ELDM_SHIFT (5U) +#define ESC_USER_RAM_BYTE3_ELDM_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE3_ELDM_SHIFT) & ESC_USER_RAM_BYTE3_ELDM_MASK) +#define ESC_USER_RAM_BYTE3_ELDM_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE3_ELDM_MASK) >> ESC_USER_RAM_BYTE3_ELDM_SHIFT) + +/* + * MMI (RW) + * + * MII Management Interface (0x0510:0x0515) + */ +#define ESC_USER_RAM_BYTE3_MMI_MASK (0x10U) +#define ESC_USER_RAM_BYTE3_MMI_SHIFT (4U) +#define ESC_USER_RAM_BYTE3_MMI_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE3_MMI_SHIFT) & ESC_USER_RAM_BYTE3_MMI_MASK) +#define ESC_USER_RAM_BYTE3_MMI_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE3_MMI_MASK) >> ESC_USER_RAM_BYTE3_MMI_SHIFT) + +/* + * LLC (RW) + * + * Lost Link Counter (0x0310:0x0313) + */ +#define ESC_USER_RAM_BYTE3_LLC_MASK (0x8U) +#define ESC_USER_RAM_BYTE3_LLC_SHIFT (3U) +#define ESC_USER_RAM_BYTE3_LLC_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE3_LLC_SHIFT) & ESC_USER_RAM_BYTE3_LLC_MASK) +#define ESC_USER_RAM_BYTE3_LLC_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE3_LLC_MASK) >> ESC_USER_RAM_BYTE3_LLC_SHIFT) + +/* Bitfield definition for register: USER_RAM_BYTE4 */ +/* + * LDCM (RW) + * + * Link detection and configuration by MI + */ +#define ESC_USER_RAM_BYTE4_LDCM_MASK (0x80U) +#define ESC_USER_RAM_BYTE4_LDCM_SHIFT (7U) +#define ESC_USER_RAM_BYTE4_LDCM_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE4_LDCM_SHIFT) & ESC_USER_RAM_BYTE4_LDCM_MASK) +#define ESC_USER_RAM_BYTE4_LDCM_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE4_LDCM_MASK) >> ESC_USER_RAM_BYTE4_LDCM_SHIFT) + +/* + * DTLC (RW) + * + * DC Time loop control assigned to PDI + */ +#define ESC_USER_RAM_BYTE4_DTLC_MASK (0x40U) +#define ESC_USER_RAM_BYTE4_DTLC_SHIFT (6U) +#define ESC_USER_RAM_BYTE4_DTLC_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE4_DTLC_SHIFT) & ESC_USER_RAM_BYTE4_DTLC_MASK) +#define ESC_USER_RAM_BYTE4_DTLC_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE4_DTLC_MASK) >> ESC_USER_RAM_BYTE4_DTLC_SHIFT) + +/* + * DSOU (RW) + * + * DC Sync Out Unit + */ +#define ESC_USER_RAM_BYTE4_DSOU_MASK (0x20U) +#define ESC_USER_RAM_BYTE4_DSOU_SHIFT (5U) +#define ESC_USER_RAM_BYTE4_DSOU_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE4_DSOU_SHIFT) & ESC_USER_RAM_BYTE4_DSOU_MASK) +#define ESC_USER_RAM_BYTE4_DSOU_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE4_DSOU_MASK) >> ESC_USER_RAM_BYTE4_DSOU_SHIFT) + +/* + * DLIU (RW) + * + * DC Latch In Unit + */ +#define ESC_USER_RAM_BYTE4_DLIU_MASK (0x8U) +#define ESC_USER_RAM_BYTE4_DLIU_SHIFT (3U) +#define ESC_USER_RAM_BYTE4_DLIU_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE4_DLIU_SHIFT) & ESC_USER_RAM_BYTE4_DLIU_MASK) +#define ESC_USER_RAM_BYTE4_DLIU_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE4_DLIU_MASK) >> ESC_USER_RAM_BYTE4_DLIU_SHIFT) + +/* + * LALED (RW) + * + * Link/Activity LED + */ +#define ESC_USER_RAM_BYTE4_LALED_MASK (0x1U) +#define ESC_USER_RAM_BYTE4_LALED_SHIFT (0U) +#define ESC_USER_RAM_BYTE4_LALED_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE4_LALED_SHIFT) & ESC_USER_RAM_BYTE4_LALED_MASK) +#define ESC_USER_RAM_BYTE4_LALED_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE4_LALED_MASK) >> ESC_USER_RAM_BYTE4_LALED_SHIFT) + +/* Bitfield definition for register: USER_RAM_BYTE5 */ +/* + * DDIOR (RW) + * + * Disable Digital I/O register (0x0F00:0x0F03) + */ +#define ESC_USER_RAM_BYTE5_DDIOR_MASK (0x20U) +#define ESC_USER_RAM_BYTE5_DDIOR_SHIFT (5U) +#define ESC_USER_RAM_BYTE5_DDIOR_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE5_DDIOR_SHIFT) & ESC_USER_RAM_BYTE5_DDIOR_MASK) +#define ESC_USER_RAM_BYTE5_DDIOR_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE5_DDIOR_MASK) >> ESC_USER_RAM_BYTE5_DDIOR_SHIFT) + +/* + * EEU (RW) + * + * EEPROM emulation by µController + */ +#define ESC_USER_RAM_BYTE5_EEU_MASK (0x4U) +#define ESC_USER_RAM_BYTE5_EEU_SHIFT (2U) +#define ESC_USER_RAM_BYTE5_EEU_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE5_EEU_SHIFT) & ESC_USER_RAM_BYTE5_EEU_MASK) +#define ESC_USER_RAM_BYTE5_EEU_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE5_EEU_MASK) >> ESC_USER_RAM_BYTE5_EEU_SHIFT) + +/* + * ATS (RW) + * + * Automatic TX shift + */ +#define ESC_USER_RAM_BYTE5_ATS_MASK (0x2U) +#define ESC_USER_RAM_BYTE5_ATS_SHIFT (1U) +#define ESC_USER_RAM_BYTE5_ATS_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE5_ATS_SHIFT) & ESC_USER_RAM_BYTE5_ATS_MASK) +#define ESC_USER_RAM_BYTE5_ATS_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE5_ATS_MASK) >> ESC_USER_RAM_BYTE5_ATS_SHIFT) + +/* + * MCPP (RW) + * + * MI control by PDI possible + */ +#define ESC_USER_RAM_BYTE5_MCPP_MASK (0x1U) +#define ESC_USER_RAM_BYTE5_MCPP_SHIFT (0U) +#define ESC_USER_RAM_BYTE5_MCPP_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE5_MCPP_SHIFT) & ESC_USER_RAM_BYTE5_MCPP_MASK) +#define ESC_USER_RAM_BYTE5_MCPP_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE5_MCPP_MASK) >> ESC_USER_RAM_BYTE5_MCPP_SHIFT) + +/* Bitfield definition for register: USER_RAM_BYTE6 */ +/* + * RELEDOR (RW) + * + * RUN/ERR LED Override (0x0138:0x0139) + */ +#define ESC_USER_RAM_BYTE6_RELEDOR_MASK (0x4U) +#define ESC_USER_RAM_BYTE6_RELEDOR_SHIFT (2U) +#define ESC_USER_RAM_BYTE6_RELEDOR_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE6_RELEDOR_SHIFT) & ESC_USER_RAM_BYTE6_RELEDOR_MASK) +#define ESC_USER_RAM_BYTE6_RELEDOR_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE6_RELEDOR_MASK) >> ESC_USER_RAM_BYTE6_RELEDOR_SHIFT) + +/* Bitfield definition for register: USER_RAM_BYTE7 */ +/* + * DCST (RW) + * + * DC System Time (0x0910:0x0936) + */ +#define ESC_USER_RAM_BYTE7_DCST_MASK (0x80U) +#define ESC_USER_RAM_BYTE7_DCST_SHIFT (7U) +#define ESC_USER_RAM_BYTE7_DCST_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE7_DCST_SHIFT) & ESC_USER_RAM_BYTE7_DCST_MASK) +#define ESC_USER_RAM_BYTE7_DCST_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE7_DCST_MASK) >> ESC_USER_RAM_BYTE7_DCST_SHIFT) + +/* + * DCRT (RW) + * + * DC Receive Times (0x0900:0x090F) + */ +#define ESC_USER_RAM_BYTE7_DCRT_MASK (0x40U) +#define ESC_USER_RAM_BYTE7_DCRT_SHIFT (6U) +#define ESC_USER_RAM_BYTE7_DCRT_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE7_DCRT_SHIFT) & ESC_USER_RAM_BYTE7_DCRT_MASK) +#define ESC_USER_RAM_BYTE7_DCRT_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE7_DCRT_MASK) >> ESC_USER_RAM_BYTE7_DCRT_SHIFT) + +/* + * DCS1D (RW) + * + * DC Sync1 disable + */ +#define ESC_USER_RAM_BYTE7_DCS1D_MASK (0x8U) +#define ESC_USER_RAM_BYTE7_DCS1D_SHIFT (3U) +#define ESC_USER_RAM_BYTE7_DCS1D_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE7_DCS1D_SHIFT) & ESC_USER_RAM_BYTE7_DCS1D_MASK) +#define ESC_USER_RAM_BYTE7_DCS1D_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE7_DCS1D_MASK) >> ESC_USER_RAM_BYTE7_DCS1D_SHIFT) + +/* Bitfield definition for register: USER_RAM_BYTE8 */ +/* + * PPDI (RW) + * + * PLB PDI + */ +#define ESC_USER_RAM_BYTE8_PPDI_MASK (0x20U) +#define ESC_USER_RAM_BYTE8_PPDI_SHIFT (5U) +#define ESC_USER_RAM_BYTE8_PPDI_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE8_PPDI_SHIFT) & ESC_USER_RAM_BYTE8_PPDI_MASK) +#define ESC_USER_RAM_BYTE8_PPDI_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE8_PPDI_MASK) >> ESC_USER_RAM_BYTE8_PPDI_SHIFT) + +/* + * OPDI (RW) + * + * OPB PDI + */ +#define ESC_USER_RAM_BYTE8_OPDI_MASK (0x10U) +#define ESC_USER_RAM_BYTE8_OPDI_SHIFT (4U) +#define ESC_USER_RAM_BYTE8_OPDI_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE8_OPDI_SHIFT) & ESC_USER_RAM_BYTE8_OPDI_MASK) +#define ESC_USER_RAM_BYTE8_OPDI_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE8_OPDI_MASK) >> ESC_USER_RAM_BYTE8_OPDI_SHIFT) + +/* + * APDI (RW) + * + * Avalon PDI + */ +#define ESC_USER_RAM_BYTE8_APDI_MASK (0x8U) +#define ESC_USER_RAM_BYTE8_APDI_SHIFT (3U) +#define ESC_USER_RAM_BYTE8_APDI_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE8_APDI_SHIFT) & ESC_USER_RAM_BYTE8_APDI_MASK) +#define ESC_USER_RAM_BYTE8_APDI_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE8_APDI_MASK) >> ESC_USER_RAM_BYTE8_APDI_SHIFT) + +/* + * PDICEC (RW) + * + * PDI clears error counter + */ +#define ESC_USER_RAM_BYTE8_PDICEC_MASK (0x4U) +#define ESC_USER_RAM_BYTE8_PDICEC_SHIFT (2U) +#define ESC_USER_RAM_BYTE8_PDICEC_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE8_PDICEC_SHIFT) & ESC_USER_RAM_BYTE8_PDICEC_MASK) +#define ESC_USER_RAM_BYTE8_PDICEC_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE8_PDICEC_MASK) >> ESC_USER_RAM_BYTE8_PDICEC_SHIFT) + +/* + * DC64 (RW) + * + * DC 64 bit + */ +#define ESC_USER_RAM_BYTE8_DC64_MASK (0x1U) +#define ESC_USER_RAM_BYTE8_DC64_SHIFT (0U) +#define ESC_USER_RAM_BYTE8_DC64_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE8_DC64_SHIFT) & ESC_USER_RAM_BYTE8_DC64_MASK) +#define ESC_USER_RAM_BYTE8_DC64_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE8_DC64_MASK) >> ESC_USER_RAM_BYTE8_DC64_SHIFT) + +/* Bitfield definition for register: USER_RAM_BYTE9 */ +/* + * DR (RW) + * + * Direct RESET + */ +#define ESC_USER_RAM_BYTE9_DR_MASK (0x80U) +#define ESC_USER_RAM_BYTE9_DR_SHIFT (7U) +#define ESC_USER_RAM_BYTE9_DR_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE9_DR_SHIFT) & ESC_USER_RAM_BYTE9_DR_MASK) +#define ESC_USER_RAM_BYTE9_DR_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE9_DR_MASK) >> ESC_USER_RAM_BYTE9_DR_SHIFT) + +/* Bitfield definition for register: USER_RAM_BYTE10 */ +/* + * PDIIR (RW) + * + * PDI Information register (0x014E:0x014F) + */ +#define ESC_USER_RAM_BYTE10_PDIIR_MASK (0x80U) +#define ESC_USER_RAM_BYTE10_PDIIR_SHIFT (7U) +#define ESC_USER_RAM_BYTE10_PDIIR_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE10_PDIIR_SHIFT) & ESC_USER_RAM_BYTE10_PDIIR_MASK) +#define ESC_USER_RAM_BYTE10_PDIIR_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE10_PDIIR_MASK) >> ESC_USER_RAM_BYTE10_PDIIR_SHIFT) + +/* + * PDIFA (RW) + * + * PDI function acknowledge by PDI write + */ +#define ESC_USER_RAM_BYTE10_PDIFA_MASK (0x40U) +#define ESC_USER_RAM_BYTE10_PDIFA_SHIFT (6U) +#define ESC_USER_RAM_BYTE10_PDIFA_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE10_PDIFA_SHIFT) & ESC_USER_RAM_BYTE10_PDIFA_MASK) +#define ESC_USER_RAM_BYTE10_PDIFA_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE10_PDIFA_MASK) >> ESC_USER_RAM_BYTE10_PDIFA_SHIFT) + +/* + * APDI (RW) + * + * AXI PDI + */ +#define ESC_USER_RAM_BYTE10_APDI_MASK (0x8U) +#define ESC_USER_RAM_BYTE10_APDI_SHIFT (3U) +#define ESC_USER_RAM_BYTE10_APDI_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE10_APDI_SHIFT) & ESC_USER_RAM_BYTE10_APDI_MASK) +#define ESC_USER_RAM_BYTE10_APDI_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE10_APDI_MASK) >> ESC_USER_RAM_BYTE10_APDI_SHIFT) + +/* + * DCL1D (RW) + * + * DC Latch1 disable + */ +#define ESC_USER_RAM_BYTE10_DCL1D_MASK (0x4U) +#define ESC_USER_RAM_BYTE10_DCL1D_SHIFT (2U) +#define ESC_USER_RAM_BYTE10_DCL1D_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE10_DCL1D_SHIFT) & ESC_USER_RAM_BYTE10_DCL1D_MASK) +#define ESC_USER_RAM_BYTE10_DCL1D_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE10_DCL1D_MASK) >> ESC_USER_RAM_BYTE10_DCL1D_SHIFT) + +/* Bitfield definition for register: USER_RAM_BYTE11 */ +/* + * LEDTST (RW) + * + * LED test + */ +#define ESC_USER_RAM_BYTE11_LEDTST_MASK (0x8U) +#define ESC_USER_RAM_BYTE11_LEDTST_SHIFT (3U) +#define ESC_USER_RAM_BYTE11_LEDTST_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE11_LEDTST_SHIFT) & ESC_USER_RAM_BYTE11_LEDTST_MASK) +#define ESC_USER_RAM_BYTE11_LEDTST_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE11_LEDTST_MASK) >> ESC_USER_RAM_BYTE11_LEDTST_SHIFT) + +/* Bitfield definition for register: USER_RAM_BYTE14 */ +/* + * DIOBS (RW) + * + * Digital I/O PDI byte size + */ +#define ESC_USER_RAM_BYTE14_DIOBS_MASK (0xC0U) +#define ESC_USER_RAM_BYTE14_DIOBS_SHIFT (6U) +#define ESC_USER_RAM_BYTE14_DIOBS_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE14_DIOBS_SHIFT) & ESC_USER_RAM_BYTE14_DIOBS_MASK) +#define ESC_USER_RAM_BYTE14_DIOBS_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE14_DIOBS_MASK) >> ESC_USER_RAM_BYTE14_DIOBS_SHIFT) + +/* Bitfield definition for register: USER_RAM_BYTE15 */ +/* + * AUCPDI (RW) + * + * Asynchronous µC PDI + */ +#define ESC_USER_RAM_BYTE15_AUCPDI_MASK (0x10U) +#define ESC_USER_RAM_BYTE15_AUCPDI_SHIFT (4U) +#define ESC_USER_RAM_BYTE15_AUCPDI_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE15_AUCPDI_SHIFT) & ESC_USER_RAM_BYTE15_AUCPDI_MASK) +#define ESC_USER_RAM_BYTE15_AUCPDI_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE15_AUCPDI_MASK) >> ESC_USER_RAM_BYTE15_AUCPDI_SHIFT) + +/* + * SSPDI (RW) + * + * SPI Slave PDI + */ +#define ESC_USER_RAM_BYTE15_SSPDI_MASK (0x8U) +#define ESC_USER_RAM_BYTE15_SSPDI_SHIFT (3U) +#define ESC_USER_RAM_BYTE15_SSPDI_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE15_SSPDI_SHIFT) & ESC_USER_RAM_BYTE15_SSPDI_MASK) +#define ESC_USER_RAM_BYTE15_SSPDI_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE15_SSPDI_MASK) >> ESC_USER_RAM_BYTE15_SSPDI_SHIFT) + +/* + * DIOPDI (RW) + * + * Digital I/O PDI + */ +#define ESC_USER_RAM_BYTE15_DIOPDI_MASK (0x4U) +#define ESC_USER_RAM_BYTE15_DIOPDI_SHIFT (2U) +#define ESC_USER_RAM_BYTE15_DIOPDI_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE15_DIOPDI_SHIFT) & ESC_USER_RAM_BYTE15_DIOPDI_MASK) +#define ESC_USER_RAM_BYTE15_DIOPDI_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE15_DIOPDI_MASK) >> ESC_USER_RAM_BYTE15_DIOPDI_SHIFT) + +/* Bitfield definition for register: USER_RAM_BYTE19 */ +/* + * SCP (RW) + * + * Security CPLD protection + */ +#define ESC_USER_RAM_BYTE19_SCP_MASK (0x40U) +#define ESC_USER_RAM_BYTE19_SCP_SHIFT (6U) +#define ESC_USER_RAM_BYTE19_SCP_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE19_SCP_SHIFT) & ESC_USER_RAM_BYTE19_SCP_MASK) +#define ESC_USER_RAM_BYTE19_SCP_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE19_SCP_MASK) >> ESC_USER_RAM_BYTE19_SCP_SHIFT) + +/* + * RMII (RW) + * + * RMII + */ +#define ESC_USER_RAM_BYTE19_RMII_MASK (0x20U) +#define ESC_USER_RAM_BYTE19_RMII_SHIFT (5U) +#define ESC_USER_RAM_BYTE19_RMII_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE19_RMII_SHIFT) & ESC_USER_RAM_BYTE19_RMII_MASK) +#define ESC_USER_RAM_BYTE19_RMII_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE19_RMII_MASK) >> ESC_USER_RAM_BYTE19_RMII_SHIFT) + +/* + * URGP (RW) + * + * Use RGMII GTX_CLK phase shifted clock input + */ +#define ESC_USER_RAM_BYTE19_URGP_MASK (0x10U) +#define ESC_USER_RAM_BYTE19_URGP_SHIFT (4U) +#define ESC_USER_RAM_BYTE19_URGP_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE19_URGP_SHIFT) & ESC_USER_RAM_BYTE19_URGP_MASK) +#define ESC_USER_RAM_BYTE19_URGP_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE19_URGP_MASK) >> ESC_USER_RAM_BYTE19_URGP_SHIFT) + +/* + * CIA (RW) + * + * CLK_PDI_EXT is asynchronous + */ +#define ESC_USER_RAM_BYTE19_CIA_MASK (0x4U) +#define ESC_USER_RAM_BYTE19_CIA_SHIFT (2U) +#define ESC_USER_RAM_BYTE19_CIA_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE19_CIA_SHIFT) & ESC_USER_RAM_BYTE19_CIA_MASK) +#define ESC_USER_RAM_BYTE19_CIA_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE19_CIA_MASK) >> ESC_USER_RAM_BYTE19_CIA_SHIFT) + +/* + * IPARO (RW) + * + * Individual PHY address read out (0x0510[7:3]) + */ +#define ESC_USER_RAM_BYTE19_IPARO_MASK (0x2U) +#define ESC_USER_RAM_BYTE19_IPARO_SHIFT (1U) +#define ESC_USER_RAM_BYTE19_IPARO_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE19_IPARO_SHIFT) & ESC_USER_RAM_BYTE19_IPARO_MASK) +#define ESC_USER_RAM_BYTE19_IPARO_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE19_IPARO_MASK) >> ESC_USER_RAM_BYTE19_IPARO_SHIFT) + +/* + * RGMII (RW) + * + * RGMII + */ +#define ESC_USER_RAM_BYTE19_RGMII_MASK (0x1U) +#define ESC_USER_RAM_BYTE19_RGMII_SHIFT (0U) +#define ESC_USER_RAM_BYTE19_RGMII_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE19_RGMII_SHIFT) & ESC_USER_RAM_BYTE19_RGMII_MASK) +#define ESC_USER_RAM_BYTE19_RGMII_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE19_RGMII_MASK) >> ESC_USER_RAM_BYTE19_RGMII_SHIFT) + +/* Bitfield definition for register: PDRAM */ +/* + * DATA (RW) + * + * Input Data + */ +#define ESC_PDRAM_DATA_MASK (0xFFFFFFFFUL) +#define ESC_PDRAM_DATA_SHIFT (0U) +#define ESC_PDRAM_DATA_SET(x) (((uint32_t)(x) << ESC_PDRAM_DATA_SHIFT) & ESC_PDRAM_DATA_MASK) +#define ESC_PDRAM_DATA_GET(x) (((uint32_t)(x) & ESC_PDRAM_DATA_MASK) >> ESC_PDRAM_DATA_SHIFT) + +/* Bitfield definition for register: PDRAM_ALS */ +/* + * DATA (RW) + * + */ +#define ESC_PDRAM_ALS_DATA_MASK (0xFFFFFFFFUL) +#define ESC_PDRAM_ALS_DATA_SHIFT (0U) +#define ESC_PDRAM_ALS_DATA_SET(x) (((uint32_t)(x) << ESC_PDRAM_ALS_DATA_SHIFT) & ESC_PDRAM_ALS_DATA_MASK) +#define ESC_PDRAM_ALS_DATA_GET(x) (((uint32_t)(x) & ESC_PDRAM_ALS_DATA_MASK) >> ESC_PDRAM_ALS_DATA_SHIFT) + +/* Bitfield definition for register: GPR_CFG0 */ +/* + * CLK100_EN (RW) + * + */ +#define ESC_GPR_CFG0_CLK100_EN_MASK (0x2000U) +#define ESC_GPR_CFG0_CLK100_EN_SHIFT (13U) +#define ESC_GPR_CFG0_CLK100_EN_SET(x) (((uint32_t)(x) << ESC_GPR_CFG0_CLK100_EN_SHIFT) & ESC_GPR_CFG0_CLK100_EN_MASK) +#define ESC_GPR_CFG0_CLK100_EN_GET(x) (((uint32_t)(x) & ESC_GPR_CFG0_CLK100_EN_MASK) >> ESC_GPR_CFG0_CLK100_EN_SHIFT) + +/* + * EEPROM_EMU (RW) + * + * 1 is EEPROM emulation mode (default) + */ +#define ESC_GPR_CFG0_EEPROM_EMU_MASK (0x1000U) +#define ESC_GPR_CFG0_EEPROM_EMU_SHIFT (12U) +#define ESC_GPR_CFG0_EEPROM_EMU_SET(x) (((uint32_t)(x) << ESC_GPR_CFG0_EEPROM_EMU_SHIFT) & ESC_GPR_CFG0_EEPROM_EMU_MASK) +#define ESC_GPR_CFG0_EEPROM_EMU_GET(x) (((uint32_t)(x) & ESC_GPR_CFG0_EEPROM_EMU_MASK) >> ESC_GPR_CFG0_EEPROM_EMU_SHIFT) + +/* + * I2C_SCLK_EN (RW) + * + */ +#define ESC_GPR_CFG0_I2C_SCLK_EN_MASK (0x8U) +#define ESC_GPR_CFG0_I2C_SCLK_EN_SHIFT (3U) +#define ESC_GPR_CFG0_I2C_SCLK_EN_SET(x) (((uint32_t)(x) << ESC_GPR_CFG0_I2C_SCLK_EN_SHIFT) & ESC_GPR_CFG0_I2C_SCLK_EN_MASK) +#define ESC_GPR_CFG0_I2C_SCLK_EN_GET(x) (((uint32_t)(x) & ESC_GPR_CFG0_I2C_SCLK_EN_MASK) >> ESC_GPR_CFG0_I2C_SCLK_EN_SHIFT) + +/* + * PROM_SIZE (RW) + * + * Sets EEPROM size: + * 0:up to 16 kbit EEPROM + * 1:32 kbit-4Mbit EEPROM + */ +#define ESC_GPR_CFG0_PROM_SIZE_MASK (0x1U) +#define ESC_GPR_CFG0_PROM_SIZE_SHIFT (0U) +#define ESC_GPR_CFG0_PROM_SIZE_SET(x) (((uint32_t)(x) << ESC_GPR_CFG0_PROM_SIZE_SHIFT) & ESC_GPR_CFG0_PROM_SIZE_MASK) +#define ESC_GPR_CFG0_PROM_SIZE_GET(x) (((uint32_t)(x) & ESC_GPR_CFG0_PROM_SIZE_MASK) >> ESC_GPR_CFG0_PROM_SIZE_SHIFT) + +/* Bitfield definition for register: GPR_CFG1 */ +/* + * SYNC1_IRQ_EN (RW) + * + */ +#define ESC_GPR_CFG1_SYNC1_IRQ_EN_MASK (0x80000000UL) +#define ESC_GPR_CFG1_SYNC1_IRQ_EN_SHIFT (31U) +#define ESC_GPR_CFG1_SYNC1_IRQ_EN_SET(x) (((uint32_t)(x) << ESC_GPR_CFG1_SYNC1_IRQ_EN_SHIFT) & ESC_GPR_CFG1_SYNC1_IRQ_EN_MASK) +#define ESC_GPR_CFG1_SYNC1_IRQ_EN_GET(x) (((uint32_t)(x) & ESC_GPR_CFG1_SYNC1_IRQ_EN_MASK) >> ESC_GPR_CFG1_SYNC1_IRQ_EN_SHIFT) + +/* + * SYNC0_IRQ_EN (RW) + * + */ +#define ESC_GPR_CFG1_SYNC0_IRQ_EN_MASK (0x40000000UL) +#define ESC_GPR_CFG1_SYNC0_IRQ_EN_SHIFT (30U) +#define ESC_GPR_CFG1_SYNC0_IRQ_EN_SET(x) (((uint32_t)(x) << ESC_GPR_CFG1_SYNC0_IRQ_EN_SHIFT) & ESC_GPR_CFG1_SYNC0_IRQ_EN_MASK) +#define ESC_GPR_CFG1_SYNC0_IRQ_EN_GET(x) (((uint32_t)(x) & ESC_GPR_CFG1_SYNC0_IRQ_EN_MASK) >> ESC_GPR_CFG1_SYNC0_IRQ_EN_SHIFT) + +/* + * RSTO_IRQ_EN (RW) + * + */ +#define ESC_GPR_CFG1_RSTO_IRQ_EN_MASK (0x20000000UL) +#define ESC_GPR_CFG1_RSTO_IRQ_EN_SHIFT (29U) +#define ESC_GPR_CFG1_RSTO_IRQ_EN_SET(x) (((uint32_t)(x) << ESC_GPR_CFG1_RSTO_IRQ_EN_SHIFT) & ESC_GPR_CFG1_RSTO_IRQ_EN_MASK) +#define ESC_GPR_CFG1_RSTO_IRQ_EN_GET(x) (((uint32_t)(x) & ESC_GPR_CFG1_RSTO_IRQ_EN_MASK) >> ESC_GPR_CFG1_RSTO_IRQ_EN_SHIFT) + +/* + * SYNC1_DMA_EN (RW) + * + */ +#define ESC_GPR_CFG1_SYNC1_DMA_EN_MASK (0x2000U) +#define ESC_GPR_CFG1_SYNC1_DMA_EN_SHIFT (13U) +#define ESC_GPR_CFG1_SYNC1_DMA_EN_SET(x) (((uint32_t)(x) << ESC_GPR_CFG1_SYNC1_DMA_EN_SHIFT) & ESC_GPR_CFG1_SYNC1_DMA_EN_MASK) +#define ESC_GPR_CFG1_SYNC1_DMA_EN_GET(x) (((uint32_t)(x) & ESC_GPR_CFG1_SYNC1_DMA_EN_MASK) >> ESC_GPR_CFG1_SYNC1_DMA_EN_SHIFT) + +/* + * SYNC0_DMA_EN (RW) + * + */ +#define ESC_GPR_CFG1_SYNC0_DMA_EN_MASK (0x1000U) +#define ESC_GPR_CFG1_SYNC0_DMA_EN_SHIFT (12U) +#define ESC_GPR_CFG1_SYNC0_DMA_EN_SET(x) (((uint32_t)(x) << ESC_GPR_CFG1_SYNC0_DMA_EN_SHIFT) & ESC_GPR_CFG1_SYNC0_DMA_EN_MASK) +#define ESC_GPR_CFG1_SYNC0_DMA_EN_GET(x) (((uint32_t)(x) & ESC_GPR_CFG1_SYNC0_DMA_EN_MASK) >> ESC_GPR_CFG1_SYNC0_DMA_EN_SHIFT) + +/* + * LATCH1_FROM_IO (RW) + * + * 0:from NTM + */ +#define ESC_GPR_CFG1_LATCH1_FROM_IO_MASK (0x200U) +#define ESC_GPR_CFG1_LATCH1_FROM_IO_SHIFT (9U) +#define ESC_GPR_CFG1_LATCH1_FROM_IO_SET(x) (((uint32_t)(x) << ESC_GPR_CFG1_LATCH1_FROM_IO_SHIFT) & ESC_GPR_CFG1_LATCH1_FROM_IO_MASK) +#define ESC_GPR_CFG1_LATCH1_FROM_IO_GET(x) (((uint32_t)(x) & ESC_GPR_CFG1_LATCH1_FROM_IO_MASK) >> ESC_GPR_CFG1_LATCH1_FROM_IO_SHIFT) + +/* + * LATCH0_FROM_IO (RW) + * + * 0:from TRIGGER_MUX + */ +#define ESC_GPR_CFG1_LATCH0_FROM_IO_MASK (0x100U) +#define ESC_GPR_CFG1_LATCH0_FROM_IO_SHIFT (8U) +#define ESC_GPR_CFG1_LATCH0_FROM_IO_SET(x) (((uint32_t)(x) << ESC_GPR_CFG1_LATCH0_FROM_IO_SHIFT) & ESC_GPR_CFG1_LATCH0_FROM_IO_MASK) +#define ESC_GPR_CFG1_LATCH0_FROM_IO_GET(x) (((uint32_t)(x) & ESC_GPR_CFG1_LATCH0_FROM_IO_MASK) >> ESC_GPR_CFG1_LATCH0_FROM_IO_SHIFT) + +/* + * RSTO_OVRD (RW) + * + */ +#define ESC_GPR_CFG1_RSTO_OVRD_MASK (0x80U) +#define ESC_GPR_CFG1_RSTO_OVRD_SHIFT (7U) +#define ESC_GPR_CFG1_RSTO_OVRD_SET(x) (((uint32_t)(x) << ESC_GPR_CFG1_RSTO_OVRD_SHIFT) & ESC_GPR_CFG1_RSTO_OVRD_MASK) +#define ESC_GPR_CFG1_RSTO_OVRD_GET(x) (((uint32_t)(x) & ESC_GPR_CFG1_RSTO_OVRD_MASK) >> ESC_GPR_CFG1_RSTO_OVRD_SHIFT) + +/* + * RSTO_OVRD_ENJ (RW) + * + */ +#define ESC_GPR_CFG1_RSTO_OVRD_ENJ_MASK (0x40U) +#define ESC_GPR_CFG1_RSTO_OVRD_ENJ_SHIFT (6U) +#define ESC_GPR_CFG1_RSTO_OVRD_ENJ_SET(x) (((uint32_t)(x) << ESC_GPR_CFG1_RSTO_OVRD_ENJ_SHIFT) & ESC_GPR_CFG1_RSTO_OVRD_ENJ_MASK) +#define ESC_GPR_CFG1_RSTO_OVRD_ENJ_GET(x) (((uint32_t)(x) & ESC_GPR_CFG1_RSTO_OVRD_ENJ_MASK) >> ESC_GPR_CFG1_RSTO_OVRD_ENJ_SHIFT) + +/* Bitfield definition for register: GPR_CFG2 */ +/* + * NMII_LINK2_FROM_IO (RW) + * + */ +#define ESC_GPR_CFG2_NMII_LINK2_FROM_IO_MASK (0x20000000UL) +#define ESC_GPR_CFG2_NMII_LINK2_FROM_IO_SHIFT (29U) +#define ESC_GPR_CFG2_NMII_LINK2_FROM_IO_SET(x) (((uint32_t)(x) << ESC_GPR_CFG2_NMII_LINK2_FROM_IO_SHIFT) & ESC_GPR_CFG2_NMII_LINK2_FROM_IO_MASK) +#define ESC_GPR_CFG2_NMII_LINK2_FROM_IO_GET(x) (((uint32_t)(x) & ESC_GPR_CFG2_NMII_LINK2_FROM_IO_MASK) >> ESC_GPR_CFG2_NMII_LINK2_FROM_IO_SHIFT) + +/* + * NMII_LINK2_GPR (RW) + * + */ +#define ESC_GPR_CFG2_NMII_LINK2_GPR_MASK (0x10000000UL) +#define ESC_GPR_CFG2_NMII_LINK2_GPR_SHIFT (28U) +#define ESC_GPR_CFG2_NMII_LINK2_GPR_SET(x) (((uint32_t)(x) << ESC_GPR_CFG2_NMII_LINK2_GPR_SHIFT) & ESC_GPR_CFG2_NMII_LINK2_GPR_MASK) +#define ESC_GPR_CFG2_NMII_LINK2_GPR_GET(x) (((uint32_t)(x) & ESC_GPR_CFG2_NMII_LINK2_GPR_MASK) >> ESC_GPR_CFG2_NMII_LINK2_GPR_SHIFT) + +/* + * NMII_LINK1_FROM_IO (RW) + * + */ +#define ESC_GPR_CFG2_NMII_LINK1_FROM_IO_MASK (0x2000000UL) +#define ESC_GPR_CFG2_NMII_LINK1_FROM_IO_SHIFT (25U) +#define ESC_GPR_CFG2_NMII_LINK1_FROM_IO_SET(x) (((uint32_t)(x) << ESC_GPR_CFG2_NMII_LINK1_FROM_IO_SHIFT) & ESC_GPR_CFG2_NMII_LINK1_FROM_IO_MASK) +#define ESC_GPR_CFG2_NMII_LINK1_FROM_IO_GET(x) (((uint32_t)(x) & ESC_GPR_CFG2_NMII_LINK1_FROM_IO_MASK) >> ESC_GPR_CFG2_NMII_LINK1_FROM_IO_SHIFT) + +/* + * NMII_LINK1_GPR (RW) + * + */ +#define ESC_GPR_CFG2_NMII_LINK1_GPR_MASK (0x1000000UL) +#define ESC_GPR_CFG2_NMII_LINK1_GPR_SHIFT (24U) +#define ESC_GPR_CFG2_NMII_LINK1_GPR_SET(x) (((uint32_t)(x) << ESC_GPR_CFG2_NMII_LINK1_GPR_SHIFT) & ESC_GPR_CFG2_NMII_LINK1_GPR_MASK) +#define ESC_GPR_CFG2_NMII_LINK1_GPR_GET(x) (((uint32_t)(x) & ESC_GPR_CFG2_NMII_LINK1_GPR_MASK) >> ESC_GPR_CFG2_NMII_LINK1_GPR_SHIFT) + +/* + * NMII_LINK0_FROM_IO (RW) + * + */ +#define ESC_GPR_CFG2_NMII_LINK0_FROM_IO_MASK (0x200000UL) +#define ESC_GPR_CFG2_NMII_LINK0_FROM_IO_SHIFT (21U) +#define ESC_GPR_CFG2_NMII_LINK0_FROM_IO_SET(x) (((uint32_t)(x) << ESC_GPR_CFG2_NMII_LINK0_FROM_IO_SHIFT) & ESC_GPR_CFG2_NMII_LINK0_FROM_IO_MASK) +#define ESC_GPR_CFG2_NMII_LINK0_FROM_IO_GET(x) (((uint32_t)(x) & ESC_GPR_CFG2_NMII_LINK0_FROM_IO_MASK) >> ESC_GPR_CFG2_NMII_LINK0_FROM_IO_SHIFT) + +/* + * NMII_LINK0_GPR (RW) + * + */ +#define ESC_GPR_CFG2_NMII_LINK0_GPR_MASK (0x100000UL) +#define ESC_GPR_CFG2_NMII_LINK0_GPR_SHIFT (20U) +#define ESC_GPR_CFG2_NMII_LINK0_GPR_SET(x) (((uint32_t)(x) << ESC_GPR_CFG2_NMII_LINK0_GPR_SHIFT) & ESC_GPR_CFG2_NMII_LINK0_GPR_MASK) +#define ESC_GPR_CFG2_NMII_LINK0_GPR_GET(x) (((uint32_t)(x) & ESC_GPR_CFG2_NMII_LINK0_GPR_MASK) >> ESC_GPR_CFG2_NMII_LINK0_GPR_SHIFT) + +/* Bitfield definition for register: PHY_CFG0 */ +/* + * MAC_SPEED (RW) + * + * 1:100M + */ +#define ESC_PHY_CFG0_MAC_SPEED_MASK (0x40000000UL) +#define ESC_PHY_CFG0_MAC_SPEED_SHIFT (30U) +#define ESC_PHY_CFG0_MAC_SPEED_SET(x) (((uint32_t)(x) << ESC_PHY_CFG0_MAC_SPEED_SHIFT) & ESC_PHY_CFG0_MAC_SPEED_MASK) +#define ESC_PHY_CFG0_MAC_SPEED_GET(x) (((uint32_t)(x) & ESC_PHY_CFG0_MAC_SPEED_MASK) >> ESC_PHY_CFG0_MAC_SPEED_SHIFT) + +/* + * PHY_OFFSET_VAL (RW) + * + */ +#define ESC_PHY_CFG0_PHY_OFFSET_VAL_MASK (0x1F000000UL) +#define ESC_PHY_CFG0_PHY_OFFSET_VAL_SHIFT (24U) +#define ESC_PHY_CFG0_PHY_OFFSET_VAL_SET(x) (((uint32_t)(x) << ESC_PHY_CFG0_PHY_OFFSET_VAL_SHIFT) & ESC_PHY_CFG0_PHY_OFFSET_VAL_MASK) +#define ESC_PHY_CFG0_PHY_OFFSET_VAL_GET(x) (((uint32_t)(x) & ESC_PHY_CFG0_PHY_OFFSET_VAL_MASK) >> ESC_PHY_CFG0_PHY_OFFSET_VAL_SHIFT) + +/* + * PORT2_RMII_EN (RW) + * + */ +#define ESC_PHY_CFG0_PORT2_RMII_EN_MASK (0x800000UL) +#define ESC_PHY_CFG0_PORT2_RMII_EN_SHIFT (23U) +#define ESC_PHY_CFG0_PORT2_RMII_EN_SET(x) (((uint32_t)(x) << ESC_PHY_CFG0_PORT2_RMII_EN_SHIFT) & ESC_PHY_CFG0_PORT2_RMII_EN_MASK) +#define ESC_PHY_CFG0_PORT2_RMII_EN_GET(x) (((uint32_t)(x) & ESC_PHY_CFG0_PORT2_RMII_EN_MASK) >> ESC_PHY_CFG0_PORT2_RMII_EN_SHIFT) + +/* + * PORT1_RMII_EN (RW) + * + */ +#define ESC_PHY_CFG0_PORT1_RMII_EN_MASK (0x8000U) +#define ESC_PHY_CFG0_PORT1_RMII_EN_SHIFT (15U) +#define ESC_PHY_CFG0_PORT1_RMII_EN_SET(x) (((uint32_t)(x) << ESC_PHY_CFG0_PORT1_RMII_EN_SHIFT) & ESC_PHY_CFG0_PORT1_RMII_EN_MASK) +#define ESC_PHY_CFG0_PORT1_RMII_EN_GET(x) (((uint32_t)(x) & ESC_PHY_CFG0_PORT1_RMII_EN_MASK) >> ESC_PHY_CFG0_PORT1_RMII_EN_SHIFT) + +/* + * PORT0_RMII_EN (RW) + * + */ +#define ESC_PHY_CFG0_PORT0_RMII_EN_MASK (0x80U) +#define ESC_PHY_CFG0_PORT0_RMII_EN_SHIFT (7U) +#define ESC_PHY_CFG0_PORT0_RMII_EN_SET(x) (((uint32_t)(x) << ESC_PHY_CFG0_PORT0_RMII_EN_SHIFT) & ESC_PHY_CFG0_PORT0_RMII_EN_MASK) +#define ESC_PHY_CFG0_PORT0_RMII_EN_GET(x) (((uint32_t)(x) & ESC_PHY_CFG0_PORT0_RMII_EN_MASK) >> ESC_PHY_CFG0_PORT0_RMII_EN_SHIFT) + +/* Bitfield definition for register: PHY_CFG1 */ +/* + * RMII_REFCLK_SEL (RW) + * + * 0:use RXCK as 50M refclk. 1:use TXCK as 50M refclk + */ +#define ESC_PHY_CFG1_RMII_REFCLK_SEL_MASK (0x700U) +#define ESC_PHY_CFG1_RMII_REFCLK_SEL_SHIFT (8U) +#define ESC_PHY_CFG1_RMII_REFCLK_SEL_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_RMII_REFCLK_SEL_SHIFT) & ESC_PHY_CFG1_RMII_REFCLK_SEL_MASK) +#define ESC_PHY_CFG1_RMII_REFCLK_SEL_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_RMII_REFCLK_SEL_MASK) >> ESC_PHY_CFG1_RMII_REFCLK_SEL_SHIFT) + +/* + * REFCK_25M_INV (RW) + * + */ +#define ESC_PHY_CFG1_REFCK_25M_INV_MASK (0x80U) +#define ESC_PHY_CFG1_REFCK_25M_INV_SHIFT (7U) +#define ESC_PHY_CFG1_REFCK_25M_INV_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_REFCK_25M_INV_SHIFT) & ESC_PHY_CFG1_REFCK_25M_INV_MASK) +#define ESC_PHY_CFG1_REFCK_25M_INV_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_REFCK_25M_INV_MASK) >> ESC_PHY_CFG1_REFCK_25M_INV_SHIFT) + +/* + * RMII_P2_RXCK_REFCLK_OE (RW) + * + */ +#define ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_MASK (0x40U) +#define ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_SHIFT (6U) +#define ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_SHIFT) & ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_MASK) +#define ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_MASK) >> ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_SHIFT) + +/* + * RMII_P1_RXCK_REFCLK_OE (RW) + * + */ +#define ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_MASK (0x20U) +#define ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_SHIFT (5U) +#define ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_SHIFT) & ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_MASK) +#define ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_MASK) >> ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_SHIFT) + +/* + * RMII_P0_RXCK_REFCLK_OE (RW) + * + */ +#define ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_MASK (0x10U) +#define ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_SHIFT (4U) +#define ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_SHIFT) & ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_MASK) +#define ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_MASK) >> ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_SHIFT) + +/* + * REFCK_25M_OE (RW) + * + */ +#define ESC_PHY_CFG1_REFCK_25M_OE_MASK (0x8U) +#define ESC_PHY_CFG1_REFCK_25M_OE_SHIFT (3U) +#define ESC_PHY_CFG1_REFCK_25M_OE_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_REFCK_25M_OE_SHIFT) & ESC_PHY_CFG1_REFCK_25M_OE_MASK) +#define ESC_PHY_CFG1_REFCK_25M_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_REFCK_25M_OE_MASK) >> ESC_PHY_CFG1_REFCK_25M_OE_SHIFT) + +/* + * RMII_P2_TXCK_REFCLK_OE (RW) + * + */ +#define ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_MASK (0x4U) +#define ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_SHIFT (2U) +#define ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_SHIFT) & ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_MASK) +#define ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_MASK) >> ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_SHIFT) + +/* + * RMII_P1_TXCK_REFCLK_OE (RW) + * + */ +#define ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_MASK (0x2U) +#define ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_SHIFT (1U) +#define ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_SHIFT) & ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_MASK) +#define ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_MASK) >> ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_SHIFT) + +/* + * RMII_P0_TXCK_REFCLK_OE (RW) + * + */ +#define ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_MASK (0x1U) +#define ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_SHIFT (0U) +#define ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_SHIFT) & ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_MASK) +#define ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_MASK) >> ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_SHIFT) + +/* Bitfield definition for register: GPIO_CTRL */ +/* + * SW_LATCH_GPI (WO) + * + * if gpi_trig_sel is set to 4'b1001, setting this bit will latch GPI to gpi_reg0/1 + */ +#define ESC_GPIO_CTRL_SW_LATCH_GPI_MASK (0x80000000UL) +#define ESC_GPIO_CTRL_SW_LATCH_GPI_SHIFT (31U) +#define ESC_GPIO_CTRL_SW_LATCH_GPI_SET(x) (((uint32_t)(x) << ESC_GPIO_CTRL_SW_LATCH_GPI_SHIFT) & ESC_GPIO_CTRL_SW_LATCH_GPI_MASK) +#define ESC_GPIO_CTRL_SW_LATCH_GPI_GET(x) (((uint32_t)(x) & ESC_GPIO_CTRL_SW_LATCH_GPI_MASK) >> ESC_GPIO_CTRL_SW_LATCH_GPI_SHIFT) + +/* + * SW_LATCH_GPO (WO) + * + * if gpo_trig_sel is set to 4'b1001, setting this bit will latch GPO to gpo_reg0/1 + */ +#define ESC_GPIO_CTRL_SW_LATCH_GPO_MASK (0x40000000UL) +#define ESC_GPIO_CTRL_SW_LATCH_GPO_SHIFT (30U) +#define ESC_GPIO_CTRL_SW_LATCH_GPO_SET(x) (((uint32_t)(x) << ESC_GPIO_CTRL_SW_LATCH_GPO_SHIFT) & ESC_GPIO_CTRL_SW_LATCH_GPO_MASK) +#define ESC_GPIO_CTRL_SW_LATCH_GPO_GET(x) (((uint32_t)(x) & ESC_GPIO_CTRL_SW_LATCH_GPO_MASK) >> ESC_GPIO_CTRL_SW_LATCH_GPO_SHIFT) + +/* + * GPI_OVERRIDE_EN (RW) + * + * set this bit will use GPI from the software register gpi_override0/1 + * clr to use GPI from pad directly + */ +#define ESC_GPIO_CTRL_GPI_OVERRIDE_EN_MASK (0x2000U) +#define ESC_GPIO_CTRL_GPI_OVERRIDE_EN_SHIFT (13U) +#define ESC_GPIO_CTRL_GPI_OVERRIDE_EN_SET(x) (((uint32_t)(x) << ESC_GPIO_CTRL_GPI_OVERRIDE_EN_SHIFT) & ESC_GPIO_CTRL_GPI_OVERRIDE_EN_MASK) +#define ESC_GPIO_CTRL_GPI_OVERRIDE_EN_GET(x) (((uint32_t)(x) & ESC_GPIO_CTRL_GPI_OVERRIDE_EN_MASK) >> ESC_GPIO_CTRL_GPI_OVERRIDE_EN_SHIFT) + +/* + * GPI_TRIG_EN (RW) + * + * use gpi_trig_sel can select the trigger event to latch GPI signal(from reg or pad) + * set to use triggered signal; + * clr to use signals direclty(from reg or pad) + * assign pdi_gpi = gpi_trig_en ? gpi_reg : + * (gpi_override_en ? gpi_override :pad_di_ecat_gpi); + */ +#define ESC_GPIO_CTRL_GPI_TRIG_EN_MASK (0x1000U) +#define ESC_GPIO_CTRL_GPI_TRIG_EN_SHIFT (12U) +#define ESC_GPIO_CTRL_GPI_TRIG_EN_SET(x) (((uint32_t)(x) << ESC_GPIO_CTRL_GPI_TRIG_EN_SHIFT) & ESC_GPIO_CTRL_GPI_TRIG_EN_MASK) +#define ESC_GPIO_CTRL_GPI_TRIG_EN_GET(x) (((uint32_t)(x) & ESC_GPIO_CTRL_GPI_TRIG_EN_MASK) >> ESC_GPIO_CTRL_GPI_TRIG_EN_SHIFT) + +/* + * GPI_TRIG_SEL (RW) + * + * select the trigger signal to latch GPI. + * 0000: SOF; 0001: EOF; 0010: pos of SYNC0; 0011: pos of SYNC1; + * 0100: pos of LATCH0; 0101: pos of LATCH1; 0110: neg of LATCH0; 0111: neg of LATCH1 + * 1000: wdog trigger; 1001: sw set gpio_ctrl[31]; + * others no trigger + */ +#define ESC_GPIO_CTRL_GPI_TRIG_SEL_MASK (0xF00U) +#define ESC_GPIO_CTRL_GPI_TRIG_SEL_SHIFT (8U) +#define ESC_GPIO_CTRL_GPI_TRIG_SEL_SET(x) (((uint32_t)(x) << ESC_GPIO_CTRL_GPI_TRIG_SEL_SHIFT) & ESC_GPIO_CTRL_GPI_TRIG_SEL_MASK) +#define ESC_GPIO_CTRL_GPI_TRIG_SEL_GET(x) (((uint32_t)(x) & ESC_GPIO_CTRL_GPI_TRIG_SEL_MASK) >> ESC_GPIO_CTRL_GPI_TRIG_SEL_SHIFT) + +/* + * GPO_TRIG_EN (RW) + * + * use gpo_trig_sel can select the trigger event to latch GPO signal(from core) + * set to use triggered signal; + * clr to use GPO signals direclty(from reg or pad) + */ +#define ESC_GPIO_CTRL_GPO_TRIG_EN_MASK (0x10U) +#define ESC_GPIO_CTRL_GPO_TRIG_EN_SHIFT (4U) +#define ESC_GPIO_CTRL_GPO_TRIG_EN_SET(x) (((uint32_t)(x) << ESC_GPIO_CTRL_GPO_TRIG_EN_SHIFT) & ESC_GPIO_CTRL_GPO_TRIG_EN_MASK) +#define ESC_GPIO_CTRL_GPO_TRIG_EN_GET(x) (((uint32_t)(x) & ESC_GPIO_CTRL_GPO_TRIG_EN_MASK) >> ESC_GPIO_CTRL_GPO_TRIG_EN_SHIFT) + +/* + * GPO_TRIG_SEL (RW) + * + * select the trigger signal to latch GPO. + * 0000: SOF; 0001: EOF; 0010: pos of SYNC0; 0011: pos of SYNC1; + * 0100: pos of LATCH0; 0101: pos of LATCH1; 0110: neg of LATCH0; 0111: neg of LATCH1 + * 1000: wdog trigger; 1001: sw set gpio_ctrl[30]; + * others no trigger + */ +#define ESC_GPIO_CTRL_GPO_TRIG_SEL_MASK (0xFU) +#define ESC_GPIO_CTRL_GPO_TRIG_SEL_SHIFT (0U) +#define ESC_GPIO_CTRL_GPO_TRIG_SEL_SET(x) (((uint32_t)(x) << ESC_GPIO_CTRL_GPO_TRIG_SEL_SHIFT) & ESC_GPIO_CTRL_GPO_TRIG_SEL_MASK) +#define ESC_GPIO_CTRL_GPO_TRIG_SEL_GET(x) (((uint32_t)(x) & ESC_GPIO_CTRL_GPO_TRIG_SEL_MASK) >> ESC_GPIO_CTRL_GPO_TRIG_SEL_SHIFT) + +/* Bitfield definition for register: GPI_OVERRIDE0 */ +/* + * GPR_OVERRIDE_LOW (RW) + * + */ +#define ESC_GPI_OVERRIDE0_GPR_OVERRIDE_LOW_MASK (0xFFFFFFFFUL) +#define ESC_GPI_OVERRIDE0_GPR_OVERRIDE_LOW_SHIFT (0U) +#define ESC_GPI_OVERRIDE0_GPR_OVERRIDE_LOW_SET(x) (((uint32_t)(x) << ESC_GPI_OVERRIDE0_GPR_OVERRIDE_LOW_SHIFT) & ESC_GPI_OVERRIDE0_GPR_OVERRIDE_LOW_MASK) +#define ESC_GPI_OVERRIDE0_GPR_OVERRIDE_LOW_GET(x) (((uint32_t)(x) & ESC_GPI_OVERRIDE0_GPR_OVERRIDE_LOW_MASK) >> ESC_GPI_OVERRIDE0_GPR_OVERRIDE_LOW_SHIFT) + +/* Bitfield definition for register: GPI_OVERRIDE1 */ +/* + * GPR_OVERRIDE_HIGH (RW) + * + */ +#define ESC_GPI_OVERRIDE1_GPR_OVERRIDE_HIGH_MASK (0xFFFFFFFFUL) +#define ESC_GPI_OVERRIDE1_GPR_OVERRIDE_HIGH_SHIFT (0U) +#define ESC_GPI_OVERRIDE1_GPR_OVERRIDE_HIGH_SET(x) (((uint32_t)(x) << ESC_GPI_OVERRIDE1_GPR_OVERRIDE_HIGH_SHIFT) & ESC_GPI_OVERRIDE1_GPR_OVERRIDE_HIGH_MASK) +#define ESC_GPI_OVERRIDE1_GPR_OVERRIDE_HIGH_GET(x) (((uint32_t)(x) & ESC_GPI_OVERRIDE1_GPR_OVERRIDE_HIGH_MASK) >> ESC_GPI_OVERRIDE1_GPR_OVERRIDE_HIGH_SHIFT) + +/* Bitfield definition for register: GPO_REG0 */ +/* + * VALUE (RO) + * + */ +#define ESC_GPO_REG0_VALUE_MASK (0xFFFFFFFFUL) +#define ESC_GPO_REG0_VALUE_SHIFT (0U) +#define ESC_GPO_REG0_VALUE_GET(x) (((uint32_t)(x) & ESC_GPO_REG0_VALUE_MASK) >> ESC_GPO_REG0_VALUE_SHIFT) + +/* Bitfield definition for register: GPO_REG1 */ +/* + * VALUE (RO) + * + */ +#define ESC_GPO_REG1_VALUE_MASK (0xFFFFFFFFUL) +#define ESC_GPO_REG1_VALUE_SHIFT (0U) +#define ESC_GPO_REG1_VALUE_GET(x) (((uint32_t)(x) & ESC_GPO_REG1_VALUE_MASK) >> ESC_GPO_REG1_VALUE_SHIFT) + +/* Bitfield definition for register: GPI_REG0 */ +/* + * VALUE (RO) + * + */ +#define ESC_GPI_REG0_VALUE_MASK (0xFFFFFFFFUL) +#define ESC_GPI_REG0_VALUE_SHIFT (0U) +#define ESC_GPI_REG0_VALUE_GET(x) (((uint32_t)(x) & ESC_GPI_REG0_VALUE_MASK) >> ESC_GPI_REG0_VALUE_SHIFT) + +/* Bitfield definition for register: GPI_REG1 */ +/* + * VALUE (RO) + * + */ +#define ESC_GPI_REG1_VALUE_MASK (0xFFFFFFFFUL) +#define ESC_GPI_REG1_VALUE_SHIFT (0U) +#define ESC_GPI_REG1_VALUE_GET(x) (((uint32_t)(x) & ESC_GPI_REG1_VALUE_MASK) >> ESC_GPI_REG1_VALUE_SHIFT) + +/* Bitfield definition for register: GPR_STATUS */ +/* + * NLINK2_PADSEL (RO) + * + */ +#define ESC_GPR_STATUS_NLINK2_PADSEL_MASK (0xF0000000UL) +#define ESC_GPR_STATUS_NLINK2_PADSEL_SHIFT (28U) +#define ESC_GPR_STATUS_NLINK2_PADSEL_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_NLINK2_PADSEL_MASK) >> ESC_GPR_STATUS_NLINK2_PADSEL_SHIFT) + +/* + * NLINK1_PADSEL (RO) + * + */ +#define ESC_GPR_STATUS_NLINK1_PADSEL_MASK (0xF000000UL) +#define ESC_GPR_STATUS_NLINK1_PADSEL_SHIFT (24U) +#define ESC_GPR_STATUS_NLINK1_PADSEL_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_NLINK1_PADSEL_MASK) >> ESC_GPR_STATUS_NLINK1_PADSEL_SHIFT) + +/* + * NLINK0_PADSEL (RO) + * + */ +#define ESC_GPR_STATUS_NLINK0_PADSEL_MASK (0xF00000UL) +#define ESC_GPR_STATUS_NLINK0_PADSEL_SHIFT (20U) +#define ESC_GPR_STATUS_NLINK0_PADSEL_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_NLINK0_PADSEL_MASK) >> ESC_GPR_STATUS_NLINK0_PADSEL_SHIFT) + +/* + * PDI_SOF (RO) + * + */ +#define ESC_GPR_STATUS_PDI_SOF_MASK (0x80000UL) +#define ESC_GPR_STATUS_PDI_SOF_SHIFT (19U) +#define ESC_GPR_STATUS_PDI_SOF_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_PDI_SOF_MASK) >> ESC_GPR_STATUS_PDI_SOF_SHIFT) + +/* + * PDI_EOF (RO) + * + */ +#define ESC_GPR_STATUS_PDI_EOF_MASK (0x40000UL) +#define ESC_GPR_STATUS_PDI_EOF_SHIFT (18U) +#define ESC_GPR_STATUS_PDI_EOF_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_PDI_EOF_MASK) >> ESC_GPR_STATUS_PDI_EOF_SHIFT) + +/* + * PDI_WD_TRIGGER (RO) + * + */ +#define ESC_GPR_STATUS_PDI_WD_TRIGGER_MASK (0x20000UL) +#define ESC_GPR_STATUS_PDI_WD_TRIGGER_SHIFT (17U) +#define ESC_GPR_STATUS_PDI_WD_TRIGGER_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_PDI_WD_TRIGGER_MASK) >> ESC_GPR_STATUS_PDI_WD_TRIGGER_SHIFT) + +/* + * PDI_WD_STATE (RO) + * + */ +#define ESC_GPR_STATUS_PDI_WD_STATE_MASK (0x10000UL) +#define ESC_GPR_STATUS_PDI_WD_STATE_SHIFT (16U) +#define ESC_GPR_STATUS_PDI_WD_STATE_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_PDI_WD_STATE_MASK) >> ESC_GPR_STATUS_PDI_WD_STATE_SHIFT) + +/* + * SYNC_OUT1 (RO) + * + */ +#define ESC_GPR_STATUS_SYNC_OUT1_MASK (0x200U) +#define ESC_GPR_STATUS_SYNC_OUT1_SHIFT (9U) +#define ESC_GPR_STATUS_SYNC_OUT1_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_SYNC_OUT1_MASK) >> ESC_GPR_STATUS_SYNC_OUT1_SHIFT) + +/* + * SYNC_OUT0 (RO) + * + */ +#define ESC_GPR_STATUS_SYNC_OUT0_MASK (0x100U) +#define ESC_GPR_STATUS_SYNC_OUT0_SHIFT (8U) +#define ESC_GPR_STATUS_SYNC_OUT0_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_SYNC_OUT0_MASK) >> ESC_GPR_STATUS_SYNC_OUT0_SHIFT) + +/* + * LED_STATE_RUN (RO) + * + */ +#define ESC_GPR_STATUS_LED_STATE_RUN_MASK (0x40U) +#define ESC_GPR_STATUS_LED_STATE_RUN_SHIFT (6U) +#define ESC_GPR_STATUS_LED_STATE_RUN_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_LED_STATE_RUN_MASK) >> ESC_GPR_STATUS_LED_STATE_RUN_SHIFT) + +/* + * LED_ERR (RO) + * + */ +#define ESC_GPR_STATUS_LED_ERR_MASK (0x20U) +#define ESC_GPR_STATUS_LED_ERR_SHIFT (5U) +#define ESC_GPR_STATUS_LED_ERR_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_LED_ERR_MASK) >> ESC_GPR_STATUS_LED_ERR_SHIFT) + +/* + * LED_RUN (RO) + * + */ +#define ESC_GPR_STATUS_LED_RUN_MASK (0x10U) +#define ESC_GPR_STATUS_LED_RUN_SHIFT (4U) +#define ESC_GPR_STATUS_LED_RUN_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_LED_RUN_MASK) >> ESC_GPR_STATUS_LED_RUN_SHIFT) + +/* + * DEV_STATE (RO) + * + */ +#define ESC_GPR_STATUS_DEV_STATE_MASK (0x8U) +#define ESC_GPR_STATUS_DEV_STATE_SHIFT (3U) +#define ESC_GPR_STATUS_DEV_STATE_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_DEV_STATE_MASK) >> ESC_GPR_STATUS_DEV_STATE_SHIFT) + +/* + * LINK_ACT (RO) + * + */ +#define ESC_GPR_STATUS_LINK_ACT_MASK (0x7U) +#define ESC_GPR_STATUS_LINK_ACT_SHIFT (0U) +#define ESC_GPR_STATUS_LINK_ACT_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_LINK_ACT_MASK) >> ESC_GPR_STATUS_LINK_ACT_SHIFT) + +/* Bitfield definition for register array: IO_CFG */ +/* + * INVERT (RW) + * + * 1:invert the IO + */ +#define ESC_IO_CFG_INVERT_MASK (0x10U) +#define ESC_IO_CFG_INVERT_SHIFT (4U) +#define ESC_IO_CFG_INVERT_SET(x) (((uint32_t)(x) << ESC_IO_CFG_INVERT_SHIFT) & ESC_IO_CFG_INVERT_MASK) +#define ESC_IO_CFG_INVERT_GET(x) (((uint32_t)(x) & ESC_IO_CFG_INVERT_MASK) >> ESC_IO_CFG_INVERT_SHIFT) + +/* + * FUNC_ALT (RW) + * + * IO usage: + * 0:NMII_LINK0 + * 1:NMII_LINK1 + * 2:NMII_LINK2 + * 3:LINK_ACT0 + * 4:LINK_ACT1 + * 5:LINK_ACT2 + * 6:LED_RUN + * 7:LED_ERR + * 8:RESET_OUT + */ +#define ESC_IO_CFG_FUNC_ALT_MASK (0xFU) +#define ESC_IO_CFG_FUNC_ALT_SHIFT (0U) +#define ESC_IO_CFG_FUNC_ALT_SET(x) (((uint32_t)(x) << ESC_IO_CFG_FUNC_ALT_SHIFT) & ESC_IO_CFG_FUNC_ALT_MASK) +#define ESC_IO_CFG_FUNC_ALT_GET(x) (((uint32_t)(x) & ESC_IO_CFG_FUNC_ALT_MASK) >> ESC_IO_CFG_FUNC_ALT_SHIFT) + + + +/* RX_ERR_CNT register group index macro definition */ +#define ESC_RX_ERR_CNT_PORT0 (0UL) +#define ESC_RX_ERR_CNT_PORT1 (1UL) +#define ESC_RX_ERR_CNT_PORT2 (2UL) +#define ESC_RX_ERR_CNT_PORT3 (3UL) + +/* FWD_RX_ERR_CNT register group index macro definition */ +#define ESC_FWD_RX_ERR_CNT_PORT0 (0UL) +#define ESC_FWD_RX_ERR_CNT_PORT1 (1UL) +#define ESC_FWD_RX_ERR_CNT_PORT2 (2UL) +#define ESC_FWD_RX_ERR_CNT_PORT3 (3UL) + +/* LOST_LINK_CNT register group index macro definition */ +#define ESC_LOST_LINK_CNT_PORT0 (0UL) +#define ESC_LOST_LINK_CNT_PORT1 (1UL) +#define ESC_LOST_LINK_CNT_PORT2 (2UL) +#define ESC_LOST_LINK_CNT_PORT3 (3UL) + +/* PHY_STAT register group index macro definition */ +#define ESC_PHY_STAT_PORT0 (0UL) +#define ESC_PHY_STAT_PORT1 (1UL) +#define ESC_PHY_STAT_PORT2 (2UL) +#define ESC_PHY_STAT_PORT3 (3UL) + +/* FMMU register group index macro definition */ +#define ESC_FMMU_0 (0UL) +#define ESC_FMMU_1 (1UL) +#define ESC_FMMU_2 (2UL) +#define ESC_FMMU_3 (3UL) +#define ESC_FMMU_4 (4UL) +#define ESC_FMMU_5 (5UL) +#define ESC_FMMU_6 (6UL) +#define ESC_FMMU_7 (7UL) + +/* SYNCM register group index macro definition */ +#define ESC_SYNCM_0 (0UL) +#define ESC_SYNCM_1 (1UL) +#define ESC_SYNCM_2 (2UL) +#define ESC_SYNCM_3 (3UL) +#define ESC_SYNCM_4 (4UL) +#define ESC_SYNCM_5 (5UL) +#define ESC_SYNCM_6 (6UL) +#define ESC_SYNCM_7 (7UL) + +/* RCV_TIME register group index macro definition */ +#define ESC_RCV_TIME_PORT0 (0UL) +#define ESC_RCV_TIME_PORT1 (1UL) +#define ESC_RCV_TIME_PORT2 (2UL) +#define ESC_RCV_TIME_PORT3 (3UL) + +/* IO_CFG register group index macro definition */ +#define ESC_IO_CFG_CTR0 (0UL) +#define ESC_IO_CFG_CTR1 (1UL) +#define ESC_IO_CFG_CTR2 (2UL) +#define ESC_IO_CFG_CTR3 (3UL) +#define ESC_IO_CFG_CTR4 (4UL) +#define ESC_IO_CFG_CTR5 (5UL) +#define ESC_IO_CFG_CTR6 (6UL) +#define ESC_IO_CFG_CTR7 (7UL) +#define ESC_IO_CFG_CTR8 (8UL) + + +#endif /* HPM_ESC_H */ diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_mii.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_mii.h new file mode 100644 index 00000000..bd1ee182 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_mii.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef CHRY_MII_H +#define CHRY_MII_H + +/* Generic MII registers. */ +#define MII_BMCR 0x00 /* Basic Mode Control Register */ +#define MII_BMSR 0x01 /* Basic Mode Status Register */ +#define MII_PHYSID1 0x02 /* PHY Identifier Register #1 */ +#define MII_PHYSID2 0x03 /* PHY Identifier Register #2 */ +#define MII_ANAR 0x04 /* Auto-Negotiation Advertisement Register */ +#define MII_ANLPAR 0x05 /* Auto-Negotiation Link Partner Ability Register */ +#define MII_ANER 0x06 /* Auto-Negotiate Expansion Register */ +#define MII_ANNPTR 0x07 /* Auto-Negotiation Next Page Transmit Register */ +#define MII_ANNPRR 0x08 /* Auto-Negotiation Next Page Receive Register */ +#define MII_GBCR 0x09 /* 1000Base-T Control Register */ +#define MII_GBSR 0x0a /* 1000Base-T Status Register */ +#define MII_GBESR 0x0f /* 1000Base-T Extended Status Register */ + +/* Basic Mode Control Register. */ +#define BMCR_RESET (1 << 15) /* Reset to default state */ +#define BMCR_LOOPBACK (1 << 14) /* TXD loopback bits */ +#define BMCR_SPEED100 (1 << 13) /* Select 100Mbps or 10Mbps */ +#define BMCR_ANENABLE (1 << 12) /* Enable auto negotiation */ +#define BMCR_POWERDOWN (1 << 11) /* Enable low power state */ +#define BMCR_ISOLATE (1 << 10) /* Isolate data paths from MII */ +#define BMCR_ANRESTART (1 << 9) /* Auto negotiation restart */ +#define BMCR_FULLDPLX (1 << 8) /* Full duplex */ +#define BMCR_CTST (1 << 7) /* Collision test */ +#define BMCR_SPEED1000 (1 << 6) /* MSB of Speed (1000) */ +#define BMCR_RESV 0x003f /* Unused... */ + +/* Basic Mode Status Register. */ +#define BMSR_100T4 (1 << 15) /* Enable 100Base-T4 support */ +#define BMSR_100FULL (1 << 14) /* Enable 100Base-TX full duplex support */ +#define BMSR_100HALF (1 << 13) /* Enable 100Base-TX half duplex support */ +#define BMSR_10FULL (1 << 12) /* Enable 10Base-TX full duplex support */ +#define BMSR_10HALF (1 << 11) /* Enable 10Base-TX half duplex support */ +#define BMSR_100HALF2 (1 << 10) /* Can do 100BASE-T2 HDX */ +#define BMSR_100FULL2 (1 << 9) /* Can do 100BASE-T2 FDX */ +#define BMSR_ESTATEN (1 << 8) /* Extended Status in R15 */ +#define BMSR_ANEGCOMPLETE (1 << 5) /* Auto-negotiation complete */ +#define BMSR_REMOTEFAULT (1 << 4) /* Remote fault detected */ +#define BMSR_ANEGCAPABLE (1 << 3) /* Able to do auto-negotiation */ +#define BMSR_LINKSTATUS (1 << 2) /* Link status */ +#define BMSR_JCD (1 << 1) /* Jabber detected */ +#define BMSR_ERCAP (1 << 0) /* Ext-reg capability */ + +/* Auto-Negotiation Advertisement Register. */ +#define ANAR_NPAGE (1 << 15) /* Next page bit */ +#define ANAR_ACK (1 << 14) /* Link partner acknowledges reception of local node’s capability data word */ +#define ANAR_REMOTEFAULT (1 << 13) /* Link partner is indicating a remote fault */ +#define ANAR_ASYM_PAUSE (1 << 11) /* Try for asymetric pause */ +#define ANAR_PAUSE (1 << 10) /* Try for pause */ +#define ANAR_100T4 (1 << 9) /* 100Base-T4 is supported by local mode */ +#define ANAR_100FULL (1 << 8) /* 100Base-TX full duplex is supported by local mode */ +#define ANAR_100HALF (1 << 7) /* 100Base-TX half duplex is supported by local mode */ +#define ANAR_10FULL (1 << 6) /* 10Base-TX full duplex is supported by local mode */ +#define ANAR_10HALF (1 << 5) /* 10Base-TX half duplex is supported by local mode */ +#define ANAR_SLCT 0x001f /* Selector bits */ +#define ANAR_CSMA 0x0001 /* Only selector supported */ + +#define ANAR_SPEED_ALL (ANAR_10HALF | ANAR_10FULL | \ + ANAR_100HALF | ANAR_100FULL) + +/* Auto-Negotiation Link Partner Ability Register. */ +#define ANLPAR_NPAGE (1 << 15) /* Next page bit */ +#define ANLPAR_ACK (1 << 14) /* Link partner acknowledges reception of local node’s capability data word */ +#define ANLPAR_REMOTEFAULT (1 << 13) /* Link partner is indicating a remote fault */ +#define ANLPAR_ASYM_PAUSE (1 << 11) /* Try for asymetric pause */ +#define ANLPAR_PAUSE (1 << 10) /* Try for pause */ +#define ANLPAR_100T4 (1 << 9) /* 100Base-T4 is supported by local mode */ +#define ANLPAR_100FULL (1 << 8) /* 100Base-TX full duplex is supported by local mode */ +#define ANLPAR_100HALF (1 << 7) /* 100Base-TX half duplex is supported by local mode */ +#define ANLPAR_10FULL (1 << 6) /* 10Base-TX full duplex is supported by local mode */ +#define ANLPAR_10HALF (1 << 5) /* 10Base-TX half duplex is supported by local mode */ +#define ANLPAR_SLCT 0x001f /* Selector bits */ +#define ANLPAR_CSMA 0x0001 /* Only selector supported */ + +/* 1000Base-T Control Register */ +#define GBCR_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */ +#define GBCR_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */ +#define GBCR_PREFER_MASTER 0x0400 /* prefer to operate as master */ +#define GBCR_AS_MASTER 0x0800 +#define GBCR_ENABLE_MASTER 0x1000 + +/* 1000Base-T Status Register */ +#define GBSR_1000MSFAIL 0x8000 /* Master/Slave resolution failure */ +#define GBSR_1000MSRES 0x4000 /* Master/Slave resolution status */ +#define GBSR_1000LOCALRXOK 0x2000 /* Link partner local receiver status */ +#define GBSR_1000REMRXOK 0x1000 /* Link partner remote receiver status */ +#define GBSR_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */ +#define GBSR_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */ + +/* 1000Base-T Extended Status Register */ +#define GBESR_1000_XFULL 0x8000 /* Can do 1000BaseX Full */ +#define GBESR_1000_XHALF 0x4000 /* Can do 1000BaseX Half */ +#define GBESR_1000_TFULL 0x2000 /* Can do 1000BT Full */ +#define GBESR_1000_THALF 0x1000 /* Can do 1000BT Half */ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy.h new file mode 100644 index 00000000..97440c36 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef CHRY_PHY_H +#define CHRY_PHY_H + +#include +#include +#include +#include +#include + +#include "chry_mii.h" + +struct chry_phy_config { + bool loopback; + bool auto_negotiation; + bool duplex; + uint16_t speed; +}; + +struct chry_phy_status { + bool link; + bool duplex; + uint16_t speed; +}; + +struct chry_phy_device; +struct chry_phy_driver { + char *phy_name; + char *phy_desc; + uint32_t phy_id; + uint32_t phy_id_mask; + void (*phy_init)(struct chry_phy_device *phydev, struct chry_phy_config *config); + void (*phy_get_status)(struct chry_phy_device *phydev, struct chry_phy_status *status); +}; + +struct chry_phy_support { + uint32_t support_100base_t4 : 1; + uint32_t support_1000base_tx_full : 1; + uint32_t support_1000base_tx_half : 1; + uint32_t support_100base_tx_full : 1; + uint32_t support_100base_tx_half : 1; + uint32_t support_10base_tx_full : 1; + uint32_t support_10base_tx_half : 1; + uint32_t support_asym_pause : 1; + uint32_t support_pause : 1; + uint32_t support_autoeng : 1; + + uint32_t reserved : 22; +}; + +struct chry_phy_device { + uint16_t phy_addr; + uint32_t phy_id; + struct chry_phy_support support; + const struct chry_phy_driver *driver; + void (*mdio_write)(struct chry_phy_device *phydev, uint16_t phy_addr, uint16_t regnum, uint16_t val); + uint16_t (*mdio_read)(struct chry_phy_device *phydev, uint16_t phy_addr, uint16_t regnum); + void *user_data; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +int chry_phy_init(struct chry_phy_device *phydev, struct chry_phy_config *config); +void chry_phy_get_status(struct chry_phy_device *phydev, struct chry_phy_status *status); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_dp83847.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_dp83847.h new file mode 100644 index 00000000..0b0078d4 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_dp83847.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "chry_phy.h" + +#define DP83847_PHYSTS 0x11 /* PHY Status Register */ + +#define DP83847_PHYSTS_LINK_STATUS (0x400U) +/* + * SPEED (RO) + * + * Link Speed. + * 11: Reserved 10: 1000Mbps + * 01: 100Mbps 00: 10Mbps + */ +#define DP83847_PHYSTS_SPEED_STATUS (0xC000U) +#define DP83847_PHYSTS_DUPLEX_STATUS (0x2000U) + +void dp83847_phy_init(struct chry_phy_device *phydev, struct chry_phy_config *config) +{ +} + +void dp83847_phy_get_status(struct chry_phy_device *phydev, struct chry_phy_status *status) +{ + uint16_t regval; + + regval = phydev->mdio_read(phydev, phydev->phy_addr, DP83847_PHYSTS); + + status->link = regval & DP83847_PHYSTS_LINK_STATUS; + + if (status->link) { + status->duplex = regval & DP83847_PHYSTS_DUPLEX_STATUS; + + switch ((regval & DP83847_PHYSTS_SPEED_STATUS) >> 14) { + case 0: + status->speed = 10; + break; + case 1: + status->speed = 100; + break; + case 2: + status->speed = 1000; + break; + + default: + break; + } + } +} + +const struct chry_phy_driver dp83847_driver = { + .phy_id = 0x2000A230, + .phy_id_mask = 0xFFFFFFF0, + .phy_name = "DP83847", + .phy_desc = "TI DP83847 Ethernet PHY", + .phy_init = dp83847_phy_init, + .phy_get_status = dp83847_phy_get_status, +}; \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_dp83848.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_dp83848.h new file mode 100644 index 00000000..ffa4619a --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_dp83848.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "chry_phy.h" + +#define DP83848_PHYSTS 0x10 /* PHY Status Register */ + +#define DP83848_PHYSTS_LINK_STATUS (0x0001U) +/* + * SPEED_STATUS (RO) + * + * Speed10: + * This bit indicates the status of the speed and is determined from Auto-Negotiation or Forced + * Modes. + * 1 = 10 Mb/s mode. + * 0 = 100 Mb/s mode. + * Note: This bit is only valid if Auto-Negotiation is enabled and complete and there is a valid + * link or if Auto-Negotiation is disabled and there is a valid link. + */ +#define DP83848_PHYSTS_SPEED_STATUS (0x0002U) +#define DP83848_PHYSTS_DUPLEX_STATUS (0x0004U) + +void dp83848_phy_init(struct chry_phy_device *phydev, struct chry_phy_config *config) +{ +} + +void dp83848_phy_get_status(struct chry_phy_device *phydev, struct chry_phy_status *status) +{ + uint16_t regval; + + regval = phydev->mdio_read(phydev, phydev->phy_addr, DP83848_PHYSTS); + + status->link = regval & DP83848_PHYSTS_LINK_STATUS; + + if (status->link) { + status->duplex = regval & DP83848_PHYSTS_DUPLEX_STATUS; + status->speed = (regval & DP83848_PHYSTS_SPEED_STATUS) ? 10 : 100; + } +} + +const struct chry_phy_driver dp83848_driver = { + .phy_id = 0x20005C90, + .phy_id_mask = 0xFFFFFFF0, + .phy_name = "DP83848", + .phy_desc = "TI DP83848 Ethernet PHY", + .phy_init = dp83848_phy_init, + .phy_get_status = dp83848_phy_get_status, +}; \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_jl1111.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_jl1111.h new file mode 100644 index 00000000..ac9290d6 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_jl1111.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "chry_phy.h" + +void jl1111_phy_init(struct chry_phy_device *phydev, struct chry_phy_config *config) +{ +} + +void jl1111_phy_get_status(struct chry_phy_device *phydev, struct chry_phy_status *status) +{ + uint16_t regval; + + regval = phydev->mdio_read(phydev, phydev->phy_addr, MII_BMSR); + status->link = regval & BMSR_LINKSTATUS; + + if (status->link) { + regval = phydev->mdio_read(phydev, phydev->phy_addr, MII_ANAR) & phydev->mdio_read(phydev, phydev->phy_addr, MII_ANLPAR); + + if (regval & ANAR_100HALF) { + if (regval & ANAR_100FULL) { + status->speed = 100; + status->duplex = true; + } else { + status->speed = 100; + status->duplex = false; + } + } else if (regval & ANAR_10HALF) { + if (regval & ANAR_10FULL) { + status->speed = 10; + status->duplex = true; + } else { + status->speed = 10; + status->duplex = false; + } + } + } +} + +const struct chry_phy_driver jl1111_driver = { + .phy_id = 0x937C4020, + .phy_id_mask = 0xFFFFFFF0, + .phy_name = "JL1111", + .phy_desc = "JLSemi JL1111 Ethernet PHY", + .phy_init = jl1111_phy_init, + .phy_get_status = jl1111_phy_get_status, +}; \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_ksz8081.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_ksz8081.h new file mode 100644 index 00000000..3f5808c5 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_ksz8081.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "chry_phy.h" + +#define KSZ8081_PHY_CONTROL1 0x1EU /*!< The PHY control one register. */ +#define KSZ8081_PHY_CONTROL2 0x1FU /*!< The PHY control two register. */ + +#define KSZ8081_PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */ + +void ksz8081_phy_init(struct chry_phy_device *phydev, struct chry_phy_config *config) +{ + uint16_t regval; + + regval = phydev->mdio_read(phydev, phydev->phy_addr, KSZ8081_PHY_CONTROL2); + phydev->mdio_write(phydev, phydev->phy_addr, KSZ8081_PHY_CONTROL2, (regval | KSZ8081_PHY_CTL2_REFCLK_SELECT_MASK)); +} + +void ksz8081_phy_get_status(struct chry_phy_device *phydev, struct chry_phy_status *status) +{ + uint16_t regval; + + regval = phydev->mdio_read(phydev, phydev->phy_addr, KSZ8081_PHY_CONTROL1); + status->link = regval & (1 << 8); + + if (status->link) { + regval &= 0x07; + + switch (regval) { + case 0x01: + status->speed = 10; + status->duplex = false; + break; + case 0x02: + status->speed = 100; + status->duplex = false; + break; + case 0x05: + status->speed = 10; + status->duplex = true; + break; + case 0x06: + status->speed = 100; + status->duplex = true; + break; + + default: + break; + } + } +} + +const struct chry_phy_driver ksz8081_driver = { + .phy_id = 0x00221560, + .phy_id_mask = 0xFFFFFFF0, + .phy_name = "KSZ8081", + .phy_desc = "MICROCHIP KSZ8081 Ethernet PHY", + .phy_init = ksz8081_phy_init, + .phy_get_status = ksz8081_phy_get_status, +}; \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_lan8720.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_lan8720.h new file mode 100644 index 00000000..d98c3818 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_lan8720.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "chry_phy.h" + +#define LAN8720_PSCSR 31 /* PHY Special Control/Status Register */ + +#define LAN8720_PSCSR_DUPLEX_STATUS (0x10U) +/* + * SPEED (RO) + * + * HCDSPEED value: + * 01 = 10BASE-T + * 10 = 100BASE-TX + */ +#define LAN8720_PSCSR_SPEED_STATUS (0xCU) + +void lan8720_phy_init(struct chry_phy_device *phydev, struct chry_phy_config *config) +{ +} + +void lan8720_phy_get_status(struct chry_phy_device *phydev, struct chry_phy_status *status) +{ + uint16_t regval; + + regval = phydev->mdio_read(phydev, phydev->phy_addr, MII_BMSR); + status->link = regval & BMSR_LINKSTATUS; + + if (status->link) { + regval = phydev->mdio_read(phydev, phydev->phy_addr, LAN8720_PSCSR); + status->duplex = regval & LAN8720_PSCSR_DUPLEX_STATUS; + + switch ((regval & LAN8720_PSCSR_SPEED_STATUS) >> 2) { + case 1: + status->speed = 10; + break; + case 2: + status->speed = 100; + break; + + default: + break; + } + } +} + +const struct chry_phy_driver lan8720_driver = { + .phy_id = 0x0007C0F0, + .phy_id_mask = 0xFFFFFFF0, + .phy_name = "LAN8720", + .phy_desc = "MICROCHIP LAN8720 Ethernet PHY", + .phy_init = lan8720_phy_init, + .phy_get_status = lan8720_phy_get_status, +}; \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_rtl8201.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_rtl8201.h new file mode 100644 index 00000000..00dd4faf --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_rtl8201.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "chry_phy.h" + +#define RTL8201_RMSR_P7 16 /* RMII Mode Setting Register */ +#define RTL8201_PAGESEL 31 /* Page Select Register */ + +/* + * RG_RMII_CLKDIR (RW) + * + * This Bit Sets the Type of TXC in RMII Mode. + * 0: Output + * 1: Input + */ +#define RTL8201_RMSR_P7_RG_RMII_CLKDIR_MASK (0x1000U) +#define RTL8201_RMSR_P7_RG_RMII_CLKDIR_SHIFT (12U) +#define RTL8201_RMSR_P7_RG_RMII_CLKDIR_SET(x) (((uint16_t)(x) << RTL8201_RMSR_P7_RG_RMII_CLKDIR_SHIFT) & RTL8201_RMSR_P7_RG_RMII_CLKDIR_MASK) +#define RTL8201_RMSR_P7_RG_RMII_CLKDIR_GET(x) (((uint16_t)(x)&RTL8201_RMSR_P7_RG_RMII_CLKDIR_MASK) >> RTL8201_RMSR_P7_RG_RMII_CLKDIR_SHIFT) + +void rtl8201_phy_init(struct chry_phy_device *phydev, struct chry_phy_config *config) +{ + uint16_t regval; + + phydev->mdio_write(phydev, phydev->phy_addr, RTL8201_PAGESEL, 7); + + regval = phydev->mdio_read(phydev, phydev->phy_addr, RTL8201_RMSR_P7); + regval &= ~RTL8201_RMSR_P7_RG_RMII_CLKDIR_MASK; + regval |= RTL8201_RMSR_P7_RG_RMII_CLKDIR_SET(1); + phydev->mdio_write(phydev, phydev->phy_addr, RTL8201_RMSR_P7, regval); +} + +void rtl8201_phy_get_status(struct chry_phy_device *phydev, struct chry_phy_status *status) +{ + uint16_t regval; + + regval = phydev->mdio_read(phydev, phydev->phy_addr, MII_BMSR); + status->link = regval & BMSR_LINKSTATUS; + + if (status->link) { + regval = phydev->mdio_read(phydev, phydev->phy_addr, MII_BMCR); + status->speed = regval & BMCR_SPEED100 ? 100 : 10; + status->duplex = regval & BMCR_FULLDPLX; + } +} + +const struct chry_phy_driver rtl8201_driver = { + .phy_id = 0x001CC810, + .phy_id_mask = 0xFFFFFFF0, + .phy_name = "RTL8201", + .phy_desc = "REALTEK RTL8201 Ethernet PHY", + .phy_init = rtl8201_phy_init, + .phy_get_status = rtl8201_phy_get_status, +}; \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_rtl8211.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_rtl8211.h new file mode 100644 index 00000000..27dd44d3 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_rtl8211.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "chry_phy.h" + +#define RTL8211_PHYSR 17 /* PHY Specific Status Register */ + +#define RTL8211_PHYSTS_LINK_STATUS (0x400U) +/* + * SPEED (RO) + * + * Link Speed. + * 11: Reserved 10: 1000Mbps + * 01: 100Mbps 00: 10Mbps + */ +#define RTL8211_PHYSTS_SPEED_STATUS (0xC000U) +#define RTL8211_PHYSTS_DUPLEX_STATUS (0x2000U) + +void rtl8211_phy_init(struct chry_phy_device *phydev, struct chry_phy_config *config) +{ +} + +void rtl8211_phy_get_status(struct chry_phy_device *phydev, struct chry_phy_status *status) +{ + uint16_t regval; + + regval = phydev->mdio_read(phydev, phydev->phy_addr, RTL8211_PHYSR); + + status->link = regval & RTL8211_PHYSTS_LINK_STATUS; + + if (status->link) { + status->duplex = regval & RTL8211_PHYSTS_DUPLEX_STATUS; + + switch ((regval & RTL8211_PHYSTS_SPEED_STATUS) >> 14) { + case 0: + status->speed = 10; + break; + case 1: + status->speed = 100; + break; + case 2: + status->speed = 1000; + break; + + default: + break; + } + } +} + +const struct chry_phy_driver rtl8211_driver = { + .phy_id = 0x001CC910, + .phy_id_mask = 0xFFFFFFF0, + .phy_name = "RTL8211", + .phy_desc = "REALTEK RTL8211 Ethernet PHY", + .phy_init = rtl8211_phy_init, + .phy_get_status = rtl8211_phy_get_status, +}; \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_yt8522.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_yt8522.h new file mode 100644 index 00000000..af66903b --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/include/phy/chry_phy_yt8522.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "chry_phy.h" + +#define YT8522_PHYSTS 0x11 /* PHY Status Register */ + +#define YT8522_PHYSTS_LINK_STATUS (0x400U) +/* + * SPEED (RO) + * + * Link Speed. + * 11: Reserved 10: 1000Mbps + * 01: 100Mbps 00: 10Mbps + */ +#define YT8522_PHYSTS_SPEED_STATUS (0xC000U) +#define YT8522_PHYSTS_DUPLEX_STATUS (0x2000U) + +void yt8522_phy_init(struct chry_phy_device *phydev, struct chry_phy_config *config) +{ +} + +void yt8522_phy_get_status(struct chry_phy_device *phydev, struct chry_phy_status *status) +{ + uint16_t regval; + + regval = phydev->mdio_read(phydev, phydev->phy_addr, YT8522_PHYSTS); + + status->link = regval & YT8522_PHYSTS_LINK_STATUS; + + if (status->link) { + status->duplex = regval & YT8522_PHYSTS_DUPLEX_STATUS; + + switch ((regval & YT8522_PHYSTS_SPEED_STATUS) >> 14) { + case 0: + status->speed = 10; + break; + case 1: + status->speed = 100; + break; + case 2: + status->speed = 1000; + break; + + default: + break; + } + } +} + +const struct chry_phy_driver yt8522_driver = { + .phy_id = 0x4F51E900, + .phy_id_mask = 0xFFFFFFC0, + .phy_name = "YT8512/YT8522/YT8531", + .phy_desc = "MOTOR COMM YT8512/YT8522/YT8531 Ethernet PHY", + .phy_init = yt8522_phy_init, + .phy_get_status = yt8522_phy_get_status, +}; \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/osal/ec_osal_freertos.c b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/osal/ec_osal_freertos.c new file mode 100644 index 00000000..b005fc71 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/osal/ec_osal_freertos.c @@ -0,0 +1,208 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "ec_master.h" +#include +#include "semphr.h" +#include "event_groups.h" + +ec_osal_thread_t ec_osal_thread_create(const char *name, uint32_t stack_size, uint32_t prio, ec_thread_entry_t entry, void *args) +{ + TaskHandle_t htask = NULL; + stack_size /= sizeof(StackType_t); + xTaskCreate(entry, name, stack_size, args, configMAX_PRIORITIES - 1 - prio, &htask); + if (htask == NULL) { + EC_LOG_ERR("Create thread %s failed\r\n", name); + while (1) { + } + } + return (ec_osal_thread_t)htask; +} + +void ec_osal_thread_delete(ec_osal_thread_t thread) +{ + vTaskDelete(thread); +} + +void ec_osal_thread_suspend(ec_osal_thread_t thread) +{ + vTaskSuspend((TaskHandle_t)thread); +} + +void ec_osal_thread_resume(ec_osal_thread_t thread) +{ + vTaskResume((TaskHandle_t)thread); +} + +ec_osal_sem_t ec_osal_sem_create(uint32_t max_count, uint32_t initial_count) +{ + ec_osal_sem_t sem = (ec_osal_sem_t)xSemaphoreCreateCounting(max_count, initial_count); + if (sem == NULL) { + EC_LOG_ERR("Create semaphore failed\r\n"); + while (1) { + } + } + return sem; +} + +void ec_osal_sem_delete(ec_osal_sem_t sem) +{ + vSemaphoreDelete((SemaphoreHandle_t)sem); +} + +int ec_osal_sem_take(ec_osal_sem_t sem, uint32_t timeout) +{ + if (timeout == EC_OSAL_WAITING_FOREVER) { + return (xSemaphoreTake((SemaphoreHandle_t)sem, portMAX_DELAY) == pdPASS) ? 0 : -EC_ERR_TIMEOUT; + } else { + return (xSemaphoreTake((SemaphoreHandle_t)sem, pdMS_TO_TICKS(timeout)) == pdPASS) ? 0 : -EC_ERR_TIMEOUT; + } +} + +int ec_osal_sem_give(ec_osal_sem_t sem) +{ + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + int ret; + + if (xPortIsInsideInterrupt()) { + ret = xSemaphoreGiveFromISR((SemaphoreHandle_t)sem, &xHigherPriorityTaskWoken); + if (ret == pdPASS) { + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); + } + } else { + ret = xSemaphoreGive((SemaphoreHandle_t)sem); + } + + return (ret == pdPASS) ? 0 : -EC_ERR_TIMEOUT; +} + +void ec_osal_sem_reset(ec_osal_sem_t sem) +{ + xQueueReset((QueueHandle_t)sem); +} + +ec_osal_mutex_t ec_osal_mutex_create(void) +{ + ec_osal_mutex_t mutex = (ec_osal_mutex_t)xSemaphoreCreateMutex(); + if (mutex == NULL) { + EC_LOG_ERR("Create mutex failed\r\n"); + while (1) { + } + } + return mutex; +} + +void ec_osal_mutex_delete(ec_osal_mutex_t mutex) +{ + vSemaphoreDelete((SemaphoreHandle_t)mutex); +} + +int ec_osal_mutex_take(ec_osal_mutex_t mutex) +{ + return (xSemaphoreTake((SemaphoreHandle_t)mutex, portMAX_DELAY) == pdPASS) ? 0 : -EC_ERR_TIMEOUT; +} + +int ec_osal_mutex_give(ec_osal_mutex_t mutex) +{ + return (xSemaphoreGive((SemaphoreHandle_t)mutex) == pdPASS) ? 0 : -EC_ERR_TIMEOUT; +} + +static void __ec_timeout(TimerHandle_t *handle) +{ + struct ec_osal_timer *timer = (struct ec_osal_timer *)pvTimerGetTimerID((TimerHandle_t)handle); + + timer->handler(timer->argument); +} + +struct ec_osal_timer *ec_osal_timer_create(const char *name, uint32_t timeout_ms, ec_timer_handler_t handler, void *argument, bool is_period) +{ + struct ec_osal_timer *timer; + (void)name; + + timer = pvPortMalloc(sizeof(struct ec_osal_timer)); + + if (timer == NULL) { + EC_LOG_ERR("Create ec_osal_timer failed\r\n"); + while (1) { + } + } + memset(timer, 0, sizeof(struct ec_osal_timer)); + + timer->handler = handler; + timer->argument = argument; + + timer->timer = (void *)xTimerCreate("ec_tim", pdMS_TO_TICKS(timeout_ms), is_period, timer, (TimerCallbackFunction_t)__ec_timeout); + if (timer->timer == NULL) { + EC_LOG_ERR("Create timer failed\r\n"); + while (1) { + } + } + return timer; +} + +void ec_osal_timer_delete(struct ec_osal_timer *timer) +{ + xTimerStop(timer->timer, 0); + xTimerDelete(timer->timer, 0); + vPortFree(timer); +} + +void ec_osal_timer_start(struct ec_osal_timer *timer) +{ + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + int ret; + + if (xPortIsInsideInterrupt()) { + ret = xTimerStartFromISR(timer->timer, &xHigherPriorityTaskWoken); + if (ret == pdPASS) { + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); + } + } else { + xTimerStart(timer->timer, 0); + } +} + +void ec_osal_timer_stop(struct ec_osal_timer *timer) +{ + xTimerStop(timer->timer, 0); +} + +size_t ec_osal_enter_critical_section(void) +{ + size_t ret; + + if (xPortIsInsideInterrupt()) { + ret = taskENTER_CRITICAL_FROM_ISR(); + } else { + taskENTER_CRITICAL(); + ret = 1; + } + + return ret; +} + +void ec_osal_leave_critical_section(size_t flag) +{ + if (xPortIsInsideInterrupt()) { + taskEXIT_CRITICAL_FROM_ISR(flag); + } else { + taskEXIT_CRITICAL(); + } +} + +void ec_osal_msleep(uint32_t delay) +{ + vTaskDelay(pdMS_TO_TICKS(delay)); +} + +void *ec_osal_malloc(size_t size) +{ + return pvPortMalloc(size); +} + +void ec_osal_free(void *ptr) +{ + vPortFree(ptr); +} \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/osal/ec_osal_rtthread.c b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/osal/ec_osal_rtthread.c new file mode 100644 index 00000000..74788d79 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/osal/ec_osal_rtthread.c @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "ec_master.h" +#include +#include + +ec_osal_thread_t ec_osal_thread_create(const char *name, uint32_t stack_size, uint32_t prio, ec_thread_entry_t entry, void *args) +{ + rt_thread_t htask; + htask = rt_thread_create(name, entry, args, stack_size, prio, 10); + if (htask == NULL) { + EC_LOG_ERR("Create thread %s failed\r\n", name); + while (1) { + } + } + rt_thread_startup(htask); + return (ec_osal_thread_t)htask; +} + +void ec_osal_thread_delete(ec_osal_thread_t thread) +{ + if (thread == NULL) { + rt_thread_t self = rt_thread_self(); + rt_thread_control(self, RT_THREAD_CTRL_CLOSE, RT_NULL); + return; + } + + rt_thread_delete(thread); +} + +void ec_osal_thread_suspend(ec_osal_thread_t thread) +{ + rt_thread_suspend((rt_thread_t)thread); +} + +void ec_osal_thread_resume(ec_osal_thread_t thread) +{ + rt_thread_resume((rt_thread_t)thread); +} + +ec_osal_sem_t ec_osal_sem_create(uint32_t max_count, uint32_t initial_count) +{ + ec_osal_sem_t sem = (ec_osal_sem_t)rt_sem_create("ec_sem", initial_count, RT_IPC_FLAG_FIFO); + if (sem == NULL) { + EC_LOG_ERR("Create semaphore failed\r\n"); + while (1) { + } + } + return sem; +} + +void ec_osal_sem_delete(ec_osal_sem_t sem) +{ + rt_sem_delete((rt_sem_t)sem); +} + +int ec_osal_sem_take(ec_osal_sem_t sem, uint32_t timeout) +{ + int ret = 0; + rt_err_t result = RT_EOK; + + if (timeout == EC_OSAL_WAITING_FOREVER) { + result = rt_sem_take((rt_sem_t)sem, RT_WAITING_FOREVER); + } else { + result = rt_sem_take((rt_sem_t)sem, rt_tick_from_millisecond(timeout)); + } + if (result == -RT_ETIMEOUT) { + ret = -EC_ERR_TIMEOUT; + } else if (result == -RT_ERROR) { + ret = -EC_ERR_INVAL; + } else { + ret = 0; + } + + return (int)ret; +} + +int ec_osal_sem_give(ec_osal_sem_t sem) +{ + return (int)rt_sem_release((rt_sem_t)sem); +} + +void ec_osal_sem_reset(ec_osal_sem_t sem) +{ + rt_sem_control((rt_sem_t)sem, RT_IPC_CMD_RESET, (void *)0); +} + +ec_osal_mutex_t ec_osal_mutex_create(void) +{ + ec_osal_mutex_t mutex = (ec_osal_mutex_t)rt_mutex_create("ec_mutex", RT_IPC_FLAG_FIFO); + if (mutex == NULL) { + EC_LOG_ERR("Create mutex failed\r\n"); + while (1) { + } + } + return mutex; +} + +void ec_osal_mutex_delete(ec_osal_mutex_t mutex) +{ + rt_mutex_delete((rt_mutex_t)mutex); +} + +int ec_osal_mutex_take(ec_osal_mutex_t mutex) +{ + return (int)rt_mutex_take((rt_mutex_t)mutex, RT_WAITING_FOREVER); +} + +int ec_osal_mutex_give(ec_osal_mutex_t mutex) +{ + return (int)rt_mutex_release((rt_mutex_t)mutex); +} + +struct ec_osal_timer *ec_osal_timer_create(const char *name, uint32_t timeout_ms, ec_timer_handler_t handler, void *argument, bool is_period) +{ + struct ec_osal_timer *timer; + + timer = rt_malloc(sizeof(struct ec_osal_timer)); + if (timer == NULL) { + EC_LOG_ERR("Create ec_osal_timer failed\r\n"); + while (1) { + } + } + memset(timer, 0, sizeof(struct ec_osal_timer)); + + timer->timer = (void *)rt_timer_create(name, handler, argument, timeout_ms, is_period ? (RT_TIMER_FLAG_PERIODIC | RT_TIMER_FLAG_SOFT_TIMER) : (RT_TIMER_FLAG_ONE_SHOT | RT_TIMER_FLAG_SOFT_TIMER)); + if (timer->timer == NULL) { + EC_LOG_ERR("Create timer failed\r\n"); + while (1) { + } + } + return timer; +} + +void ec_osal_timer_delete(struct ec_osal_timer *timer) +{ + rt_timer_stop(timer->timer); + rt_timer_delete(timer->timer); + rt_free(timer); +} + +void ec_osal_timer_start(struct ec_osal_timer *timer) +{ + rt_timer_start(timer->timer); +} + +void ec_osal_timer_stop(struct ec_osal_timer *timer) +{ + rt_timer_stop(timer->timer); +} + +size_t ec_osal_enter_critical_section(void) +{ + return rt_hw_interrupt_disable(); +} + +void ec_osal_leave_critical_section(size_t flag) +{ + rt_hw_interrupt_enable(flag); +} + +void ec_osal_msleep(uint32_t delay) +{ + rt_thread_mdelay(delay); +} + +void *ec_osal_malloc(size_t size) +{ + return rt_malloc(size); +} + +void ec_osal_free(void *ptr) +{ + rt_free(ptr); +} diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/osal/ec_osal_threadx.c b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/osal/ec_osal_threadx.c new file mode 100644 index 00000000..a45671a4 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/osal/ec_osal_threadx.c @@ -0,0 +1,267 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "ec_master.h" +#include "tx_api.h" + +/* create bytepool in tx_application_define + * + * tx_byte_pool_create(&ec_byte_pool, "ec byte pool", memory_area, 65536); + */ + +extern TX_BYTE_POOL ec_byte_pool; + +ec_osal_thread_t ec_osal_thread_create(const char *name, uint32_t stack_size, uint32_t prio, ec_thread_entry_t entry, void *args) +{ + CHAR *pointer = TX_NULL; + TX_THREAD *thread_ptr = TX_NULL; + + tx_byte_allocate(&ec_byte_pool, (VOID **)&thread_ptr, sizeof(TX_THREAD), TX_NO_WAIT); + + if (thread_ptr == TX_NULL) { + EC_LOG_ERR("Create thread %s failed\r\n", name); + while (1) { + } + } + + tx_byte_allocate(&ec_byte_pool, (VOID **)&pointer, stack_size, TX_NO_WAIT); + if (pointer == TX_NULL) { + EC_LOG_ERR("Create thread %s failed\r\n", name); + while (1) { + } + } + + tx_thread_create(thread_ptr, (CHAR *)name, (VOID(*)(ULONG))entry, (uintptr_t)args, + pointer, stack_size, + prio, prio, TX_NO_TIME_SLICE, TX_AUTO_START); + + return (ec_osal_thread_t)thread_ptr; +} + +void ec_osal_thread_delete(ec_osal_thread_t thread) +{ + TX_THREAD *thread_ptr = NULL; + + if (thread == NULL) { + /* Call the tx_thread_identify to get the control block pointer of the + currently executing thread. */ + thread_ptr = tx_thread_identify(); + + /* Check if the current running thread pointer is not NULL */ + if (thread_ptr != NULL) { + /* Call the tx_thread_terminate to terminates the specified application + thread regardless of whether the thread is suspended or not. A thread + may call this service to terminate itself. */ + tx_thread_terminate(thread_ptr); + tx_byte_release(thread_ptr->tx_thread_stack_start); + tx_byte_release(thread_ptr); + } + return; + } + + tx_thread_terminate(thread); + tx_byte_release(thread_ptr->tx_thread_stack_start); + tx_byte_release(thread); +} + +void ec_osal_thread_suspend(ec_osal_thread_t thread) +{ + tx_thread_suspend((TX_THREAD *)thread); +} + +void ec_osal_thread_resume(ec_osal_thread_t thread) +{ + tx_thread_resume((TX_THREAD *)thread); +} + +ec_osal_sem_t ec_osal_sem_create(uint32_t max_count, uint32_t initial_count) +{ + TX_SEMAPHORE *sem_ptr = TX_NULL; + + tx_byte_allocate(&ec_byte_pool, (VOID **)&sem_ptr, sizeof(TX_SEMAPHORE), TX_NO_WAIT); + + if (sem_ptr == TX_NULL) { + EC_LOG_ERR("Create semaphore failed\r\n"); + while (1) { + } + } + + tx_semaphore_create(sem_ptr, "ec_sem", initial_count); + return (ec_osal_sem_t)sem_ptr; +} + +void ec_osal_sem_delete(ec_osal_sem_t sem) +{ + tx_semaphore_delete((TX_SEMAPHORE *)sem); + tx_byte_release(sem); +} + +int ec_osal_sem_take(ec_osal_sem_t sem, uint32_t timeout) +{ + int ret = 0; + + ret = tx_semaphore_get((TX_SEMAPHORE *)sem, timeout); + if (ret == TX_SUCCESS) { + ret = 0; + } else if ((ret == TX_WAIT_ABORTED) || (ret == TX_NO_INSTANCE)) { + ret = -EC_ERR_TIMEOUT; + } else { + ret = -EC_ERR_INVAL; + } + + return (int)ret; +} + +int ec_osal_sem_give(ec_osal_sem_t sem) +{ + return (int)tx_semaphore_put((TX_SEMAPHORE *)sem); +} + +void ec_osal_sem_reset(ec_osal_sem_t sem) +{ + tx_semaphore_get((TX_SEMAPHORE *)sem, 0); +} + +ec_osal_mutex_t ec_osal_mutex_create(void) +{ + TX_MUTEX *mutex_ptr = TX_NULL; + + tx_byte_allocate(&ec_byte_pool, (VOID **)&mutex_ptr, sizeof(TX_MUTEX), TX_NO_WAIT); + + if (mutex_ptr == TX_NULL) { + EC_LOG_ERR("Create mutex failed\r\n"); + while (1) { + } + } + + tx_mutex_create(mutex_ptr, "ec_mutx", TX_INHERIT); + return (ec_osal_mutex_t)mutex_ptr; +} + +void ec_osal_mutex_delete(ec_osal_mutex_t mutex) +{ + tx_mutex_delete((TX_MUTEX *)mutex); + tx_byte_release(mutex); +} + +int ec_osal_mutex_take(ec_osal_mutex_t mutex) +{ + int ret = 0; + + ret = tx_mutex_get((TX_MUTEX *)mutex, TX_WAIT_FOREVER); + if (ret == TX_SUCCESS) { + ret = 0; + } else if ((ret == TX_WAIT_ABORTED) || (ret == TX_NO_INSTANCE)) { + ret = -EC_ERR_TIMEOUT; + } else { + ret = -EC_ERR_INVAL; + } + + return (int)ret; +} + +int ec_osal_mutex_give(ec_osal_mutex_t mutex) +{ + return (int)(tx_mutex_put((TX_MUTEX *)mutex) == TX_SUCCESS) ? 0 : -EC_ERR_INVAL; +} + +struct ec_osal_timer *ec_osal_timer_create(const char *name, uint32_t timeout_ms, ec_timer_handler_t handler, void *argument, bool is_period) +{ + TX_TIMER *timer_ptr = TX_NULL; + struct ec_osal_timer *timer; + + tx_byte_allocate(&ec_byte_pool, (VOID **)&timer, sizeof(struct ec_osal_timer), TX_NO_WAIT); + + if (timer == TX_NULL) { + EC_LOG_ERR("Create ec_osal_timer failed\r\n"); + while (1) { + } + } + memset(timer, 0, sizeof(struct ec_osal_timer)); + + tx_byte_allocate(&ec_byte_pool, (VOID **)&timer_ptr, sizeof(TX_TIMER), TX_NO_WAIT); + + if (timer_ptr == TX_NULL) { + EC_LOG_ERR("Create TX_TIMER failed\r\n"); + while (1) { + } + } + + timer->timer = timer_ptr; + timer->timeout_ms = timeout_ms; + timer->is_period = is_period; + if (tx_timer_create(timer_ptr, (CHAR *)name, (void (*)(ULONG))handler, (uintptr_t)argument, 1, is_period ? 1 : 0, + TX_NO_ACTIVATE) != TX_SUCCESS) { + return NULL; + } + return timer; +} + +void ec_osal_timer_delete(struct ec_osal_timer *timer) +{ + tx_timer_deactivate((TX_TIMER *)timer->timer); + tx_timer_delete((TX_TIMER *)timer->timer); + tx_byte_release(timer->timer); + tx_byte_release(timer); +} + +void ec_osal_timer_start(struct ec_osal_timer *timer) +{ + if (tx_timer_change((TX_TIMER *)timer->timer, timer->timeout_ms, timer->is_period ? timer->timeout_ms : 0) == TX_SUCCESS) { + /* Call the tx_timer_activate to activates the specified application + timer. The expiration routines of timers that expire at the same + time are executed in the order they were activated. */ + if (tx_timer_activate((TX_TIMER *)timer->timer) == TX_SUCCESS) { + /* Return osOK for success */ + } else { + /* Return osErrorResource in case of error */ + } + } else { + } +} + +void ec_osal_timer_stop(struct ec_osal_timer *timer) +{ + tx_timer_deactivate((TX_TIMER *)timer->timer); +} + +size_t ec_osal_enter_critical_section(void) +{ + TX_INTERRUPT_SAVE_AREA + + TX_DISABLE + + return interrupt_save; +} + +void ec_osal_leave_critical_section(size_t flag) +{ + int interrupt_save; + + interrupt_save = flag; + TX_RESTORE +} + +void ec_osal_msleep(uint32_t delay) +{ +#if TX_TIMER_TICKS_PER_SECOND != 1000 +#error "TX_TIMER_TICKS_PER_SECOND must be 1000" +#endif + tx_thread_sleep(delay); +} + +void *ec_osal_malloc(size_t size) +{ + CHAR *pointer = TX_NULL; + + tx_byte_allocate(&ec_byte_pool, (VOID **)&pointer, size, TX_WAIT_FOREVER); + + return pointer; +} + +void ec_osal_free(void *ptr) +{ + tx_byte_release(ptr); +} \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/port/netdev_hpmicro.c b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/port/netdev_hpmicro.c new file mode 100644 index 00000000..93726b5e --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/port/netdev_hpmicro.c @@ -0,0 +1,464 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "hpm_clock_drv.h" +#include "hpm_enet_drv.h" +#include "hpm_enet_phy_common.h" +#include "hpm_otp_drv.h" +#include "hpm_l1c_drv.h" +#include "board.h" +#include "ec_master.h" + +#if defined(RGMII) && RGMII +#define ENET_INF_TYPE enet_inf_rgmii +#define ENET BOARD_ENET_RGMII +#else +#define ENET_INF_TYPE enet_inf_rmii +#define ENET BOARD_ENET_RMII +#endif + +#define __ENABLE_ENET_RECEIVE_INTERRUPT 1 + +#define MAC_ADDR0 0x00 +#define MAC_ADDR1 0x80 +#define MAC_ADDR2 0xE1 +#define MAC_ADDR3 0x00 +#define MAC_ADDR4 0x00 +#define MAC_ADDR5 0x00 + +#define ENET_TX_BUFF_COUNT CONFIG_EC_MAX_ENET_TXBUF_COUNT +#define ENET_RX_BUFF_COUNT CONFIG_EC_MAX_ENET_RXBUF_COUNT +#define ENET_RX_BUFF_SIZE ENET_MAX_FRAME_SIZE +#define ENET_TX_BUFF_SIZE ENET_MAX_FRAME_SIZE + +ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(ENET_SOC_DESC_ADDR_ALIGNMENT) +__RW enet_rx_desc_t dma_rx_desc_tab[ENET_RX_BUFF_COUNT]; /* Ethernet Rx DMA Descriptor */ + +ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(ENET_SOC_DESC_ADDR_ALIGNMENT) +__RW enet_tx_desc_t dma_tx_desc_tab[ENET_TX_BUFF_COUNT]; /* Ethernet Tx DMA Descriptor */ + +ATTR_PLACE_AT_FAST_RAM_BSS_WITH_ALIGNMENT(ENET_SOC_BUFF_ADDR_ALIGNMENT) +__RW uint8_t rx_buff[ENET_RX_BUFF_COUNT][ENET_RX_BUFF_SIZE]; /* Ethernet Receive Buffer */ + +ATTR_PLACE_AT_FAST_RAM_BSS_WITH_ALIGNMENT(ENET_SOC_BUFF_ADDR_ALIGNMENT) +__RW uint8_t tx_buff[ENET_TX_BUFF_COUNT][ENET_TX_BUFF_SIZE]; /* Ethernet Transmit Buffer */ + +enet_desc_t desc; +uint8_t mac[ENET_MAC]; + +ec_netdev_t g_netdev; + +ATTR_WEAK void enet_get_mac_address(uint8_t *mac) +{ + bool invalid = true; + + uint32_t uuid[(ENET_MAC + (ENET_MAC - 1)) / sizeof(uint32_t)]; + + for (int i = 0; i < ARRAY_SIZE(uuid); i++) { + uuid[i] = otp_read_from_shadow(OTP_SOC_UUID_IDX + i); + if (uuid[i] != 0xFFFFFFFFUL && uuid[i] != 0) { + invalid = false; + } + } + + if (invalid == true) { + ec_memcpy(mac, &uuid, ENET_MAC); + } else { + mac[0] = MAC_ADDR0; + mac[1] = MAC_ADDR1; + mac[2] = MAC_ADDR2; + mac[3] = MAC_ADDR3; + mac[4] = MAC_ADDR4; + mac[5] = MAC_ADDR5; + } +} + +hpm_stat_t enet_init(ENET_Type *ptr) +{ + enet_int_config_t int_config = { .int_enable = 0, .int_mask = 0 }; + enet_mac_config_t enet_config; + enet_tx_control_config_t enet_tx_control_config; + +#ifdef CONFIG_EC_PHY_CUSTOM +#if defined(RGMII) && RGMII +#if defined(__USE_DP83867) && __USE_DP83867 + dp83867_config_t phy_config; +#else + rtl8211_config_t phy_config; +#endif +#else +#if defined(__USE_DP83848) && __USE_DP83848 + dp83848_config_t phy_config; +#else + rtl8201_config_t phy_config; +#endif +#endif +#endif + + /* Initialize td, rd and the corresponding buffers */ + memset((uint8_t *)dma_tx_desc_tab, 0x00, sizeof(dma_tx_desc_tab)); + memset((uint8_t *)dma_rx_desc_tab, 0x00, sizeof(dma_rx_desc_tab)); + memset((uint8_t *)rx_buff, 0x00, sizeof(rx_buff)); + memset((uint8_t *)tx_buff, 0x00, sizeof(tx_buff)); + + desc.tx_desc_list_head = (enet_tx_desc_t *)core_local_mem_to_sys_address(BOARD_RUNNING_CORE, (uint32_t)dma_tx_desc_tab); + desc.rx_desc_list_head = (enet_rx_desc_t *)core_local_mem_to_sys_address(BOARD_RUNNING_CORE, (uint32_t)dma_rx_desc_tab); + + desc.tx_buff_cfg.buffer = core_local_mem_to_sys_address(BOARD_RUNNING_CORE, (uint32_t)tx_buff); + desc.tx_buff_cfg.count = ENET_TX_BUFF_COUNT; + desc.tx_buff_cfg.size = ENET_TX_BUFF_SIZE; + + desc.rx_buff_cfg.buffer = core_local_mem_to_sys_address(BOARD_RUNNING_CORE, (uint32_t)rx_buff); + desc.rx_buff_cfg.count = ENET_RX_BUFF_COUNT; + desc.rx_buff_cfg.size = ENET_RX_BUFF_SIZE; + + /*Get a default control config for tx descriptor */ + enet_get_default_tx_control_config(ENET, &enet_tx_control_config); + + /* Set the control config for tx descriptor */ + ec_memcpy(&desc.tx_control_config, &enet_tx_control_config, sizeof(enet_tx_control_config_t)); + + /* Get MAC address */ + enet_get_mac_address(mac); + + /* Set MAC0 address */ + enet_config.mac_addr_high[0] = mac[5] << 8 | mac[4]; + enet_config.mac_addr_low[0] = mac[3] << 24 | mac[2] << 16 | mac[1] << 8 | mac[0]; + enet_config.valid_max_count = 1; + + /* Set DMA PBL */ + enet_config.dma_pbl = board_get_enet_dma_pbl(ENET); + + /* Set SARC */ + enet_config.sarc = enet_sarc_replace_mac0; + +#if defined(__ENABLE_ENET_RECEIVE_INTERRUPT) && __ENABLE_ENET_RECEIVE_INTERRUPT + /* Enable Enet IRQ */ + board_enable_enet_irq(ENET); + + /* Get the default interrupt config */ + enet_get_default_interrupt_config(ENET, &int_config); +#endif + + /* Initialize enet controller */ + if (enet_controller_init(ptr, ENET_INF_TYPE, &desc, &enet_config, &int_config) != status_success) { + return status_fail; + } + +#if defined(__ENABLE_ENET_RECEIVE_INTERRUPT) && __ENABLE_ENET_RECEIVE_INTERRUPT + /* Disable LPI interrupt */ + enet_disable_lpi_interrupt(ENET); +#endif + +#ifdef CONFIG_EC_PHY_CUSTOM +/* Initialize phy */ +#if defined(RGMII) && RGMII +#if defined(__USE_DP83867) && __USE_DP83867 + dp83867_reset(ptr); +#if defined(__DISABLE_AUTO_NEGO) && __DISABLE_AUTO_NEGO + dp83867_set_mdi_crossover_mode(ENET, enet_phy_mdi_crossover_manual_mdix); +#endif + dp83867_basic_mode_default_config(ptr, &phy_config); + if (dp83867_basic_mode_init(ptr, &phy_config) == true) { +#else + rtl8211_reset(ptr); + rtl8211_basic_mode_default_config(ptr, &phy_config); + if (rtl8211_basic_mode_init(ptr, &phy_config) == true) { +#endif +#else +#if defined(__USE_DP83848) && __USE_DP83848 + dp83848_reset(ptr); + dp83848_basic_mode_default_config(ptr, &phy_config); + if (dp83848_basic_mode_init(ptr, &phy_config) == true) { +#else + rtl8201_reset(ptr); + rtl8201_basic_mode_default_config(ptr, &phy_config); + if (rtl8201_basic_mode_init(ptr, &phy_config) == true) { +#endif +#endif + EC_LOG_DBG("Enet phy init passed !\n"); + } else { + EC_LOG_DBG("Enet phy init failed !\n"); + return status_fail; + } +#endif + return status_success; +} + +ec_netdev_t *ec_netdev_low_level_init(uint8_t netdev_index) +{ + /* Initialize GPIOs */ + board_init_enet_pins(ENET); + + /* Reset an enet PHY */ + board_reset_enet_phy(ENET); +#if defined(RGMII) && RGMII + /* Set RGMII clock delay */ + board_init_enet_rgmii_clock_delay(ENET); +#else + /* Set RMII reference clock */ + board_init_enet_rmii_reference_clock(ENET, BOARD_ENET_RMII_INT_REF_CLK); + EC_LOG_DBG("Reference Clock: %s\n", BOARD_ENET_RMII_INT_REF_CLK ? "Internal Clock" : "External Clock"); +#endif + + /* Initialize MAC and DMA */ + if (enet_init(ENET) == 0) { + } else { + EC_LOG_DBG("Enet initialization fails !!!\n"); + while (1) { + } + } + + ec_memcpy(g_netdev.mac_addr, mac, ENET_MAC); + + for (uint32_t i = 0; i < ENET_TX_BUFF_COUNT; i++) { + for (uint8_t j = 0; j < 6; j++) { // dst MAC + EC_WRITE_U8(&tx_buff[i][j], 0xFF); + } + for (uint8_t j = 0; j < 6; j++) { // src MAC + EC_WRITE_U8(&tx_buff[i][6 + j], mac[j]); + } + EC_WRITE_U16(&tx_buff[i][12], ec_htons(0x88a4)); + } + + return &g_netdev; +} + +#ifndef CONFIG_EC_PHY_CUSTOM +void ec_mdio_low_level_write(struct chry_phy_device *phydev, uint16_t phy_addr, uint16_t regnum, uint16_t val) +{ + //ec_netdev_t *netdev = (ec_netdev_t *)phydev->user_data; + enet_write_phy(ENET, phy_addr, regnum, val); +} + +uint16_t ec_mdio_low_level_read(struct chry_phy_device *phydev, uint16_t phy_addr, uint16_t regnum) +{ + //ec_netdev_t *netdev = (ec_netdev_t *)phydev->user_data; + return enet_read_phy(ENET, phy_addr, regnum); +} + +void ec_netdev_low_level_link_up(ec_netdev_t *netdev, struct chry_phy_status *status) +{ + enet_line_speed_t line_speed = enet_line_speed_10mbps; + + switch (status->speed) { + case 10: + line_speed = enet_line_speed_10mbps; + break; + case 100: + line_speed = enet_line_speed_100mbps; + break; + case 1000: + line_speed = enet_line_speed_1000mbps; + break; + + default: + break; + } + if (status->link) { + enet_set_line_speed(ENET, line_speed); + enet_set_duplex_mode(ENET, status->duplex); + } else { + } +} +#else +void ec_netdev_low_level_poll_link_state(ec_netdev_t *netdev) +{ + static enet_phy_status_t last_status; + enet_phy_status_t status = { 0 }; + + enet_line_speed_t line_speed[] = { enet_line_speed_10mbps, enet_line_speed_100mbps, enet_line_speed_1000mbps }; + +#if defined(RGMII) && RGMII +#if defined(__USE_DP83867) && __USE_DP83867 + dp83867_get_phy_status(ENET, &status); +#else + rtl8211_get_phy_status(ENET, &status); +#endif +#else +#if defined(__USE_DP83848) && __USE_DP83848 + dp83848_get_phy_status(ENET, &status); +#else + rtl8201_get_phy_status(ENET, &status); +#endif +#endif + + if (memcmp(&last_status, &status, sizeof(enet_phy_status_t)) != 0) { + ec_memcpy(&last_status, &status, sizeof(enet_phy_status_t)); + if (status.enet_phy_link) { + enet_set_line_speed(ENET, line_speed[status.enet_phy_speed]); + enet_set_duplex_mode(ENET, status.enet_phy_duplex); + netdev->link_state = true; + } else { + netdev->link_state = false; + } + } +} +#endif + +EC_FAST_CODE_SECTION uint8_t *ec_netdev_low_level_get_txbuf(ec_netdev_t *netdev) +{ + return (uint8_t *)tx_buff[netdev->tx_frame_index]; +} + +EC_FAST_CODE_SECTION int ec_netdev_low_level_output(ec_netdev_t *netdev, uint32_t size) +{ + __IO enet_tx_desc_t *dma_tx_desc; + + dma_tx_desc = desc.tx_desc_list_cur; + if (dma_tx_desc->tdes0_bm.own != 0) { + return -1; + } + + netdev->tx_frame_index++; + netdev->tx_frame_index %= ENET_TX_BUFF_COUNT; + + /* Prepare transmit descriptors to give to DMA*/ + enet_prepare_transmission_descriptors(ENET, &desc.tx_desc_list_cur, size + 4, desc.tx_buff_cfg.size); + + return 0; +} + +EC_FAST_CODE_SECTION int ec_netdev_low_level_input(ec_netdev_t *netdev) +{ + uint32_t len; + uint8_t *buffer; + enet_frame_t frame = { 0, 0, 0 }; + enet_rx_desc_t *dma_rx_desc; + uint32_t i = 0; + int ret = 0; + + /* Check and get a received frame */ + if (enet_check_received_frame(&desc.rx_desc_list_cur, &desc.rx_frame_info) == 1) { + frame = enet_get_received_frame(&desc.rx_desc_list_cur, &desc.rx_frame_info); + } + + /* Obtain the size of the packet and put it into the "len" variable. */ + len = frame.length; + buffer = (uint8_t *)sys_address_to_core_local_mem(BOARD_RUNNING_CORE, (uint32_t)frame.buffer); + + if (len > 0) { + ec_netdev_receive(netdev, buffer, len); + /* Release descriptors to DMA */ + dma_rx_desc = frame.rx_desc; + + /* Set Own bit in Rx descriptors: gives the buffers back to DMA */ + for (i = 0; i < desc.rx_frame_info.seg_count; i++) { + dma_rx_desc->rdes0_bm.own = 1; + dma_rx_desc = (enet_rx_desc_t *)(dma_rx_desc->rdes3_bm.next_desc); + } + + /* Clear Segment_Count */ + desc.rx_frame_info.seg_count = 0; + } else { + ret = -1; + } + + /* Resume Rx Process */ + enet_rx_resume(ENET); + return ret; +} + +#if defined(__ENABLE_ENET_RECEIVE_INTERRUPT) && __ENABLE_ENET_RECEIVE_INTERRUPT +void isr_enet(ENET_Type *ptr) +{ + uint32_t status; + uint32_t rxgbfrmis; + uint32_t intr_status; + + status = ptr->DMA_STATUS; + rxgbfrmis = ptr->MMC_INTR_RX; + intr_status = ptr->INTR_STATUS; + + if (ENET_DMA_STATUS_GLPII_GET(status)) { + /* read LPI_CSR to clear interrupt status */ + ptr->LPI_CSR; + } + + if (ENET_INTR_STATUS_RGSMIIIS_GET(intr_status)) { + /* read XMII_CSR to clear interrupt status */ + ptr->XMII_CSR; + } + + if (ENET_DMA_STATUS_RI_GET(status)) { + ptr->DMA_STATUS |= ENET_DMA_STATUS_RI_MASK; + while (ec_netdev_low_level_input(&g_netdev) == 0) { + } + } + + if (ENET_MMC_INTR_RX_RXCTRLFIS_GET(rxgbfrmis)) { + ptr->RXFRAMECOUNT_GB; + } +} + +#ifdef HPM_ENET0_BASE +void isr_enet0(void) +{ + isr_enet(ENET); +} +SDK_DECLARE_EXT_ISR_M(IRQn_ENET0, isr_enet0) +#endif + +#ifdef HPM_ENET1_BASE +void isr_enet1(void) +{ + isr_enet(ENET); +} +SDK_DECLARE_EXT_ISR_M(IRQn_ENET1, isr_enet1) +#endif + +#endif + +#include "hpm_gptmr_drv.h" + +#define EC_HTIMER BOARD_GPTMR +#define EC_HTIMER_CH BOARD_GPTMR_CHANNEL +#define EC_HTIMER_IRQ BOARD_GPTMR_IRQ +#define EC_HTIMER_CLK_NAME BOARD_GPTMR_CLK_NAME + +ec_htimer_cb g_ec_htimer_cb = NULL; +void *g_ec_htimer_arg = NULL; + +void ec_htimer_isr(void) +{ + if (gptmr_check_status(EC_HTIMER, GPTMR_CH_RLD_STAT_MASK(EC_HTIMER_CH))) { + gptmr_clear_status(EC_HTIMER, GPTMR_CH_RLD_STAT_MASK(EC_HTIMER_CH)); + g_ec_htimer_cb(g_ec_htimer_arg); + } +} +SDK_DECLARE_EXT_ISR_M(EC_HTIMER_IRQ, ec_htimer_isr); + +void ec_htimer_start(uint32_t us, ec_htimer_cb cb, void *arg) +{ + uint32_t gptmr_freq; + gptmr_channel_config_t config; + + g_ec_htimer_cb = cb; + g_ec_htimer_arg = arg; + + gptmr_channel_get_default_config(EC_HTIMER, &config); + + clock_add_to_group(EC_HTIMER_CLK_NAME, 0); + gptmr_freq = clock_get_frequency(EC_HTIMER_CLK_NAME); + + config.reload = gptmr_freq / 1000000 * us; + gptmr_stop_counter(EC_HTIMER, EC_HTIMER_CH); + gptmr_channel_config(EC_HTIMER, EC_HTIMER_CH, &config, false); + gptmr_enable_irq(EC_HTIMER, GPTMR_CH_RLD_IRQ_MASK(EC_HTIMER_CH)); + intc_m_enable_irq_with_priority(EC_HTIMER_IRQ, 10); + gptmr_start_counter(EC_HTIMER, EC_HTIMER_CH); +} + +void ec_htimer_stop(void) +{ + gptmr_stop_counter(EC_HTIMER, EC_HTIMER_CH); + gptmr_disable_irq(EC_HTIMER, GPTMR_CH_RLD_IRQ_MASK(EC_HTIMER_CH)); + intc_m_disable_irq(EC_HTIMER_IRQ); +} + +uint32_t ec_get_cpu_frequency(void) +{ + return clock_get_frequency(clock_cpu0); +} diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/port/netdev_renesas.c b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/port/netdev_renesas.c new file mode 100644 index 00000000..d5d4945a --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/port/netdev_renesas.c @@ -0,0 +1,304 @@ +/* + * Copyright (c) 2025, sakumisu + * Copyright (c) 2025, yans + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include "ec_master.h" + +ec_netdev_t g_netdev; + +#if defined(BSP_MCU_GROUP_RZT2M) || defined(BSP_MCU_GROUP_RZN2L) +#define ETHER_BUFFER_PLACE_IN_SECTION BSP_PLACE_IN_SECTION(".noncache_buffer.eth") +#else +#define ETHER_BUFFER_PLACE_IN_SECTION +#endif + +__attribute__((__aligned__(32))) uint8_t tx_buffer[CONFIG_EC_MAX_ENET_TXBUF_COUNT][1536] ETHER_BUFFER_PLACE_IN_SECTION; + +extern uint32_t SystemCoreClock; + +#define PING_PORT_COUNT (3) ///< Count of port + +static uint8_t g_link_change = 0; ///< Link change (bit0:port0, bit1:port1, bit2:port2) +static uint8_t g_link_status = 0; ///< Link status (bit0:port0, bit1:port1, bit2:port2) +static uint8_t previous_link_status = 0; + +static int phy_rtl8211f_led_fixup(ether_phy_instance_ctrl_t *phydev) +{ +#define RTL_8211F_PAGE_SELECT 0x1F +#define RTL_8211F_EEELCR_ADDR 0x11 +#define RTL_8211F_LED_PAGE 0xD04 +#define RTL_8211F_LCR_ADDR 0x10 + + uint32_t val1, val2 = 0; + + /* switch to led page */ + R_ETHER_PHY_Write(phydev, RTL_8211F_PAGE_SELECT, RTL_8211F_LED_PAGE); + + /* set led1(green) Link 10/100/1000M, and set led2(yellow) Link 10/100/1000M+Active */ + R_ETHER_PHY_Read(phydev, RTL_8211F_LCR_ADDR, &val1); + val1 |= (1 << 5); + val1 |= (1 << 8); + val1 &= (~(1 << 9)); + val1 |= (1 << 10); + val1 |= (1 << 11); + R_ETHER_PHY_Write(phydev, RTL_8211F_LCR_ADDR, val1); + + /* set led1(green) EEE LED function disabled so it can keep on when linked */ + R_ETHER_PHY_Read(phydev, RTL_8211F_EEELCR_ADDR, &val2); + val2 &= (~(1 << 2)); + R_ETHER_PHY_Write(phydev, RTL_8211F_EEELCR_ADDR, val2); + + /* switch back to page0 */ + R_ETHER_PHY_Write(phydev, RTL_8211F_PAGE_SELECT, 0xa42); + + return 0; +} + +void ether_phy_targets_initialize_rtl8211_rgmii(ether_phy_instance_ctrl_t *p_instance_ctrl) +{ + ec_osal_msleep(100); + phy_rtl8211f_led_fixup(p_instance_ctrl); +} + +ec_netdev_t *ec_netdev_low_level_init(uint8_t netdev_index) +{ + fsp_err_t res; + + EC_ASSERT_MSG(g_ether0_cfg.zerocopy == ETHER_ZEROCOPY_ENABLE, "zerocopy must be enabled"); + + res = R_GMAC_Open(&g_ether0_ctrl, &g_ether0_cfg); + if (res != FSP_SUCCESS) + EC_LOG_ERR("R_ETHER_Open failed!, res = %d", res); + + ec_memcpy(g_netdev.mac_addr, g_ether0_cfg.p_mac_address, 6); + + for (uint32_t i = 0; i < g_ether0_cfg.num_tx_descriptors; i++) { + for (uint8_t j = 0; j < 6; j++) { // dst MAC + EC_WRITE_U8(&tx_buffer[i][j], 0xFF); + } + for (uint8_t j = 0; j < 6; j++) { // src MAC + EC_WRITE_U8(&tx_buffer[i][6 + j], g_ether0_cfg.p_mac_address[j]); + } + EC_WRITE_U16(&tx_buffer[i][12], ec_htons(0x88a4)); + } + + return &g_netdev; +} + +void ec_netdev_low_level_poll_link_state(ec_netdev_t *netdev) +{ + fsp_err_t res; + gmac_link_status_t port_status; + uint8_t port = 0; + uint8_t port_bit = 0; + + res = R_GMAC_LinkProcess(&g_ether0_ctrl); + if (res != FSP_SUCCESS) + EC_LOG_ERR("R_ETHER_LinkProcess failed!, res = %d", res); + + if (0 == g_ether0.p_cfg->p_callback) { + for (port = 0; port < PING_PORT_COUNT; port++) { + res = R_GMAC_GetLinkStatus(&g_ether0_ctrl, port, &port_status); + if (FSP_SUCCESS != res) { + /* An error has occurred */ + EC_LOG_ERR("R_GMAC_GetLinkStatus failed!, res = %d", res); + break; + } + + if (GMAC_LINK_STATUS_DOWN != port_status) { + /* Set link up */ + g_link_status |= (uint8_t)(1U << port); + } + } + if (FSP_SUCCESS == res) { + /* Set changed link status */ + g_link_change = previous_link_status ^ g_link_status; + } + } + + previous_link_status = g_link_status; + + if (FSP_SUCCESS == res) { + for (port = 0; port < PING_PORT_COUNT; port++) { + port_bit = (uint8_t)(1U << port); + + if (g_link_change & port_bit) { + /* Link status changed */ + g_link_change &= (uint8_t)(~port_bit); // change bit clear + + if (g_link_status & port_bit) { + /* Changed to Link-up */ + netdev->link_state = true; + } else { + /* Changed to Link-down */ + netdev->link_state = false; + } + } + } + } +} + +EC_FAST_CODE_SECTION uint8_t *ec_netdev_low_level_get_txbuf(ec_netdev_t *netdev) +{ + return (uint8_t *)tx_buffer[netdev->tx_frame_index]; +} + +EC_FAST_CODE_SECTION int ec_netdev_low_level_output(ec_netdev_t *netdev, uint32_t size) +{ + fsp_err_t res; + + res = R_GMAC_Write(&g_ether0_ctrl, tx_buffer[netdev->tx_frame_index], size); + if (res != FSP_SUCCESS) { + return -1; + } + + netdev->tx_frame_index++; + netdev->tx_frame_index %= g_ether0_cfg.num_tx_descriptors; + + return 0; +} + +EC_FAST_CODE_SECTION int ec_netdev_low_level_input(ec_netdev_t *netdev) +{ + fsp_err_t res; + uint8_t *buffer; + uint32_t len = 0; + + res = R_GMAC_Read(&g_ether0_ctrl, (void *)&buffer, &len); + if (res != FSP_SUCCESS) { + return -1; + } + + ec_netdev_receive(netdev, buffer, len); + + R_GMAC_BufferRelease(&g_ether0_ctrl); + + return 0; +} + +static ec_htimer_cb g_ec_htimer_cb = NULL; +static void *g_ec_htimer_arg = NULL; + +void timer0_esc_callback(timer_callback_args_t *p_args) +{ + rt_interrupt_enter(); + if (TIMER_EVENT_CYCLE_END == p_args->event) { + if (g_ec_htimer_cb) { + g_ec_htimer_cb(g_ec_htimer_arg); + } + } + rt_interrupt_leave(); +} + +void ec_htimer_start(uint32_t us, ec_htimer_cb cb, void *arg) +{ + fsp_err_t fsp_err = FSP_SUCCESS; + uint32_t count = us * (SystemCoreClock / 1000000); // 400MHz, 1us = 400 ticks + + g_ec_htimer_cb = cb; + g_ec_htimer_arg = arg; + + fsp_err = R_GPT_Open(&g_timer0_ctrl, &g_timer0_cfg); + fsp_err |= R_GPT_CounterSet(&g_timer0_ctrl, 0); + fsp_err |= R_GPT_PeriodSet(&g_timer0_ctrl, count); + fsp_err |= R_GPT_Start(&g_timer0_ctrl); + + if (fsp_err != FSP_SUCCESS) { + EC_LOG_ERR("R_GPT_Open failed!, res = %d", fsp_err); + } +} + +void ec_htimer_stop(void) +{ + R_GPT_Stop(&g_timer0_ctrl); +} + +volatile uint64_t mtu3_overflow_count = 0; + +void g_mtu3_callback(timer_callback_args_t *p_args) +{ + rt_interrupt_enter(); + if (TIMER_EVENT_CYCLE_END == p_args->event) { + mtu3_overflow_count++; + } + rt_interrupt_leave(); +} + +uint64_t gpt_get_count(void) +{ + mtu3_status_t status; + uint64_t high; + uint64_t low; + + do { + high = mtu3_overflow_count; + R_MTU3_StatusGet(&g_mtu3_ctrl, &status); + low = status.counter; + } while (high != mtu3_overflow_count); + + return (high << 16) | low; +} + +void ec_timestamp_init(void) +{ + fsp_err_t fsp_err = FSP_SUCCESS; + + fsp_err = R_MTU3_Open(&g_mtu3_ctrl, &g_mtu3_cfg); + fsp_err |= R_MTU3_Start(&g_mtu3_ctrl); + + if (fsp_err != FSP_SUCCESS) { + EC_LOG_ERR("R_GPT_Open failed!, res = %d", fsp_err); + } +} + +EC_FAST_CODE_SECTION uint64_t ec_timestamp_get_time_ns(void) +{ + return (uint64_t)(gpt_get_count() * 5ULL); +} + +EC_FAST_CODE_SECTION uint64_t ec_timestamp_get_time_us(void) +{ + return ec_timestamp_get_time_ns() / 1000ULL; +} + +void user_ether0_callback(ether_callback_args_t *p_args) +{ + rt_interrupt_enter(); + + switch (p_args->event) { + case ETHER_EVENT_LINK_ON: ///< Link up detection event/ + g_link_status |= (uint8_t)p_args->status_link; ///< status up + g_link_change |= (uint8_t)p_args->status_link; ///< change bit set + break; + + case ETHER_EVENT_LINK_OFF: ///< Link down detection event + g_link_status &= (uint8_t)(~p_args->status_link); ///< status down + g_link_change |= (uint8_t)p_args->status_link; ///< change bit set + break; + + case ETHER_EVENT_WAKEON_LAN: ///< Magic packet detection event + /* If EDMAC FR (Frame Receive Event) or FDE (Receive Descriptor Empty Event) + * interrupt occurs, send rx mailbox. */ + case ETHER_EVENT_SBD_INTERRUPT: ///< BSD Interrupt event + { + while (ec_netdev_low_level_input(&g_netdev) == 0) { + } + break; + } + case ETHER_EVENT_PMT_INTERRUPT: ///< PMT Interrupt event + break; + + default: + break; + } + + rt_interrupt_leave(); +} + +uint32_t ec_get_cpu_frequency(void) +{ + return SystemCoreClock; +} diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/ECAT_CIA402_ENI.xml b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/ECAT_CIA402_ENI.xml new file mode 100644 index 00000000..b85a399e --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/ECAT_CIA402_ENI.xml @@ -0,0 +1,1094 @@ + + + + + + + 010105010000 + 2c58b9dca252 + a488 + + + 150994944 + 1 + + + + IP + true + + cycle + 7 + 0 + 304 + 0000 + 0 + + + IP + true + + cycle + 7 + 0 + 304 + 0000 + 0 + + + IP + true + + cycle + 8 + 0 + 512 + 0400 + 3 + + + IP + true + + cycle + 8 + 0 + 16 + 0000 + 3 + + + IP + true + + cycle + 8 + 0 + 768 + 0000000000000000 + 3 + + + IP + PI + BI + SI + OI + true + + cycle + 8 + 0 + 1536 + 256 + 3 + + + IP + true + + cycle + 8 + 0 + 2048 + 256 + 3 + + + IP + true + + cycle + 8 + 0 + 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424DD8020000000000003600000028000000100000000E0000000100180000000000A2020000120B0000120B000000000000000000001306E31306E3190CE42B1FE62B1FE61306E31F13E5190CE42519E51306E31306E3190CE42F24E7190CE41306E31306E31306E31306E35F56EC645CED645CED4137E91F13E5473DE95F57EC3227E71306E3473DE95A51EC271BE61306E31306E31409CA524CC68E8AD74F48C1615CC82218D03E36BF716BCE746FCE453DC01307CE3931BA7D78D27671D1150CB21409CA1712801B1D1D1B1D1D1B1D1D1B1D1D120B891B1D1D1B1D1D1B1D1D1B1D1D120B891B1D1D1B1D1D1B1D1D1B1D1D1712801712807F8080D4D5D5D4D5D5383939120B89545656D4D5D5D4D5D5626464130C89292B2BD4D5D5D4D5D56264641915801712804647471B1D1DAAAAAAD4D5D5130E82383939292B2B717272D4D5D5151183D4D5D57F80801B1D1D7172721E1C81191580464747D4D5D5D4D5D51B1D1D19158A292B2BD4D5D5D4D5D5292B2B1B1B8AD4D5D56264641B1D1D1B1D1D2427821E1D81D4D5D54647476264643839391E208BD4D5D57F8080464747545656242A8BD4D5D59B9C9C292B2BAAAAAA2D3683252882464747D4D5D5D4D5D51B1D1D272D85292B2BD4D5D5D4D5D5292B2B2E37861B1D1DD4D5D5D4D5D5464747394484323BB52324812122822426822526824554C0323883292B822A2D83353C84424CBF3238843940842E32834853865D6EBB5262EB3E43E83334E74147E94349E9535FEB4D56EA5662EB484DEA545DEB636FED545AEA5A63EC6671ED8CA0F290A5F2748AEF6B7BEE5D68EC6874ED788AEF8397F17684EF7986EF8C9FF2818FF1818EF08E9DF18A97F18791F19BA9F3B0C0F691A4F291A2F28390F192A1F29CACF3A3B3F498A6F3A4B3F4AEBDF5B0BEF59EA8F3A3ADF4BBC7F7C4D1F8CAD7F8CED9F9B4C4F6B8C8F6ACB8F59AA3F3B6C1F6C5D2F8C2CDF8CCD7F9D2DDF9D5E0FAD2DAF9D5DCF9DFE7FBE2E9FBE5EBFBE8EEFB0000 + + + + + csv,csp - axis + dynamic switch bewteen csp/csv + + #x1600 + Outputs + + #x6040 + 0 + 16 + Control Word + object 0x6040:0 + UINT + + + #x607A + 0 + 32 + TargetPosition + object 0x607A:0 + DINT + + + #x60FF + 0 + 32 + TargetVelocity + object 0x60FF:0 + DINT + + + #x6060 + 0 + 8 + ModeOfOperation + object 0x6060:0 + USINT + + + 0 + 0 + 8 + + + + #x1a00 + Inputs + + #x6041 + 0 + 16 + Status Word + object 0x6041:0 + UINT + + + #x6064 + 0 + 32 + ActualPosition + object 0x6064:0 + DINT + + + #x606C + 0 + 32 + ActualVelocity + object 0x606C:0 + DINT + + + #x6061 + 0 + 8 + ModeOfOperationDisplay + object 0x6061:0 + USINT + + + 0 + 0 + 8 + + + + 402 + 2 + + + + SINT + 8 + + + USINT + 8 + + + UDINT + 32 + + + DINT + 32 + + + INT + 16 + + + UINT + 16 + + + DT607DARR + DINT + 64 + + 1 + 2 + + + + DT607D + 80 + + 0 + SubIndex 000 + USINT + 8 + 0 + + ro + + + + Elements + DT607DARR + 64 + 16 + + rw + r + + + + + DT60C2 + 32 + + 0 + SubIndex 000 + USINT + 8 + 0 + + ro + + + + 1 + Interpolation time period value + USINT + 8 + 16 + + rw + r + + + + 2 + Interpolation time index + SINT + 8 + 24 + + rw + r + + + + + + + #x603F + Error Code + UINT + 16 + + ro + t + + + + #x6040 + Control Word + UINT + 16 + + rw + r + + + + #x6041 + Status Word + UINT + 16 + + ro + t + + + + #x605A + Quick stop option code + INT + 16 + + rw + + + + #x605B + Shutdown option code + INT + 16 + + rw + + + + #x605C + Disable operation option code + INT + 16 + + rw + + + + #x605E + Fault reaction option code + INT + 16 + + rw + + + + #x6060 + Modes of operation + SINT + 8 + + rw + r + + + + #x6061 + Modes of operation display + SINT + 8 + + ro + t + + + + #x6064 + Position actual value + DINT + 32 + + ro + t + + + + #x606C + Velocity actual value + DINT + 32 + + ro + t + + + + #x6077 + Torque actual value + INT + 16 + + ro + t + + + + #x607D + Software position limit + DT607D + 80 + + + #x607A + Target position + DINT + 32 + + rw + r + + + + #x6085 + Quick stop deceleration + UDINT + 32 + + rw + r + + + + #x60C2 + Interpolation time period + DT60C2 + 32 + + + #x60FF + Target velocity + DINT + 32 + + rw + r + + + + #x6502 + Supported drive modes + UDINT + 32 + + ro + t + + + + + + + + csp - axis + csp + + #x1601 + Outputs + + #x6040 + 0 + 16 + Control Word + object 0x6040:0 + UINT + + + #x607A + 0 + 32 + TargetPosition + object 0x607A:0 + DINT + + + #x0 + 0 + 16 + 16bit padding + + + + #x1a01 + Inputs + + #x6041 + 0 + 16 + Status Word + object 0x6041:0 + UINT + + + #x6064 + 0 + 32 + ActualPosition + object 0x6064:0 + DINT + + + #x0 + 0 + 16 + 16bit padding + + + + + + SO + #x6060 + 0 + 08 + + + + + 402 + 2 + + + + SINT + 8 + + + USINT + 8 + + + UDINT + 32 + + + DINT + 32 + + + INT + 16 + + + UINT + 16 + + + DT60C2 + 32 + + 0 + SubIndex 000 + USINT + 8 + 0 + + ro + + + + 1 + Interpolation time period value + USINT + 8 + 16 + + rw + r + + + + 2 + Interpolation time index + SINT + 8 + 24 + + rw + r + + + + + DT607DARR + DINT + 64 + + 1 + 2 + + + + DT607D + 80 + + 0 + SubIndex 000 + USINT + 8 + 0 + + ro + + + + Elements + DT607DARR + 64 + 16 + + rw + r + + + + + + + #x603F + Error Code + UINT + 16 + + ro + t + + + + #x6040 + Control Word + UINT + 16 + + rw + r + + + + #x6041 + Status Word + UINT + 16 + + ro + t + + + + #x605A + Quick stop option code + INT + 16 + + rw + + + + #x605B + Shutdown option code + INT + 16 + + rw + + + + #x605C + Disable operation option code + INT + 16 + + rw + + + + #x605E + Fault reaction option code + INT + 16 + + rw + + + + #x6060 + Modes of operation + SINT + 8 + + rw + r + + + + #x6061 + Modes of operation display + SINT + 8 + + ro + t + + + + #x6064 + Position actual value + DINT + 32 + + ro + t + + + + #x606C + Velocity actual value + DINT + 32 + + ro + t + + + + #x6077 + Torque actual value + INT + 16 + + ro + t + + + + #x607D + Software position limit + DT607D + 80 + + + #x607A + Target position + DINT + 32 + + rw + r + + + + #x6085 + Quick stop deceleration + UDINT + 32 + + rw + r + + + + #x60C2 + Interpolation time period + DT60C2 + 32 + + + #x60FF + Target velocity + DINT + 32 + + rw + r + + + + #x6502 + Supported drive modes + UDINT + 32 + + ro + t + + + + + + + + csv - axis + csv + + #x1602 + Outputs + + #x6040 + 0 + 16 + Control Word + object 0x6040:0 + UINT + + + #x60FF + 0 + 32 + TargetVelocity + object 0x60FF:0 + DINT + + + #x0 + 0 + 16 + 16bit padding + + + + #x1a02 + Inputs + + #x6041 + 0 + 16 + Status Word + object 0x6041:0 + UINT + + + #x6064 + 0 + 32 + ActualPosition + object 0x6064:0 + DINT + + + #x0 + 0 + 16 + 16bit padding + + + + + + SO + #x6060 + 0 + 09 + + + + + 402 + 2 + + + + SINT + 8 + + + USINT + 8 + + + UDINT + 32 + + + DINT + 32 + + + INT + 16 + + + UINT + 16 + + + DT607DARR + DINT + 64 + + 1 + 2 + + + + DT607D + 80 + + 0 + SubIndex 000 + USINT + 8 + 0 + + ro + + + + Elements + DT607DARR + 64 + 16 + + rw + r + + + + + DT60C2 + 32 + + 0 + SubIndex 000 + USINT + 8 + 0 + + ro + + + + 1 + Interpolation time period value + USINT + 8 + 16 + + rw + r + + + + 2 + Interpolation time index + SINT + 8 + 24 + + rw + r + + + + + + + #x603F + Error Code + UINT + 16 + + ro + t + + + + #x6040 + Control Word + UINT + 16 + + rw + r + + + + #x6041 + Status Word + UINT + 16 + + ro + t + + + + #x605A + Quick stop option code + INT + 16 + + rw + + + + #x605B + Shutdown option code + INT + 16 + + rw + + + + #x605C + Disable operation option code + INT + 16 + + rw + + + + #x605E + Fault reaction option code + INT + 16 + + rw + + + + #x6060 + Modes of operation + SINT + 8 + + rw + r + + + + #x6061 + Modes of operation display + SINT + 8 + + ro + t + + + + #x6064 + Position actual value + DINT + 32 + + ro + t + + + + #x606C + Velocity actual value + DINT + 32 + + ro + t + + + + #x6077 + Torque actual value + INT + 16 + + ro + t + + + + #x607D + Software position limit + DT607D + 80 + + + #x607A + Target position + DINT + 32 + + rw + r + + + + #x6085 + Quick stop deceleration + UDINT + 32 + + rw + r + + + + #x60C2 + Interpolation time period + DT60C2 + 32 + + + #x60FF + Target velocity + DINT + 32 + + rw + r + + + + #x6502 + Supported drive modes + UDINT + 32 + + ro + t + + + + + + + + + \ No newline at end of file diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/eeprom.bin b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/eeprom.bin new file mode 100644 index 00000000..2d1dbc42 Binary files /dev/null and b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/eeprom.bin differ diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/eeprom.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/eeprom.h new file mode 100644 index 00000000..12e2d4d2 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/eeprom.h @@ -0,0 +1,138 @@ +/* +The EEPROM data is created based on EtherCAT Slave Information (ESI) XML file. +Generated 2048 bytes of EEPROM data +Vendor ID: 0x0048504D +Product Code: 0x00000003 +Revision: 0x00000001 +Device Name: ECAT_CIA402 +*/ +unsigned char cherryecat_eepromdata[] = { +0x0C,0x80,0x81,0x66,0x00,0x00,0x00,0x00,0x12,0x34,0x00,0x00,0x61,0xE5,0x4D,0x50, +0x48,0x00,0x03,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10, +0x80,0x00,0x80,0x10,0x80,0x00,0x00,0x10,0x80,0x00,0x80,0x10,0x80,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x0A,0x00,0x0D,0x00,0x02,0x0B,0x45,0x43,0x41,0x54,0x5F,0x44,0x65,0x76,0x69,0x63, +0x65,0x0B,0x45,0x43,0x41,0x54,0x5F,0x43,0x49,0x41,0x34,0x30,0x32,0x00,0x1E,0x00, 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b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/eni_parser.py new file mode 100644 index 00000000..118635bb --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/eni_parser.py @@ -0,0 +1,381 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +""" +ENI (EtherCAT Network Information) Parser + +Copyright (c) 2025, sakumisu + +SPDX-License-Identifier: Apache-2.0 + +""" + +import xml.etree.ElementTree as ET +import sys +import os +from typing import Dict, List, Tuple, Optional + +class ENIParser: + def __init__(self): + self.slaves = [] + + def parse_hex_value(self, hex_str: str) -> int: + """解析十六进制字符串""" + if not hex_str: + return 0 + hex_str = hex_str.strip() + if hex_str.startswith('#x'): + return int(hex_str[2:], 16) + elif hex_str.startswith('0x'): + return int(hex_str[2:], 16) + else: + try: + return int(hex_str, 16) + except: + try: + return int(hex_str, 10) + except: + return 0 + + def parse_slave_info(self, slave_elem): + """解析从站基本信息""" + slave_info = {} + + info_elem = slave_elem.find('Info') + if info_elem is not None: + name_elem = info_elem.find('Name') + if name_elem is not None: + slave_info['name'] = name_elem.text.strip() if name_elem.text else "" + + vendor_id_elem = info_elem.find('VendorId') + if vendor_id_elem is not None: + slave_info['vendor_id'] = int(vendor_id_elem.text) + + product_code_elem = info_elem.find('ProductCode') + if product_code_elem is not None: + slave_info['product_code'] = int(product_code_elem.text) + + revision_no_elem = info_elem.find('RevisionNo') + if revision_no_elem is not None: + slave_info['revision_no'] = int(revision_no_elem.text) + + return slave_info + + def parse_pdo_entry(self, entry_elem): + """解析单个PDO条目""" + entry_info = {} + + # 解析Index + index_elem = entry_elem.find('Index') + if index_elem is not None and index_elem.text: + entry_info['index'] = self.parse_hex_value(index_elem.text) + else: + entry_info['index'] = 0x0000 + + # 解析SubIndex + subindex_elem = entry_elem.find('SubIndex') + if subindex_elem is not None and subindex_elem.text: + entry_info['subindex'] = int(subindex_elem.text) + else: + entry_info['subindex'] = 0x00 + + # 解析BitLen + bitlen_elem = entry_elem.find('BitLen') + if bitlen_elem is not None and bitlen_elem.text: + entry_info['bit_length'] = int(bitlen_elem.text) + else: + entry_info['bit_length'] = 16 + + # 解析Name (作为注释) + name_elem = entry_elem.find('Name') + if name_elem is not None and name_elem.text: + entry_info['name'] = name_elem.text.strip() + else: + # 如果Index是0或#x0，标记为Padding + if entry_info['index'] == 0: + entry_info['name'] = 'Padding' + else: + entry_info['name'] = f'Object_{entry_info["index"]:04X}' + + # 解析DataType + datatype_elem = entry_elem.find('DataType') + if datatype_elem is not None and datatype_elem.text: + entry_info['data_type'] = datatype_elem.text.strip() + else: + entry_info['data_type'] = 'UINT' + + # 解析Comment + comment_elem = entry_elem.find('Comment') + if comment_elem is not None and comment_elem.text: + entry_info['comment'] = comment_elem.text.strip() + else: + entry_info['comment'] = '' + + return entry_info + + def parse_process_data(self, slave_elem): + """解析过程数据配置""" + process_data = { + 'rx_pdos': [], # 输出PDO (主站->从站) + 'tx_pdos': [], # 输入PDO (从站->主站) + 'syncs': [] + } + + process_elem = slave_elem.find('ProcessData') + if process_elem is None: + return process_data + + # 解析RxPDO (输出) + for rxpdo_elem in process_elem.findall('RxPdo'): + pdo_info = {} + + # 解析PDO Index + index_elem = rxpdo_elem.find('Index') + if index_elem is not None: + pdo_info['index'] = self.parse_hex_value(index_elem.text) + + # 解析PDO Name + name_elem = rxpdo_elem.find('Name') + if name_elem is not None: + pdo_info['name'] = name_elem.text.strip() if name_elem.text else "" + + # 解析所有Entry + entries = [] + for entry_elem in rxpdo_elem.findall('Entry'): + entry_info = self.parse_pdo_entry(entry_elem) + entries.append(entry_info) + + pdo_info['entries'] = entries + process_data['rx_pdos'].append(pdo_info) + + # 解析TxPDO (输入) + for txpdo_elem in process_elem.findall('TxPdo'): + pdo_info = {} + + # 解析PDO Index + index_elem = txpdo_elem.find('Index') + if index_elem is not None: + pdo_info['index'] = self.parse_hex_value(index_elem.text) + + # 解析PDO Name + name_elem = txpdo_elem.find('Name') + if name_elem is not None: + pdo_info['name'] = name_elem.text.strip() if name_elem.text else "" + + # 解析所有Entry + entries = [] + for entry_elem in txpdo_elem.findall('Entry'): + entry_info = self.parse_pdo_entry(entry_elem) + entries.append(entry_info) + + pdo_info['entries'] = entries + process_data['tx_pdos'].append(pdo_info) + + # 解析同步管理器配置 + sm2_elem = process_elem.find('Sm2') + if sm2_elem is not None: + sm_info = { + 'index': 2, + 'direction': 'EC_DIR_OUTPUT', + 'type': sm2_elem.find('Type').text if sm2_elem.find('Type') is not None else 'Outputs' + } + process_data['syncs'].append(sm_info) + + sm3_elem = process_elem.find('Sm3') + if sm3_elem is not None: + sm_info = { + 'index': 3, + 'direction': 'EC_DIR_INPUT', + 'type': sm3_elem.find('Type').text if sm3_elem.find('Type') is not None else 'Inputs' + } + process_data['syncs'].append(sm_info) + + return process_data + + def parse_eni(self, eni_file: str) -> bool: + """解析ENI文件""" + try: + tree = ET.parse(eni_file) + root = tree.getroot() + + # 解析从站配置 + for slave_elem in root.findall('.//Slave'): + slave_info = self.parse_slave_info(slave_elem) + process_data = self.parse_process_data(slave_elem) + + slave_config = { + 'info': slave_info, + 'process_data': process_data + } + + self.slaves.append(slave_config) + + return True + + except Exception as e: + print(f"Error parsing ENI file: {e}") + import traceback + traceback.print_exc() + return False + + def generate_slave_name(self, slave_info): + """生成从站名称标识符""" + name = slave_info.get('name', 'slave') + # 清理名称，只保留字母数字和下划线 + clean_name = ''.join(c if c.isalnum() or c == '_' else '_' for c in name.lower()) + clean_name = clean_name.replace('__', '_').strip('_') + + # 根据产品代码生成后缀 + product_code = slave_info.get('product_code', 0) + return f'eni_{product_code:04x}' + + def generate_c_code(self) -> str: + """生成C代码""" + lines = [ + "/*", + " * Generated CherryECAT PDO configuration from ENI file", + " * Auto-generated - do not modify manually", + " */", + "", + "#include \"ec_master.h\"", + "" + ] + + for slave_idx, slave in enumerate(self.slaves): + slave_info = slave['info'] + process_data = slave['process_data'] + + slave_name = self.generate_slave_name(slave_info) + + lines.append(f"// Slave {slave_idx + 1}: {slave_info.get('name', 'Unknown')}") + lines.append(f"// Vendor ID: 0x{slave_info.get('vendor_id', 0):08X}") + lines.append(f"// Product Code: 0x{slave_info.get('product_code', 0):08X}") + lines.append("") + + # 生成RxPDO entries (输出) + rx_entries_generated = set() + for pdo in process_data['rx_pdos']: + pdo_index = pdo.get('index', 0) + pdo_hex = f"{pdo_index:04x}" + entries_name = f"{slave_name}_{pdo_hex}" + + if entries_name not in rx_entries_generated: + lines.append(f"static ec_pdo_entry_info_t {entries_name}[] = {{") + + # 生成每个entry + for entry in pdo.get('entries', []): + comment = entry.get('name', 'Padding') + lines.append(f" {{ 0x{entry['index']:04x}, 0x{entry['subindex']:02x}, 0x{entry['bit_length']:02x} }}, // {comment}") + + lines.append("};") + lines.append("") + rx_entries_generated.add(entries_name) + + # 生成TxPDO entries (输入) + tx_entries_generated = set() + for pdo in process_data['tx_pdos']: + pdo_index = pdo.get('index', 0) + pdo_hex = f"{pdo_index:04x}" + entries_name = f"{slave_name}_{pdo_hex}" + + if entries_name not in tx_entries_generated: + lines.append(f"static ec_pdo_entry_info_t {entries_name}[] = {{") + + # 生成每个entry + for entry in pdo.get('entries', []): + comment = entry.get('name', 'Padding') + lines.append(f" {{ 0x{entry['index']:04x}, 0x{entry['subindex']:02x}, 0x{entry['bit_length']:02x} }}, // {comment}") + + lines.append("};") + lines.append("") + tx_entries_generated.add(entries_name) + + # 生成RxPDO info + if process_data['rx_pdos']: + lines.append(f"static ec_pdo_info_t {slave_name}_rxpdos[] = {{") + for pdo in process_data['rx_pdos']: + pdo_index = pdo.get('index', 0) + pdo_hex = f"{pdo_index:04x}" + entries_name = f"{slave_name}_{pdo_hex}" + entry_count = len(pdo.get('entries', [])) + lines.append(f" {{ 0x{pdo_index:04x}, {entry_count}, &{entries_name}[0] }},") + lines.append("};") + lines.append("") + + # 生成TxPDO info + if process_data['tx_pdos']: + lines.append(f"static ec_pdo_info_t {slave_name}_txpdos[] = {{") + for pdo in process_data['tx_pdos']: + pdo_index = pdo.get('index', 0) + pdo_hex = f"{pdo_index:04x}" + entries_name = f"{slave_name}_{pdo_hex}" + entry_count = len(pdo.get('entries', [])) + lines.append(f" {{ 0x{pdo_index:04x}, {entry_count}, &{entries_name}[0] }},") + lines.append("};") + lines.append("") + + # 生成同步管理器配置 + lines.append(f"static ec_sync_info_t {slave_name}_syncs[] = {{") + + # 添加SM2 (输出) + if process_data['rx_pdos']: + lines.append(f" {{ 2, EC_DIR_OUTPUT, {len(process_data['rx_pdos'])}, {slave_name}_rxpdos }},") + + # 添加SM3 (输入) + if process_data['tx_pdos']: + lines.append(f" {{ 3, EC_DIR_INPUT, {len(process_data['tx_pdos'])}, {slave_name}_txpdos }},") + + lines.append("};") + lines.append("") + + return "\n".join(lines) + +def main(): + if len(sys.argv) != 3: + print("Usage: python eni_parser.py ") + print(" input.xml - ENI XML file") + print(" output.h - Output C header file") + sys.exit(1) + + input_file = sys.argv[1] + output_file = sys.argv[2] + + if not os.path.exists(input_file): + print(f"Error: Input file '{input_file}' not found") + sys.exit(1) + + # 创建解析器 + parser = ENIParser() + + # 解析ENI文件 + print(f"Parsing ENI file: {input_file}") + if not parser.parse_eni(input_file): + print("Failed to parse ENI file") + sys.exit(1) + + # 生成C代码 + print("Generating C code...") + c_code = parser.generate_c_code() + + # 写入输出文件 + try: + with open(output_file, 'w') as f: + f.write(c_code) + + print(f"✓ Successfully converted '{input_file}' to '{output_file}'") + print(f"✓ Generated C code for {len(parser.slaves)} slave(s)") + + # 显示生成的PDO映射信息 + for slave_idx, slave in enumerate(parser.slaves): + process_data = slave['process_data'] + print(f"✓ Slave {slave_idx + 1}:") + for pdo in process_data['rx_pdos']: + print(f" - RxPDO 0x{pdo.get('index', 0):04X}: {len(pdo.get('entries', []))} entries") + for pdo in process_data['tx_pdos']: + print(f" - TxPDO 0x{pdo.get('index', 0):04X}: {len(pdo.get('entries', []))} entries") + + except Exception as e: + print(f"Error writing output file: {e}") + sys.exit(1) + +if __name__ == "__main__": + main() diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/esi_parser.py b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/esi_parser.py new file mode 100644 index 00000000..add2f274 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/esi_parser.py @@ -0,0 +1,510 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +""" +ESI(EtherCAT Slave Information) to EEPROM Binary Converter + +Copyright (c) 2025, sakumisu + +SPDX-License-Identifier: Apache-2.0 + +""" + +import xml.etree.ElementTree as ET +import struct +import sys +import os +from typing import Dict, List, Tuple, Optional + +class EtherCATXMLParser: + def __init__(self): + # 设备基本信息 + self.vendor_id = 0x00000000 # 默认厂商ID + self.product_code = 0x00000000 # 默认产品代码 + self.revision_no = 0x00000000 # 默认版本号 + self.serial_number = 0x00000000 # 序列号 + self.device_name = "" + self.device_type = "" + + # 邮箱配置 + self.mailbox_protocols = 0x0 + self.boot_rx_mailbox = {} + self.boot_tx_mailbox = {} + self.std_rx_mailbox = {} + self.std_tx_mailbox = {} + + # 字符串表 + self.strings = [] + + # 类别数据 + self.categories = [] + + def parse_hex_value(self, hex_str: str) -> int: + """解析十六进制字符串""" + if not hex_str: + return 0 + hex_str = hex_str.strip() + if hex_str.startswith('#x'): + return int(hex_str[2:], 16) + elif hex_str.startswith('0x'): + return int(hex_str[2:], 16) + else: + try: + return int(hex_str, 16) + except: + return int(hex_str, 10) + + def parse_device_info(self, device_elem): + """解析设备基本信息""" + # 获取产品代码和版本号 + type_elem = device_elem.find('Type') + if type_elem is not None: + product_code = type_elem.get('ProductCode') + if product_code: + self.product_code = self.parse_hex_value(product_code) + + revision_no = type_elem.get('RevisionNo') + if revision_no: + self.revision_no = self.parse_hex_value(revision_no) + + # 获取设备名称 + name_elem = device_elem.find('Name') + if name_elem is not None and name_elem.text: + self.device_name = name_elem.text.strip() + + # 获取设备类型 + type_name = device_elem.find('Type/Name') + if type_name is not None and type_name.text: + self.device_type = type_name.text.strip() + + def parse_vendor_info(self, vendor_elem): + """解析厂商信息""" + vendor_id_elem = vendor_elem.find('Id') + if vendor_id_elem is not None and vendor_id_elem.text: + self.vendor_id = self.parse_hex_value(vendor_id_elem.text) + + def parse_mailbox_info(self, device_elem): + """解析邮箱信息""" + mailbox_elem = device_elem.find('.//Mailbox') + if mailbox_elem is not None: + # 检查支持的协议 + self.mailbox_protocols = 0 + + if mailbox_elem.find('CoE') is not None: + self.mailbox_protocols |= 0x04 # CoE + if mailbox_elem.find('FoE') is not None: + self.mailbox_protocols |= 0x08 # FoE + if mailbox_elem.find('EoE') is not None: + self.mailbox_protocols |= 0x10 # EoE + if mailbox_elem.find('SoE') is not None: + self.mailbox_protocols |= 0x20 # SoE + + # 从SM配置中获取邮箱地址和大小 + sm_elems = device_elem.findall('.//Sm') + for i, sm_elem in enumerate(sm_elems): + start_addr = self.parse_hex_value(sm_elem.get('StartAddress', '0')) + size = self.parse_hex_value(sm_elem.get('DefaultSize', '0')) + + if i == 0: # MBoxOut (接收) + self.boot_rx_mailbox = {"offset": start_addr, "size": size} + self.std_rx_mailbox = {"offset": start_addr, "size": size} + elif i == 1: # MBoxIn (发送) + self.boot_tx_mailbox = {"offset": start_addr, "size": size} + self.std_tx_mailbox = {"offset": start_addr, "size": size} + + def add_string(self, text: str) -> int: + """添加字符串到字符串表，返回索引""" + if not text: + return 0 + + # 检查是否已存在 + for i, existing in enumerate(self.strings): + if existing == text: + return i + 1 + + # 添加新字符串 + self.strings.append(text) + return len(self.strings) + + def create_strings_category(self) -> bytes: + """创建字符串类别(Category 10)""" + if not self.strings: + return b'' + + data = bytearray() + + # 字符串数量 + data.append(len(self.strings)) + + # 每个字符串: 长度 + 内容 + for string in self.strings: + string_bytes = string.encode('ascii', errors='replace') + data.append(len(string_bytes)) + data.extend(string_bytes) + + # 填充到偶数长度 + if len(data) % 2: + data.append(0) + + return bytes(data) + + def create_general_category(self) -> bytes: + """创建通用类别(Category 30)""" + data = bytearray() + + # Group Type String Index (2 bytes) + group_idx = self.add_string("ECAT_Device") + data.extend(struct.pack(' bytes: + """创建FMMU类别(Category 40)""" + data = bytearray() + + # FMMU配置 - 8个FMMU + fmmu_configs = [ + 0x01, # FMMU0: Outputs + 0x02, # FMMU1: Inputs + 0x03, # FMMU2: MBox State + 0x00, # FMMU3: Unused + 0x00, # FMMU4: Unused + 0x00, # FMMU5: Unused + 0x00, # FMMU6: Unused + 0x00, # FMMU7: Unused + ] + + for config in fmmu_configs: + data.append(config) + + return bytes(data) + + def create_sm_category(self) -> bytes: + """创建同步管理器类别(Category 41)""" + data = bytearray() + + # SM配置数据结构: StartAddr(2) + Length(2) + ControlByte(1) + Enable(1) + sm_configs = [ + # SM0: MBoxOut (接收邮箱) + (self.boot_rx_mailbox["offset"], self.boot_rx_mailbox["size"], 0x26, 0x01), + # SM1: MBoxIn (发送邮箱) + (self.boot_tx_mailbox["offset"], self.boot_tx_mailbox["size"], 0x22, 0x01), + # SM2: Process Data Output + (0x1100, 0x0000, 0x64, 0x00), # 长度为0表示未配置 + # SM3: Process Data Input + (0x1400, 0x0000, 0x20, 0x00), # 长度为0表示未配置 + # SM4-7: 未使用 + (0x0000, 0x0000, 0x00, 0x00), + (0x0000, 0x0000, 0x00, 0x00), + (0x0000, 0x0000, 0x00, 0x00), + (0x0000, 0x0000, 0x00, 0x00), + ] + + for start_addr, length, control, enable in sm_configs: + data.extend(struct.pack(' bytes: + """创建类别头部+数据""" + header = bytearray() + + # Category Type (2 bytes) + header.extend(struct.pack(' bytes: + """生成完整的EEPROM数据，参考eeprom.h的格式""" + eeprom_data = bytearray() + + # === EEPROM Header (固定128字节) === + + # PDI Control (2 bytes) - 0x800C (Digital I/O + SII EEPROM) + eeprom_data.extend(struct.pack(' bool: + """解析XML文件""" + try: + tree = ET.parse(xml_file) + root = tree.getroot() + + # 查找并解析厂商信息 + vendor_elem = root.find('.//Vendor') + if vendor_elem is not None: + self.parse_vendor_info(vendor_elem) + + # 查找并解析设备信息 + device_elem = root.find('.//Device') + if device_elem is not None: + self.parse_device_info(device_elem) + self.parse_mailbox_info(device_elem) + + print(f"Parsed XML: Vendor=0x{self.vendor_id:08X}, Product=0x{self.product_code:08X}") + print(f"Device Name: {self.device_name}") + print(f"Mailbox RX: 0x{self.std_rx_mailbox['offset']:04X}({self.std_rx_mailbox['size']})") + print(f"Mailbox TX: 0x{self.std_tx_mailbox['offset']:04X}({self.std_tx_mailbox['size']})") + + return True + + except Exception as e: + print(f"Error parsing XML file: {e}") + import traceback + traceback.print_exc() + return False + + def generate_c_header(self, array_name: str = "cherryecat_eepromdata") -> str: + """生成C语言头文件格式的数组""" + eeprom_data = self.generate_eeprom() + + lines = [ + "/*", + f"The EEPROM data is created based on EtherCAT Slave Information (ESI) XML file.", + f"Generated {len(eeprom_data)} bytes of EEPROM data", + f"Vendor ID: 0x{self.vendor_id:08X}", + f"Product Code: 0x{self.product_code:08X}", + f"Revision: 0x{self.revision_no:08X}", + f"Device Name: {self.device_name}", + "*/", + f"unsigned char {array_name}[] = {{", + ] + + # 按16字节一行格式化数据 + for i in range(0, len(eeprom_data), 16): + chunk = eeprom_data[i:i+16] + hex_values = [f"0x{b:02X}" for b in chunk] + line = ",".join(hex_values) + if i + 16 < len(eeprom_data): + line += "," + lines.append(line) + + lines.append("};") + + return "\n".join(lines) + +def main(): + if len(sys.argv) < 3: + print("Usage: python esi_parse.py [output.h]") + print(" input.xml - EtherCAT ESI XML file") + print(" output.bin - Output binary EEPROM file") + print(" output.h - Optional C header file output") + sys.exit(1) + + input_file = sys.argv[1] + output_file = sys.argv[2] + header_file = sys.argv[3] if len(sys.argv) > 3 else None + + if not os.path.exists(input_file): + print(f"Error: Input file '{input_file}' not found") + sys.exit(1) + + # 创建解析器 + parser = EtherCATXMLParser() + + # 解析XML + print(f"Parsing XML file: {input_file}") + if not parser.parse_xml(input_file): + print("Failed to parse XML file") + sys.exit(1) + + # 生成EEPROM数据 + print("Generating EEPROM data...") + eeprom_data = parser.generate_eeprom() + + # 写入二进制文件 + try: + with open(output_file, 'wb') as f: + f.write(eeprom_data) + + print(f"✓ Successfully converted '{input_file}' to '{output_file}'") + print(f"✓ Generated {len(eeprom_data)} bytes of EEPROM data") + print(f"✓ Vendor ID: 0x{parser.vendor_id:08X}") + print(f"✓ Product Code: 0x{parser.product_code:08X}") + print(f"✓ Revision: 0x{parser.revision_no:08X}") + print(f"✓ Device Name: {parser.device_name}") + + except Exception as e: + print(f"Error writing binary file: {e}") + sys.exit(1) + + # 生成C头文件(可选) + if header_file: + try: + header_content = parser.generate_c_header() + with open(header_file, 'w') as f: + f.write(header_content) + print(f"✓ Generated C header file: {header_file}") + except Exception as e: + print(f"Error writing header file: {e}") + +if __name__ == "__main__": + main() diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/sync_config.h b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/sync_config.h new file mode 100644 index 00000000..68152ba1 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/scripts/sync_config.h @@ -0,0 +1,35 @@ +/* + * Generated CherryECAT PDO configuration from ENI file + * Auto-generated - do not modify manually + */ + +#include "ec_master.h" + +// Slave 1: Drive 1 (ECAT_CIA402) +// Vendor ID: 0x0048504D +// Product Code: 0x00000003 + +static ec_pdo_entry_info_t eni_0003_1602[] = { + { 0x6040, 0x00, 0x10 }, // Control Word + { 0x60ff, 0x00, 0x20 }, // TargetVelocity + { 0x0000, 0x00, 0x10 }, // Padding +}; + +static ec_pdo_entry_info_t eni_0003_1a02[] = { + { 0x6041, 0x00, 0x10 }, // Status Word + { 0x6064, 0x00, 0x20 }, // ActualPosition + { 0x0000, 0x00, 0x10 }, // Padding +}; + +static ec_pdo_info_t eni_0003_rxpdos[] = { + { 0x1602, 3, &eni_0003_1602[0] }, +}; + +static ec_pdo_info_t eni_0003_txpdos[] = { + { 0x1a02, 3, &eni_0003_1a02[0] }, +}; + +static ec_sync_info_t eni_0003_syncs[] = { + { 2, EC_DIR_OUTPUT, 1, eni_0003_rxpdos }, + { 3, EC_DIR_INPUT, 1, eni_0003_txpdos }, +}; diff --git a/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_cmd.c b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_cmd.c new file mode 100644 index 00000000..620c2f29 --- /dev/null +++ b/projects/etherkit_ethercat_cherryecat/packages/CherryECAT-latest/src/ec_cmd.c @@ -0,0 +1,1059 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "ec_master.h" + +#ifdef CONFIG_EC_CMD_ENABLE + +typedef struct { + uint32_t slave_count; + uint8_t phase; + uint8_t active; + struct ec_ioctl_device { + uint8_t mac_addr[6]; + uint8_t attached; + uint8_t link_state; + uint64_t tx_count; + uint64_t rx_count; + uint64_t tx_bytes; + uint64_t rx_bytes; + uint64_t tx_errors; + int32_t tx_frame_rates[EC_RATE_COUNT]; + int32_t rx_frame_rates[EC_RATE_COUNT]; + int32_t tx_byte_rates[EC_RATE_COUNT]; + int32_t rx_byte_rates[EC_RATE_COUNT]; + } netdevs[CONFIG_EC_MAX_NETDEVS]; + uint32_t num_netdevs; + uint64_t tx_count; + uint64_t rx_count; + uint64_t tx_bytes; + uint64_t rx_bytes; + int32_t tx_frame_rates[EC_RATE_COUNT]; + int32_t rx_frame_rates[EC_RATE_COUNT]; + int32_t tx_byte_rates[EC_RATE_COUNT]; + int32_t rx_byte_rates[EC_RATE_COUNT]; + int32_t loss_rates[EC_RATE_COUNT]; + uint64_t app_time; + uint64_t dc_ref_time; + uint16_t ref_clock; +} ec_cmd_master_info_t; + +typedef struct { + uint32_t netdev_idx; + uint32_t vendor_id; + uint32_t product_code; + uint32_t revision_number; + uint32_t serial_number; + uint16_t alias; + uint16_t boot_rx_mailbox_offset; + uint16_t boot_rx_mailbox_size; + uint16_t boot_tx_mailbox_offset; + uint16_t boot_tx_mailbox_size; + uint16_t std_rx_mailbox_offset; + uint16_t std_rx_mailbox_size; + uint16_t std_tx_mailbox_offset; + uint16_t std_tx_mailbox_size; + uint16_t mailbox_protocols; + bool has_general; + ec_sii_coe_details_t coe_details; + ec_sii_general_flags_t general_flags; + int16_t current_on_ebus; + struct { + ec_slave_port_desc_t desc; + ec_slave_port_link_t link; + uint32_t receive_time; + uint16_t next_slave; + uint32_t delay_to_next_dc; + } ports[EC_MAX_PORTS]; + uint8_t base_fmmu_bit_operation; + uint8_t base_dc_supported; + ec_slave_dc_range_t base_dc_range; + uint8_t has_dc_system_time; + uint32_t transmission_delay; + uint8_t current_state; + uint8_t error_flag; + uint8_t sync_count; + uint16_t sdo_count; + uint32_t sii_nwords; + char *group; + char *image; + char *order; + char *name; +} ec_cmd_slave_info_t; + +static ec_master_t *global_cmd_master = NULL; + +void ec_master_cmd_init(ec_master_t *master) +{ + global_cmd_master = master; +} + +static void ec_master_cmd_show_help(void) +{ + EC_LOG_RAW("CherryECAT " CHERRYECAT_VERSION_STR " Command Line Tool\n\n"); + EC_LOG_RAW("Usage: ethercat [options]\n"); + EC_LOG_RAW("Commands:\n"); + EC_LOG_RAW(" master Show master information\n"); + EC_LOG_RAW(" slaves Show slaves overview\n"); + EC_LOG_RAW(" slaves -v Show detailed information for all slaves\n"); + EC_LOG_RAW(" slaves -p Show information for slave \n"); + EC_LOG_RAW(" slaves -p -v Show detailed information for slave \n"); + EC_LOG_RAW(" pdos Show PDOs for all slaves\n"); + EC_LOG_RAW(" pdos -p Show PDOs for slave \n"); + EC_LOG_RAW(" states Request state for all slaves (hex)\n"); + EC_LOG_RAW(" states -p Request state for slave (hex)\n"); + EC_LOG_RAW(" coe_read -p [idx] [index] [subindex] Read SDO via CoE\n"); + EC_LOG_RAW(" coe_write -p [idx] [index] [subindex] [data] Write SDO via CoE\n"); + EC_LOG_RAW(" pdo_read Read process data\n"); + EC_LOG_RAW(" pdo_read -p [idx] Read slave process data\n"); + EC_LOG_RAW(" pdo_write [offset] [hex low...high] Write hexarray with offset to pdo\n"); + EC_LOG_RAW(" pdo_write -p [idx] [offset] [hex low...high] Write slave hexarray with offset to pdo\n"); +#ifdef CONFIG_EC_FOE + EC_LOG_RAW(" foe_write -p [idx] [filename] [pwd] [hexdata] Read hexarray via FoE\n"); + EC_LOG_RAW(" foe_read -p [idx] [filename] [pwd] Write hexarray via FoE\n"); +#endif + EC_LOG_RAW(" sii_read -p [idx] Read SII\n"); + EC_LOG_RAW(" wc Show master working counter\n"); +#ifdef CONFIG_EC_PERF_ENABLE + EC_LOG_RAW(" perf -s