update to v0.1.6

Author: dh-04

drivers/baremetal/drv_clk.c

@@ -44,7 +44,7 @@ void system_clock_config(int target_freq_mhz)
     RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
     if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
     {
-      Error_Handler();
+        Error_Handler();
     }
     /** Initializes the CPU, AHB and APB busses clocks
     */
@@ -56,7 +56,7 @@ void system_clock_config(int target_freq_mhz)
 
     if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
     {
-      Error_Handler();
+        Error_Handler();
     }
 }
 

drivers/baremetal/drv_usart.c

@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2019-11-09     xiangxistu   first version
+ * 2020-05-18     chenyaxing   modify stm32_uart_config struct
  */
 
 #include <stm32g0xx.h>
@@ -215,14 +216,15 @@ static long stm32_gpio_clk_enable(GPIO_TypeDef *gpiox)
     return 0;
 }
 
-char * up_char(char * c)
+static int up_char(char * c)
 {
     if ((*c >= 'a') && (*c <= 'z'))
     {
         *c = *c - 32;
     }
     return 0;
 }
+
 static void get_pin_by_name(const char* pin_name, GPIO_TypeDef **port, uint16_t *pin)
 {
     int pin_num = atoi((char*) &pin_name[2]);

drivers/baremetal/uart_config.h

@@ -7,6 +7,7 @@
  * Date           Author       Notes
  * 2018-10-30     SummerGift   first version
  * 2019-01-03     zylx         modify dma support
+ * 2020-05-18     chenyaxing   modify uart_config struct
  */
 
 #ifndef __UART_CONFIG_H__

drivers/nano/drv_clk.c

@@ -43,7 +43,7 @@ void system_clock_config(int target_freq_Mhz)
     RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
     if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
     {
-      Error_Handler();
+        Error_Handler();
     }
     /** Initializes the CPU, AHB and APB busses clocks
     */
@@ -55,7 +55,7 @@ void system_clock_config(int target_freq_Mhz)
 
     if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
     {
-      Error_Handler();
+        Error_Handler();
     }
 }
 

drivers/nano/drv_usart.c

@@ -223,7 +223,7 @@ static rt_err_t stm32_gpio_clk_enable(GPIO_TypeDef *gpiox)
     return RT_EOK;
 }
 
-char * up_char(char * c)
+static int up_char(char * c)
 {
     if ((*c >= 'a') && (*c <= 'z'))
     {

drivers/rtt/drv_clk.c

@@ -42,7 +42,7 @@ void system_clock_config(int target_freq_mhz)
     RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
     if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
     {
-      Error_Handler();
+        Error_Handler();
     }
     /** Initializes the CPU, AHB and APB busses clocks
     */
@@ -54,7 +54,7 @@ void system_clock_config(int target_freq_mhz)
 
     if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
     {
-      Error_Handler();
+        Error_Handler();
     }
 }
 int clock_information(void)

drivers/rtt/drv_usart.c

@@ -331,14 +331,16 @@ static rt_err_t stm32_gpio_clk_enable(GPIO_TypeDef *gpiox)
 
     return RT_EOK;
 }
-char * up_char(char * c)
+
+static int up_char(char * c)
 {
     if ((*c >= 'a') && (*c <= 'z'))
     {
         *c = *c - 32;
     }
     return 0;
 }
+
 static void get_pin_by_name(const char* pin_name, GPIO_TypeDef **port, uint16_t *pin)
 {
     int pin_num = atoi((char*) &pin_name[2]);