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Merge pull request #15 from Rbb666/5.1.0
修复创建芯片工程时排除不必要文件的问题
2 parents 9b4ee12 + 2276309 commit dec6d10

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‎bsp/stm32/libraries/HAL_Drivers/Kconfig‎

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if BSP_USING_USBD
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config BSP_USBD_TYPE_FS
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bool
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# "USB Full Speed (FS) Core"
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config BSP_USBD_TYPE_HS
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bool
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# "USB High Speed (HS) Core"
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config BSP_USBD_SPEED_HS
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bool
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# "USB High Speed (HS) Mode"
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config BSP_USBD_SPEED_HSINFS
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bool
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# "USB High Speed (HS) Core in FS mode"
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config BSP_USBD_PHY_EMBEDDED
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bool
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# "Using Embedded phy interface"
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config BSP_USBD_PHY_UTMI
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bool
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# "UTMI: USB 2.0 Transceiver Macrocell Interace"
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config BSP_USBD_PHY_ULPI
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bool
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# "ULPI: UTMI+ Low Pin Interface"
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endif
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config BSP_USING_CRC
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bool "Enable CRC (CRC-32 0x04C11DB7 Polynomial)"
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select RT_USING_HWCRYPTO
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select RT_HWCRYPTO_USING_CRC
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# "Crypto device frame dose not support above 8-bits granularity"
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# "Reserve progress, running well, about 32-bits granularity, such as stm32f1, stm32f4"
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depends on (SOC_SERIES_STM32L4 || SOC_SERIES_STM32F0 || SOC_SERIES_STM32F7 || SOC_SERIES_STM32H7 || SOC_SERIES_STM32MP1)
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default n
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config BSP_USING_RNG
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bool "Enable RNG (Random Number Generator)"
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select RT_USING_HWCRYPTO
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select RT_HWCRYPTO_USING_RNG
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depends on (SOC_SERIES_STM32L4 || SOC_SERIES_STM32F4 || SOC_SERIES_STM32F7 || \
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SOC_SERIES_STM32H7 || SOC_SERIES_STM32MP1)
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default n
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config BSP_USING_HASH
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bool "Enable HASH (Hash House Harriers)"
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select RT_USING_HWCRYPTO
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select RT_HWCRYPTO_USING_HASH
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depends on (SOC_SERIES_STM32MP1)
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default n
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config BSP_USING_CRYP
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bool "Enable CRYP (Encrypt And Decrypt Data)"
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select RT_USING_HWCRYPTO
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select RT_HWCRYPTO_USING_CRYP
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depends on (SOC_SERIES_STM32MP1)
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default n
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config BSP_USING_UDID
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bool "Enable UDID (Unique Device Identifier)"
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select RT_USING_HWCRYPTO
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default n
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‎bsp/stm32/libraries/HAL_Drivers/config/f0/adc_config.h‎

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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-12-24 zylx first version
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*/
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#ifndef __ADC_CONFIG_H__
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#define __ADC_CONFIG_H__
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#include <rtthread.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef BSP_USING_ADC1
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#ifndef ADC1_CONFIG
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#define ADC1_CONFIG \
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{ \
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.Instance = ADC1, \
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.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1, \
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.Init.Resolution = ADC_RESOLUTION_12B, \
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.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
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.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD, \
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.Init.EOCSelection = ADC_EOC_SINGLE_CONV, \
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.Init.LowPowerAutoWait = DISABLE, \
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.Init.LowPowerAutoPowerOff = DISABLE, \
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.Init.ContinuousConvMode = DISABLE, \
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.Init.DiscontinuousConvMode = ENABLE, \
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.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
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.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
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.Init.DMAContinuousRequests = ENABLE, \
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.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \
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}
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#endif /* ADC1_CONFIG */
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#endif /* BSP_USING_ADC1 */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ADC_CONFIG_H__ */

‎bsp/stm32/libraries/HAL_Drivers/config/f0/dma_config.h‎

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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-01-05 zylx first version
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* 2019-01-08 SummerGift clean up the code
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*/
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#ifndef __DMA_CONFIG_H__
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#define __DMA_CONFIG_H__
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#include <rtthread.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* DMA1 channel1 */
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/* DMA1 channel2-3 DMA2 channel1-2 */
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#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
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#define UART1_DMA_RX_IRQHandler DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
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#define UART1_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#define UART1_RX_DMA_INSTANCE DMA1_Channel3
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#define UART1_RX_DMA_IRQ DMA1_Ch2_3_DMA2_Ch1_2_IRQn
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#elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
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#define SPI1_DMA_RX_TX_IRQHandler DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
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#define SPI1_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#define SPI1_RX_DMA_INSTANCE DMA1_Channel2
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#define SPI1_RX_DMA_IRQ DMA1_Ch2_3_DMA2_Ch1_2_IRQn
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#endif
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#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
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#define SPI1_DMA_RX_TX_IRQHandler DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
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#define SPI1_TX_DMA_RCC RCC_AHBENR_DMA1EN
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#define SPI1_TX_DMA_INSTANCE DMA1_Channel3
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#define SPI1_TX_DMA_IRQ DMA1_Ch2_3_DMA2_Ch1_2_IRQn
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#endif
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/* DMA1 channel2-3 DMA2 channel1-2 */
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/* DMA1 channel4-7 DMA2 channel3-5 */
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#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
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#define UART2_DMA_RX_IRQHandler DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
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#define UART2_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#define UART2_RX_DMA_INSTANCE DMA1_Channel5
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#define UART2_RX_DMA_IRQ DMA1_Ch4_7_DMA2_Ch3_5_IRQn
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#endif
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/* DMA1 channel4-7 DMA2 channel3-5 */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __DMA_CONFIG_H__ */

‎bsp/stm32/libraries/HAL_Drivers/config/f0/pwm_config.h‎

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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-12-24 zylx first version
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* 2023-04-08 Wangyuqiang complete PWM defination
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*/
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#ifndef __PWM_CONFIG_H__
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#define __PWM_CONFIG_H__
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#include <rtthread.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef BSP_USING_PWM1
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#define PWM1_CONFIG \
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{ \
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.tim_handle.Instance = TIM1, \
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.name = "pwm1", \
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.channel = RT_NULL \
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}
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#endif /* BSP_USING_PWM1 */
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#ifdef BSP_USING_PWM2
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#define PWM2_CONFIG \
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{ \
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.tim_handle.Instance = TIM2, \
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.name = "pwm2", \
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.channel = RT_NULL \
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}
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#endif /* BSP_USING_PWM2 */
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#ifdef BSP_USING_PWM3
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#define PWM3_CONFIG \
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{ \
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.tim_handle.Instance = TIM3, \
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.name = "pwm3", \
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.channel = RT_NULL \
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}
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#endif /* BSP_USING_PWM3 */
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#ifdef BSP_USING_PWM4
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#define PWM4_CONFIG \
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{ \
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.tim_handle.Instance = TIM4, \
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.name = "pwm4", \
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.channel = RT_NULL \
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}
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#endif /* BSP_USING_PWM4 */
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#ifdef BSP_USING_PWM5
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#define PWM5_CONFIG \
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{ \
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.tim_handle.Instance = TIM5, \
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.name = "pwm5", \
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.channel = RT_NULL \
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}
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#endif /* BSP_USING_PWM5 */
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#ifdef BSP_USING_PWM6
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#define PWM6_CONFIG \
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{ \
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.tim_handle.Instance = TIM6, \
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.name = "pwm6", \
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.channel = RT_NULL \
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}
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#endif /* BSP_USING_PWM6 */
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#ifdef BSP_USING_PWM7
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#define PWM7_CONFIG \
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{ \
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.tim_handle.Instance = TIM7, \
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.name = "pwm7", \
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.channel = RT_NULL \
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}
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#endif /* BSP_USING_PWM7 */
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#ifdef BSP_USING_PWM8
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#define PWM8_CONFIG \
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{ \
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.tim_handle.Instance = TIM8, \
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.name = "pwm8", \
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.channel = RT_NULL \
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}
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#endif /* BSP_USING_PWM8 */
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#ifdef BSP_USING_PWM9
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#define PWM9_CONFIG \
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{ \
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.tim_handle.Instance = TIM9, \
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.name = "pwm9", \
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.channel = RT_NULL \
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}
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#endif /* BSP_USING_PWM9 */
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#ifdef BSP_USING_PWM10
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#define PWM10_CONFIG \
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{ \
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.tim_handle.Instance = TIM10, \
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.name = "pwm10", \
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.channel = RT_NULL \
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}
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#endif /* BSP_USING_PWM10 */
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#ifdef BSP_USING_PWM11
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#define PWM11_CONFIG \
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{ \
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.tim_handle.Instance = TIM11, \
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.name = "pwm11", \
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.channel = RT_NULL \
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}
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#endif /* BSP_USING_PWM11 */
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#ifdef BSP_USING_PWM12
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#define PWM12_CONFIG \
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{ \
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.tim_handle.Instance = TIM12, \
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.name = "pwm12", \
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.channel = RT_NULL \
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}
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#endif /* BSP_USING_PWM12 */
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#ifdef BSP_USING_PWM13
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#define PWM13_CONFIG \
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{ \
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.tim_handle.Instance = TIM13, \
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.name = "pwm13", \
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.channel = RT_NULL \
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}
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#endif /* BSP_USING_PWM13 */
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#ifdef BSP_USING_PWM14
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#define PWM14_CONFIG \
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{ \
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.tim_handle.Instance = TIM14, \
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.name = "pwm14", \
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.channel = RT_NULL \
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}
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#endif /* BSP_USING_PWM14 */
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#ifdef BSP_USING_PWM15
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#define PWM15_CONFIG \
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{ \
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.tim_handle.Instance = TIM15, \
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.name = "pwm15", \
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.channel = RT_NULL \
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}
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#endif /* BSP_USING_PWM15 */
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#ifdef BSP_USING_PWM16
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#define PWM16_CONFIG \
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{ \
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.tim_handle.Instance = TIM16, \
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.name = "pwm16", \
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.channel = RT_NULL \
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}
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#endif /* BSP_USING_PWM16 */
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#ifdef BSP_USING_PWM17
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#define PWM17_CONFIG \
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{ \
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.tim_handle.Instance = TIM17, \
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.name = "pwm17", \
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.channel = RT_NULL \
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}
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#endif /* BSP_USING_PWM17 */
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#ifdef BSP_USING_PWM18
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#define PWM18_CONFIG \
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{ \
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.tim_handle.Instance = TIM18, \
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.name = "pwm18", \
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.channel = RT_NULL \
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}
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#endif /* BSP_USING_PWM18 */
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#ifdef BSP_USING_PWM19
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#define PWM19_CONFIG \
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{ \
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.tim_handle.Instance = TIM19, \
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.name = "pwm19", \
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.channel = RT_NULL \
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}
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#endif /* BSP_USING_PWM19 */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __PWM_CONFIG_H__ */

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