1616#include "gicv3.h"
1717#include "ioremap.h"
1818
19-
20- /* exception and interrupt handler table */
21- struct rt_irq_desc isr_table [MAX_HANDLERS ];
22-
2319#ifndef RT_USING_SMP
2420/* Those variables will be accessed in ISR, so we need to share them. */
2521rt_ubase_t rt_interrupt_from_thread = 0 ;
2622rt_ubase_t rt_interrupt_to_thread = 0 ;
2723rt_ubase_t rt_thread_switch_interrupt_flag = 0 ;
2824#endif
2925
26+ #ifndef RT_USING_PIC
27+
28+ /* exception and interrupt handler table */
29+ struct rt_irq_desc isr_table [MAX_HANDLERS ];
30+
3031#ifndef RT_CPUS_NR
3132#define RT_CPUS_NR 1
3233#endif
@@ -138,17 +139,17 @@ void rt_hw_interrupt_mask(int vector)
138139#ifdef SOC_BCM283x
139140 if (vector < 32 )
140141 {
141- IRQ_DISABLE1 = (1 << vector );
142+ IRQ_DISABLE1 = (1UL << vector );
142143 }
143144 else if (vector < 64 )
144145 {
145146 vector = vector % 32 ;
146- IRQ_DISABLE2 = (1 << vector );
147+ IRQ_DISABLE2 = (1UL << vector );
147148 }
148149 else
149150 {
150151 vector = vector - 64 ;
151- IRQ_DISABLE_BASIC = (1 << vector );
152+ IRQ_DISABLE_BASIC = (1UL << vector );
152153 }
153154#else
154155 arm_gic_mask (0 , vector );
@@ -164,17 +165,17 @@ void rt_hw_interrupt_umask(int vector)
164165#ifdef SOC_BCM283x
165166if (vector < 32 )
166167 {
167- IRQ_ENABLE1 = (1 << vector );
168+ IRQ_ENABLE1 = (1UL << vector );
168169 }
169170 else if (vector < 64 )
170171 {
171172 vector = vector % 32 ;
172- IRQ_ENABLE2 = (1 << vector );
173+ IRQ_ENABLE2 = (1UL << vector );
173174 }
174175 else
175176 {
176177 vector = vector - 64 ;
177- IRQ_ENABLE_BASIC = (1 << vector );
178+ IRQ_ENABLE_BASIC = (1UL << vector );
178179 }
179180#else
180181 arm_gic_umask (0 , vector );
@@ -416,6 +417,8 @@ void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler)
416417}
417418#endif
418419
420+ #endif /* RT_USING_PIC */
421+
419422#if defined(FINSH_USING_MSH ) && defined(RT_USING_INTERRUPT_INFO )
420423int list_isr ()
421424{
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