[lts 3,1,x] format codes

Author: mysterywolf

bsp/CME_M7/applications/application.c

@@ -28,10 +28,10 @@ int rt_application_init()
 
     tid = rt_thread_create("init",
         rt_init_thread_entry,
-		RT_NULL,
+        RT_NULL,
         2048,
-		RT_THREAD_PRIORITY_MAX/3,
-		20);
+        RT_THREAD_PRIORITY_MAX/3,
+        20);
 
     if (tid != RT_NULL)
         rt_thread_startup(tid);

bsp/CME_M7/applications/startup.c

@@ -1,7 +1,7 @@
 /*
  * File      : startup.c
  * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2014, RT-Thread Develop Team
+ * COPYRIGHT (C) 2006-2021, RT-Thread Develop Team
  *
  * The license and distribution terms for this file may be
  * found in the file LICENSE in this distribution or at

bsp/CME_M7/drivers/board.h

@@ -14,7 +14,7 @@
 #include "cmem7_includes.h"
 //#include "cmem7_retarget.h"
 
-#define SRAM_SIZE         64	// KB
+#define SRAM_SIZE         64    // KB
 #define SRAM_END          (0x20000000 + SRAM_SIZE * 1024)
 
 //#define RT_USING_UART0

bsp/CME_M7/drivers/emac.c

@@ -1,7 +1,7 @@
 /*
  * File      : emac.c
  * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2014, RT-Thread Develop Team
+ * COPYRIGHT (C) 2006-2021, RT-Thread Develop Team
  *
  * The license and distribution terms for this file may be
  * found in the file LICENSE in this distribution or at
@@ -38,7 +38,7 @@ struct rt_cme_eth
     struct eth_device parent;
 
     /* interface address info. */
-    rt_uint8_t  dev_addr[MAX_ADDR_LEN];			/* hw address	*/
+    rt_uint8_t  dev_addr[MAX_ADDR_LEN];         /* hw address   */
 
     uint32_t    ETH_Speed;
     uint32_t    ETH_Mode;
@@ -95,8 +95,8 @@ uint32_t txTotalMemory = 0x2000;
 BOOL isRxNoBuf = FALSE;
 
 #define ETH_MAX_PACKET_SIZE    1520    /* ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */
-#define ETH_RXBUFNB        	4
-#define ETH_TXBUFNB        	2
+#define ETH_RXBUFNB         4
+#define ETH_TXBUFNB         2
 
 struct eth_rx_buffer
 {

bsp/CME_M7/rtconfig.h

@@ -3,16 +3,16 @@
 #define __RTTHREAD_CFG_H__
 
 /* RT_NAME_MAX*/
-#define RT_NAME_MAX		8
+#define RT_NAME_MAX     8
 
 /* RT_ALIGN_SIZE*/
-#define RT_ALIGN_SIZE	4
+#define RT_ALIGN_SIZE   4
 
 /* PRIORITY_MAX */
-#define RT_THREAD_PRIORITY_MAX	32
+#define RT_THREAD_PRIORITY_MAX  32
 
 /* Tick per Second */
-#define RT_TICK_PER_SECOND	100
+#define RT_TICK_PER_SECOND  100
 
 /* SECTION: RT_DEBUG */
 /* Thread Debug */
@@ -61,8 +61,8 @@
 /* SECTION: Console options */
 #define RT_USING_CONSOLE
 /* the buffer size of console*/
-#define RT_CONSOLEBUF_SIZE	128
-#define RT_CONSOLE_DEVICE_NAME	        "uart2"
+#define RT_CONSOLEBUF_SIZE  128
+#define RT_CONSOLE_DEVICE_NAME          "uart2"
 
 /* SECTION: finsh, a C-Express shell */
 #define RT_USING_FINSH
@@ -79,15 +79,15 @@
 #define RT_USING_DFS_ELMFAT
 #define RT_DFS_ELM_REENTRANT
 #define RT_DFS_ELM_WORD_ACCESS
-#define RT_DFS_ELM_DRIVES			1
-#define RT_DFS_ELM_USE_LFN			2
-#define RT_DFS_ELM_MAX_LFN			255
+#define RT_DFS_ELM_DRIVES           1
+#define RT_DFS_ELM_USE_LFN          2
+#define RT_DFS_ELM_MAX_LFN          255
 #define RT_DFS_ELM_MAX_SECTOR_SIZE  512
 
 /* the max number of mounted filesystem */
-#define DFS_FILESYSTEMS_MAX			2
-/* the max number of opened files 		*/
-#define DFS_FD_MAX					4
+#define DFS_FILESYSTEMS_MAX         2
+/* the max number of opened files       */
+#define DFS_FD_MAX                  4
 
 /* SECTION: lwip, a lighwight TCP/IP protocol stack */
 #define RT_USING_LWIP
@@ -121,13 +121,13 @@
 #define RT_LWIP_MSKADDR  "255.255.255.0"
 
 /* tcp thread options */
-#define RT_LWIP_TCPTHREAD_PRIORITY		12
-#define RT_LWIP_TCPTHREAD_MBOX_SIZE		4
-#define RT_LWIP_TCPTHREAD_STACKSIZE		1024
+#define RT_LWIP_TCPTHREAD_PRIORITY      12
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE     4
+#define RT_LWIP_TCPTHREAD_STACKSIZE     1024
 
-#define RT_LWIP_ETHTHREAD_PRIORITY		15
-#define RT_LWIP_ETHTHREAD_MBOX_SIZE		4
-#define RT_LWIP_ETHTHREAD_STACKSIZE		512
+#define RT_LWIP_ETHTHREAD_PRIORITY      15
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE     4
+#define RT_LWIP_ETHTHREAD_STACKSIZE     512
 
 // <bool name="RT_USING_CMSIS_OS" description="Using CMSIS OS API" default="true" />
 // #define RT_USING_CMSIS_OS

bsp/allwinner_tina/drivers/drv_clock.c

@@ -527,7 +527,7 @@ rt_err_t mmc_set_clk(enum mmc_clk_id clk_id, int hz)
         *mmc_clk &= ~(0x1 << 31);
         return RT_EOK;
     }
-    
+
     if (hz <= 24000000)
     {
         pll = (0x0 << 24);
@@ -579,7 +579,7 @@ rt_err_t mmc_set_clk(enum mmc_clk_id clk_id, int hz)
         oclk_dly = 1;
         sclk_dly = 4;
     }
-    
+
     *mmc_clk = (0x1 << 31) | pll | (sclk_dly << 20) | \
            (n << 16) | (oclk_dly << 8) | (div - 1);
 

bsp/allwinner_tina/drivers/drv_clock.h

@@ -238,4 +238,4 @@ rt_err_t dram_gate_clk_enable(enum dram_gate dram_gate);
 rt_err_t dram_gate_clk_disable(enum dram_gate dram_gate);
 
 rt_err_t mmc_set_clk(enum mmc_clk_id clk_id, int hz);
-#endif
+#endif

bsp/allwinner_tina/drivers/drv_gpio.h

@@ -227,4 +227,4 @@ void gpio_set_debounce(enum gpio_port port, rt_uint8_t prescaler);
 void gpio_set_irq_callback(enum gpio_port port, enum gpio_pin pin, void (*irq_cb)(void *), void *irq_arg);
 int rt_hw_gpio_init(void);
 
-#endif /* __DRV_GPIO_H__ */
+#endif /* __DRV_GPIO_H__ */

bsp/allwinner_tina/drivers/drv_sdio.c

@@ -20,10 +20,10 @@
 
 
 #define DBG_TAG  "MMC"
-// #define DBG_LVL DBG_LOG    
-// #define DBG_LVL DBG_INFO   
+// #define DBG_LVL DBG_LOG
+// #define DBG_LVL DBG_INFO
 #define DBG_LVL DBG_WARNING
-// #define DBG_LVL DBG_ERROR  
+// #define DBG_LVL DBG_ERROR
 #include <rtdbg.h>
 
 #ifdef RT_USING_SDIO
@@ -33,12 +33,12 @@
 struct mmc_xfe_des
 {
     rt_uint32_t size;    /* block size  */
-	rt_uint32_t num;     /* block num   */
-	rt_uint8_t *buff;    /* buff addr   */
-	rt_uint32_t flag;    /* write or read or stream */
-#define MMC_DATA_WRITE	(1 << 0)
-#define MMC_DATA_READ	(1 << 1)
-#define MMC_DATA_STREAM	(1 << 2)
+    rt_uint32_t num;     /* block num   */
+    rt_uint8_t *buff;    /* buff addr   */
+    rt_uint32_t flag;    /* write or read or stream */
+#define MMC_DATA_WRITE  (1 << 0)
+#define MMC_DATA_READ   (1 << 1)
+#define MMC_DATA_STREAM (1 << 2)
 };
 
 struct mmc_flag
@@ -57,7 +57,7 @@ struct sdio_drv
     tina_mmc_t mmc_des;
     rt_uint8_t *mmc_buf;
     rt_uint8_t usedma;
-    
+
 };
 
 #ifdef CONFIG_MMC_USE_DMA
@@ -122,7 +122,7 @@ static int mmc_update_clk(tina_mmc_t mmc)
     mmc->risr_reg = mmc->risr_reg;
     return RT_EOK;
 }
-    
+
 static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
 {
     ALIGN(32) static struct mmc_des_v4p1 pdes[128];  // mast ALIGN(32)
@@ -131,7 +131,7 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
     unsigned length = xfe->size * xfe->num;
     unsigned buff_frag_num = length >> SDXC_DES_NUM_SHIFT;
     unsigned remain = length & (SDXC_DES_BUFFER_MAX_LEN - 1);
-    
+
     if (remain)
     {
         buff_frag_num ++;
@@ -142,7 +142,7 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
     }
     memset(pdes, 0, sizeof(pdes));
     mmu_clean_dcache((rt_uint32_t)(xfe->buff), length);
-    for (i = 0, des_idx = 0; i < buff_frag_num; i++, des_idx++) 
+    for (i = 0, des_idx = 0; i < buff_frag_num; i++, des_idx++)
     {
         // memset((void*)&pdes[des_idx], 0, sizeof(struct mmc_v4p1));
         pdes[des_idx].des_chain = 1;
@@ -168,8 +168,8 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
             pdes[des_idx].last_des = 1;
             pdes[des_idx].end_of_ring = 1;
             pdes[des_idx].buf_addr_ptr2 = 0;
-        } 
-        else 
+        }
+        else
         {
             pdes[des_idx].buf_addr_ptr2 = (unsigned long)&pdes[des_idx+1];
         }
@@ -203,7 +203,7 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
     mmc->dmac_reg = (1 << 1) | (1 << 7);        /* idma on              */
     rval = mmc->idie_reg & (~3);
     if (xfe->flag == MMC_DATA_WRITE)
-        rval |= (1 << 0);        
+        rval |= (1 << 0);
     else
         rval |= (1 << 1);
     mmc->idie_reg = rval;
@@ -222,7 +222,7 @@ static rt_err_t mmc_trans_data_by_cpu(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
 
     if (xfe->flag == MMC_DATA_WRITE)
     {
-        for (i = 0; i < (byte_cnt >> 2); i++) 
+        for (i = 0; i < (byte_cnt >> 2); i++)
         {
             while(--timeout && (mmc->star_reg & (1 << 3)));
 
@@ -237,7 +237,7 @@ static rt_err_t mmc_trans_data_by_cpu(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
     }
     else
     {
-        for (i = 0; i < (byte_cnt >> 2); i++) 
+        for (i = 0; i < (byte_cnt >> 2); i++)
         {
             while(--timeout && (mmc->star_reg & (1 << 2)));
 
@@ -276,7 +276,7 @@ static rt_err_t mmc_config_clock(tina_mmc_t mmc, int clk)
     {
         mmc_set_clk(SDMMC1, clk);
     }
-    
+
     /* Re-enable card clock */
     rval = mmc->ckcr_reg;
     rval |=  (0x1 << 16); //(3 << 16);
@@ -369,7 +369,7 @@ static int mmc_send_cmd(struct rt_mmcsd_host *host, struct rt_mmcsd_cmd *cmd)
         cmdval |= (1 << 7);
     if ((resp_type(cmd) != RESP_R3) && (resp_type(cmd) != RESP_R4))
         cmdval |= (1 << 8);
-    
+
     if (data)
     {
         cmdval |= (1 << 9) | (1 << 13);
@@ -592,7 +592,7 @@ static void sdio_request_send(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r
 
     memset(&sdio->flag, 0, sizeof(struct mmc_flag));
     mmc_send_cmd(host, req->cmd);
-    
+
     return;
 }
 

bsp/allwinner_tina/drivers/drv_sdio.h

@@ -119,8 +119,8 @@ REG[31]  : Load cmd
 #define SDXC_UPDATE_CLOCK_CMD    BIT(21)
 #define SDXC_LOAD_CMD            BIT(31)
 
-/* 
-    SD status reg 
+/*
+    SD status reg
 REG[0]   : FIFO_RX_LEVEL
 REG[1]   : FIFO_TX_LEVEL
 REG[2]   : FIFO_EMPTY
@@ -129,7 +129,7 @@ REG[4-7] : FSM_STA
 REG[8]   : CARD_PRESENT
 REG[9]   : CARD_BUSY
 REG[10]  : FSM_BUSY
-REG[11-16]: RESP_IDX 
+REG[11-16]: RESP_IDX
 REG[17-21]: FIFO_LEVEL
 REG[31]   : DMA_REQ
 */