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BernardXiongBernardXiong
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Merge pull request #3227 from armink/fix_drivers
[bsp/stm32] Add DMAMUX support for stm32l4+.
2 parents a687065 + f1e5883 commit 0dc7da6

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‎bsp/stm32/libraries/HAL_Drivers/config/l4/dma_config.h‎

Lines changed: 69 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@
77
* Date Author Notes
88
* 2019-01-05 zylx first version
99
* 2019-01-08 SummerGift clean up the code
10+
* 2019-12-01 armink add DMAMUX support
1011
*/
1112

1213
#ifndef __DMA_CONFIG_H__
@@ -25,7 +26,11 @@ extern "C" {
2526
#define SPI1_DMA_RX_IRQHandler DMA1_Channel2_IRQHandler
2627
#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
2728
#define SPI1_RX_DMA_INSTANCE DMA1_Channel2
29+
#if defined(DMAMUX1) /* for L4+ */
30+
#define SPI1_RX_DMA_REQUEST DMA_REQUEST_SPI1_RX
31+
#else /* for L4 */
2832
#define SPI1_RX_DMA_REQUEST DMA_REQUEST_1
33+
#endif /* DMAMUX1 */
2934
#define SPI1_RX_DMA_IRQ DMA1_Channel2_IRQn
3035
#endif
3136

@@ -34,13 +39,21 @@ extern "C" {
3439
#define SPI1_DMA_TX_IRQHandler DMA1_Channel3_IRQHandler
3540
#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
3641
#define SPI1_TX_DMA_INSTANCE DMA1_Channel3
42+
#if defined(DMAMUX1) /* for L4+ */
43+
#define SPI1_TX_DMA_REQUEST DMA_REQUEST_SPI1_TX
44+
#else /* for L4 */
3745
#define SPI1_TX_DMA_REQUEST DMA_REQUEST_1
46+
#endif /* DMAMUX1 */
3847
#define SPI1_TX_DMA_IRQ DMA1_Channel3_IRQn
3948
#elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
4049
#define UART3_DMA_RX_IRQHandler DMA1_Channel3_IRQHandler
4150
#define UART3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
4251
#define UART3_RX_DMA_INSTANCE DMA1_Channel3
52+
#if defined(DMAMUX1) /* for L4+ */
53+
#define UART3_RX_DMA_REQUEST DMA_REQUEST_USART3_RX
54+
#else /* for L4 */
4355
#define UART3_RX_DMA_REQUEST DMA_REQUEST_2
56+
#endif /* DMAMUX1 */
4457
#define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn
4558
#endif
4659

@@ -49,13 +62,21 @@ extern "C" {
4962
#define UART1_DMA_TX_IRQHandler DMA1_Channel4_IRQHandler
5063
#define UART1_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
5164
#define UART1_TX_DMA_INSTANCE DMA1_Channel4
65+
#if defined(DMAMUX1) /* for L4+ */
66+
#define UART1_TX_DMA_REQUEST DMA_REQUEST_USART1_TX
67+
#else /* for L4 */
5268
#define UART1_TX_DMA_REQUEST DMA_REQUEST_2
69+
#endif /* DMAMUX1 */
5370
#define UART1_TX_DMA_IRQ DMA1_Channel4_IRQn
5471
#elif defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
5572
#define SPI2_DMA_RX_IRQHandler DMA1_Channel4_IRQHandler
5673
#define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
5774
#define SPI2_RX_DMA_INSTANCE DMA1_Channel4
75+
#if defined(DMAMUX1) /* for L4+ */
76+
#define SPI2_RX_DMA_REQUEST DMA_REQUEST_SPI2_RX
77+
#else /* for L4 */
5878
#define SPI2_RX_DMA_REQUEST DMA_REQUEST_1
79+
#endif /* DMAMUX1 */
5980
#define SPI2_RX_DMA_IRQ DMA1_Channel4_IRQn
6081
#endif
6182

@@ -64,19 +85,31 @@ extern "C" {
6485
#define UART1_DMA_RX_IRQHandler DMA1_Channel5_IRQHandler
6586
#define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
6687
#define UART1_RX_DMA_INSTANCE DMA1_Channel5
88+
#if defined(DMAMUX1) /* for L4+ */
89+
#define UART1_RX_DMA_REQUEST DMA_REQUEST_USART1_RX
90+
#else /* for L4 */
6791
#define UART1_RX_DMA_REQUEST DMA_REQUEST_2
92+
#endif /* DMAMUX1 */
6893
#define UART1_RX_DMA_IRQ DMA1_Channel5_IRQn
6994
#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
7095
#define QSPI_DMA_IRQHandler DMA1_Channel5_IRQHandler
7196
#define QSPI_DMA_RCC RCC_AHB1ENR_DMA1EN
7297
#define QSPI_DMA_INSTANCE DMA1_Channel5
98+
#if defined(DMAMUX1) /* for L4+ */
99+
#define QSPI_DMA_REQUEST DMA_REQUEST_OCTOSPI1
100+
#else /* for L4 */
73101
#define QSPI_DMA_REQUEST DMA_REQUEST_5
102+
#endif /* DMAMUX1 */
74103
#define QSPI_DMA_IRQ DMA1_Channel5_IRQn
75104
#elif defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
76105
#define SPI2_DMA_TX_IRQHandler DMA1_Channel5_IRQHandler
77106
#define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
78107
#define SPI2_TX_DMA_INSTANCE DMA1_Channel5
108+
#if defined(DMAMUX1) /* for L4+ */
109+
#define SPI2_TX_DMA_REQUEST DMA_REQUEST_SPI2_TX
110+
#else /* for L4 */
79111
#define SPI2_TX_DMA_REQUEST DMA_REQUEST_1
112+
#endif /* DMAMUX1 */
80113
#define SPI2_TX_DMA_IRQ DMA1_Channel5_IRQn
81114
#endif
82115

@@ -85,7 +118,11 @@ extern "C" {
85118
#define UART2_DMA_RX_IRQHandler DMA1_Channel6_IRQHandler
86119
#define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
87120
#define UART2_RX_DMA_INSTANCE DMA1_Channel6
121+
#if defined(DMAMUX1) /* for L4+ */
122+
#define UART2_RX_DMA_REQUEST DMA_REQUEST_USART2_RX
123+
#else /* for L4 */
88124
#define UART2_RX_DMA_REQUEST DMA_REQUEST_2
125+
#endif /* DMAMUX1 */
89126
#define UART2_RX_DMA_IRQ DMA1_Channel6_IRQn
90127
#endif
91128

@@ -96,7 +133,11 @@ extern "C" {
96133
#define UART5_DMA_TX_IRQHandler DMA2_Channel1_IRQHandler
97134
#define UART5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
98135
#define UART5_TX_DMA_INSTANCE DMA2_Channel1
136+
#if defined(DMAMUX1) /* for L4+ */
137+
#define UART5_TX_DMA_REQUEST DMA_REQUEST_UART5_TX
138+
#else /* for L4 */
99139
#define UART5_TX_DMA_REQUEST DMA_REQUEST_2
140+
#endif /* DMAMUX1 */
100141
#define UART5_TX_DMA_IRQ DMA2_Channel1_IRQn
101142
#endif
102143

@@ -105,7 +146,11 @@ extern "C" {
105146
#define UART5_DMA_RX_IRQHandler DMA2_Channel2_IRQHandler
106147
#define UART5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
107148
#define UART5_RX_DMA_INSTANCE DMA2_Channel2
149+
#if defined(DMAMUX1) /* for L4+ */
150+
#define UART5_RX_DMA_REQUEST DMA_REQUEST_UART5_RX
151+
#else /* for L4 */
108152
#define UART5_RX_DMA_REQUEST DMA_REQUEST_2
153+
#endif /* DMAMUX1 */
109154
#define UART5_RX_DMA_IRQ DMA2_Channel2_IRQn
110155
#endif
111156

@@ -114,7 +159,11 @@ extern "C" {
114159
#define SPI1_DMA_RX_IRQHandler DMA2_Channel3_IRQHandler
115160
#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
116161
#define SPI1_RX_DMA_INSTANCE DMA2_Channel3
162+
#if defined(DMAMUX1) /* for L4+ */
163+
#define SPI1_RX_DMA_REQUEST DMA_REQUEST_SPI1_RX
164+
#else /* for L4 */
117165
#define SPI1_RX_DMA_REQUEST DMA_REQUEST_4
166+
#endif /* DMAMUX1 */
118167
#define SPI1_RX_DMA_IRQ DMA2_Channel3_IRQn
119168
#endif
120169

@@ -123,7 +172,11 @@ extern "C" {
123172
#define SPI1_DMA_TX_IRQHandler DMA2_Channel4_IRQHandler
124173
#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
125174
#define SPI1_TX_DMA_INSTANCE DMA2_Channel4
175+
#if defined(DMAMUX1) /* for L4+ */
176+
#define SPI1_TX_DMA_REQUEST DMA_REQUEST_SPI1_TX
177+
#else /* for L4 */
126178
#define SPI1_TX_DMA_REQUEST DMA_REQUEST_4
179+
#endif /* DMAMUX1 */
127180
#define SPI1_TX_DMA_IRQ DMA2_Channel4_IRQn
128181
#endif
129182

@@ -134,7 +187,11 @@ extern "C" {
134187
#define UART1_DMA_TX_IRQHandler DMA2_Channel6_IRQHandler
135188
#define UART1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
136189
#define UART1_TX_DMA_INSTANCE DMA2_Channel6
190+
#if defined(DMAMUX1) /* for L4+ */
191+
#define UART1_TX_DMA_REQUEST DMA_REQUEST_USART1_TX
192+
#else /* for L4 */
137193
#define UART1_TX_DMA_REQUEST DMA_REQUEST_2
194+
#endif /* DMAMUX1 */
138195
#define UART1_TX_DMA_IRQ DMA2_Channel6_IRQn
139196
#endif
140197

@@ -143,19 +200,31 @@ extern "C" {
143200
#define UART1_DMA_RX_IRQHandler DMA2_Channel7_IRQHandler
144201
#define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
145202
#define UART1_RX_DMA_INSTANCE DMA2_Channel7
203+
#if defined(DMAMUX1) /* for L4+ */
204+
#define UART1_RX_DMA_REQUEST DMA_REQUEST_USART1_RX
205+
#else /* for L4 */
146206
#define UART1_RX_DMA_REQUEST DMA_REQUEST_2
207+
#endif /* DMAMUX1 */
147208
#define UART1_RX_DMA_IRQ DMA2_Channel7_IRQn
148209
#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
149210
#define QSPI_DMA_IRQHandler DMA2_Channel7_IRQHandler
150211
#define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN
151212
#define QSPI_DMA_INSTANCE DMA2_Channel7
213+
#if defined(DMAMUX1) /* for L4+ */
214+
#define QSPI_DMA_REQUEST DMA_REQUEST_OCTOSPI1
215+
#else /* for L4 */
152216
#define QSPI_DMA_REQUEST DMA_REQUEST_3
217+
#endif /* DMAMUX1 */
153218
#define QSPI_DMA_IRQ DMA2_Channel7_IRQn
154219
#elif defined(BSP_LPUART1_RX_USING_DMA) && !defined(LPUART1_RX_DMA_INSTANCE)
155220
#define LPUART1_DMA_RX_IRQHandler DMA2_Channel7_IRQHandler
156221
#define LPUART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
157222
#define LPUART1_RX_DMA_INSTANCE DMA2_Channel7
223+
#if defined(DMAMUX1) /* for L4+ */
224+
#define LPUART1_RX_DMA_REQUEST DMA_REQUEST_LPUART1_RX
225+
#else /* for L4 */
158226
#define LPUART1_RX_DMA_REQUEST DMA_REQUEST_4
227+
#endif /* DMAMUX1 */
159228
#define LPUART1_RX_DMA_IRQ DMA2_Channel7_IRQn
160229
#endif
161230

‎bsp/stm32/libraries/HAL_Drivers/drv_usart.c‎

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@
2222
!defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && \
2323
!defined(BSP_USING_UART7) && !defined(BSP_USING_UART8) && !defined(BSP_USING_LPUART1)
2424
#error "Please define at least one BSP_USING_UARTx"
25-
/* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */
25+
/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
2626
#endif
2727

2828
#ifdef RT_SERIAL_USING_DMA
@@ -749,6 +749,12 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
749749
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
750750
SET_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
751751
tmpreg = READ_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
752+
753+
#if (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G4)) && defined(DMAMUX1)
754+
/* enable DMAMUX clock for L4+ and G4 */
755+
__HAL_RCC_DMAMUX1_CLK_ENABLE();
756+
#endif
757+
752758
#endif
753759
UNUSED(tmpreg); /* To avoid compiler warnings */
754760
}

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