@@ -132,12 +132,12 @@ extern "C" {
132132#define SPI1_RX_DMA_INSTANCE DMA2_Stream2
133133#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3
134134#define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn
135- #elif defined(BSP_UART1_RX_USING_DMA ) && !defined(USART1_RX_DMA_INSTANCE )
136- #define USART1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
137- #define USART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
138- #define USART1_RX_DMA_INSTANCE DMA2_Stream2
139- #define USART1_RX_DMA_CHANNEL DMA_CHANNEL_4
140- #define USART1_RX_DMA_IRQ DMA2_Stream2_IRQn
135+ #elif defined(BSP_UART1_RX_USING_DMA ) && !defined(UART1_RX_DMA_INSTANCE )
136+ #define UART1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
137+ #define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
138+ #define UART1_RX_DMA_INSTANCE DMA2_Stream2
139+ #define UART1_RX_DMA_CHANNEL DMA_CHANNEL_4
140+ #define UART1_RX_DMA_IRQ DMA2_Stream2_IRQn
141141#endif
142142
143143/* DMA2 stream3 */
@@ -184,12 +184,12 @@ extern "C" {
184184#define SPI1_TX_DMA_INSTANCE DMA2_Stream5
185185#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3
186186#define SPI1_TX_DMA_IRQ DMA2_Stream5_IRQn
187- #elif defined(BSP_UART1_RX_USING_DMA ) && !defined(USART1_RX_DMA_INSTANCE )
188- #define USART1_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler
189- #define USART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
190- #define USART1_RX_DMA_INSTANCE DMA2_Stream5
191- #define USART1_RX_DMA_CHANNEL DMA_CHANNEL_4
192- #define USART1_RX_DMA_IRQ DMA2_Stream5_IRQn
187+ #elif defined(BSP_UART1_RX_USING_DMA ) && !defined(UART1_RX_DMA_INSTANCE )
188+ #define UART1_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler
189+ #define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
190+ #define UART1_RX_DMA_INSTANCE DMA2_Stream5
191+ #define UART1_RX_DMA_CHANNEL DMA_CHANNEL_4
192+ #define UART1_RX_DMA_IRQ DMA2_Stream5_IRQn
193193#elif defined(BSP_SPI5_RX_USING_DMA ) && !defined(SPI5_RX_DMA_INSTANCE )
194194#define SPI5_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler
195195#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
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