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author
shaojinchun
committed
arm926内容整理
1 parent 377bbdc commit 159def7

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8 files changed

+420
-361
lines changed

8 files changed

+420
-361
lines changed

‎libcpu/arm/arm926/context_gcc.S‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@
1010

1111
#define NOINT 0xC0
1212

13+
.text
1314
;/*
1415
; * rt_base_t rt_hw_interrupt_disable();
1516
; */

‎libcpu/arm/arm926/cpuport.c‎

Lines changed: 15 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -23,30 +23,30 @@ rt_inline rt_uint32_t cp15_rd(void)
2323
{
2424
rt_uint32_t i;
2525

26-
__asm volatile("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
26+
__asm volatile("mrc p15, 0, %0, c1, c0, 0":"=r"(i));
2727
return i;
2828
}
2929

3030
rt_inline void cache_enable(rt_uint32_t bit)
3131
{
3232
__asm volatile(\
33-
"mrc p15,0,r0,c1,c0,0\n\t" \
34-
"orr r0,r0,%0\n\t" \
35-
"mcr p15,0,r0,c1,c0,0" \
36-
: \
37-
:"r" (bit) \
38-
:"memory");
33+
"mrc p15,0,r0,c1,c0,0\n\t" \
34+
"orr r0,r0,%0\n\t" \
35+
"mcr p15,0,r0,c1,c0,0" \
36+
: \
37+
: "r"(bit) \
38+
: "memory");
3939
}
4040

4141
rt_inline void cache_disable(rt_uint32_t bit)
4242
{
4343
__asm volatile(\
44-
"mrc p15,0,r0,c1,c0,0\n\t" \
45-
"bic r0,r0,%0\n\t" \
46-
"mcr p15,0,r0,c1,c0,0" \
47-
: \
48-
:"r" (bit) \
49-
:"memory");
44+
"mrc p15,0,r0,c1,c0,0\n\t" \
45+
"bic r0,r0,%0\n\t" \
46+
"mcr p15,0,r0,c1,c0,0" \
47+
: \
48+
: "r"(bit) \
49+
: "memory");
5050
}
5151
#endif
5252

@@ -152,7 +152,7 @@ void rt_hw_cpu_reset()
152152
rt_kprintf("Restarting system...\n");
153153
machine_reset();
154154

155-
while(1); /* loop forever and wait for reset to happen */
155+
while (1); /* loop forever and wait for reset to happen */
156156

157157
/* NEVER REACHED */
158158
}
@@ -206,21 +206,7 @@ int __rt_ffs(int value)
206206
#elif defined(__GNUC__) || defined(__ICCARM__)
207207
int __rt_ffs(int value)
208208
{
209-
register rt_uint32_t x;
210-
211-
if (value == 0)
212-
return value;
213-
214-
__asm
215-
(
216-
"rsb %[temp], %[val], #0\n"
217-
"and %[temp], %[temp], %[val]\n"
218-
"clz %[temp], %[temp]\n"
219-
"rsb %[temp], %[temp], #32\n"
220-
:[temp] "=r"(x)
221-
:[val] "r"(value)
222-
);
223-
return x;
209+
return __builtin_ffs(value);
224210
}
225211
#endif
226212

‎libcpu/arm/arm926/machine.c‎

Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,41 @@
1+
/*
2+
* File : cpu.c
3+
* This file is part of RT-Thread RTOS
4+
* COPYRIGHT (C) 2017, RT-Thread Development Team
5+
*
6+
* This program is free software; you can redistribute it and/or modify
7+
* it under the terms of the GNU General Public License as published by
8+
* the Free Software Foundation; either version 2 of the License, or
9+
* (at your option) any later version.
10+
*
11+
* This program is distributed in the hope that it will be useful,
12+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
13+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14+
* GNU General Public License for more details.
15+
*
16+
* You should have received a copy of the GNU General Public License along
17+
* with this program; if not, write to the Free Software Foundation, Inc.,
18+
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19+
*
20+
* Change Logs:
21+
* Date Author Notes
22+
* 2018-02-08 RT-Thread the first version
23+
*/
24+
25+
#include <rthw.h>
26+
#include <rtthread.h>
27+
28+
RT_WEAK void machine_reset(void)
29+
{
30+
rt_kprintf("reboot system...\n");
31+
rt_hw_interrupt_disable();
32+
while (1);
33+
}
34+
35+
RT_WEAK void machine_shutdown(void)
36+
{
37+
rt_kprintf("shutdown...\n");
38+
rt_hw_interrupt_disable();
39+
while (1);
40+
}
41+

‎libcpu/arm/arm926/mmu.c‎

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -140,7 +140,7 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
140140

141141
ptr = buffer & ~(CACHE_LINE_SIZE - 1);
142142

143-
while(ptr < buffer + size)
143+
while (ptr < buffer + size)
144144
{
145145
__asm volatile { MCR p15, 0, ptr, c7, c14, 1 }
146146
ptr += CACHE_LINE_SIZE;
@@ -211,18 +211,18 @@ void mmu_setttbase(register rt_uint32_t i)
211211
* set by page table entry
212212
*/
213213
value = 0;
214-
asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
214+
asm volatile("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
215215

216216
value = 0x55555555;
217-
asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
217+
asm volatile("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
218218

219-
asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i));
219+
asm volatile("mcr p15, 0, %0, c2, c0, 0"::"r"(i));
220220

221221
}
222222

223223
void mmu_set_domain(register rt_uint32_t i)
224224
{
225-
asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i));
225+
asm volatile("mcr p15,0, %0, c3, c0, 0": :"r"(i));
226226
}
227227

228228
void mmu_enable()
@@ -321,7 +321,7 @@ void mmu_disable_alignfault()
321321

322322
void mmu_clean_invalidated_cache_index(int index)
323323
{
324-
asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
324+
asm volatile("mcr p15, 0, %0, c7, c14, 2": :"r"(index));
325325
}
326326

327327
void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
@@ -330,9 +330,9 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
330330

331331
ptr = buffer & ~(CACHE_LINE_SIZE - 1);
332332

333-
while(ptr < buffer + size)
333+
while (ptr < buffer + size)
334334
{
335-
asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr));
335+
asm volatile("mcr p15, 0, %0, c7, c14, 1": :"r"(ptr));
336336

337337
ptr += CACHE_LINE_SIZE;
338338
}
@@ -347,7 +347,7 @@ void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
347347

348348
while (ptr < buffer + size)
349349
{
350-
asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
350+
asm volatile("mcr p15, 0, %0, c7, c10, 1": :"r"(ptr));
351351

352352
ptr += CACHE_LINE_SIZE;
353353
}
@@ -361,38 +361,38 @@ void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
361361

362362
while (ptr < buffer + size)
363363
{
364-
asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
364+
asm volatile("mcr p15, 0, %0, c7, c6, 1": :"r"(ptr));
365365

366366
ptr += CACHE_LINE_SIZE;
367367
}
368368
}
369369

370370
void mmu_invalidate_tlb()
371371
{
372-
asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
372+
asm volatile("mcr p15, 0, %0, c8, c7, 0": :"r"(0));
373373

374374
}
375375

376376
void mmu_invalidate_icache()
377377
{
378-
asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
378+
asm volatile("mcr p15, 0, %0, c7, c5, 0": :"r"(0));
379379

380380
}
381381

382382
void mmu_invalidate_dcache_all()
383383
{
384-
asm volatile ("mcr p15, 0, %0, c7, c6, 0": :"r" (0));
384+
asm volatile("mcr p15, 0, %0, c7, c6, 0": :"r"(0));
385385

386386
}
387387
#endif
388388

389389
/* level1 page table */
390390
#if defined(__ICCARM__)
391391
#pragma data_alignment=(16*1024)
392-
static volatile rt_uint32_t _page_table[4*1024];
392+
static volatile rt_uint32_t _page_table[4 * 1024];
393393
#else
394-
static volatile rt_uint32_t _page_table[4*1024] \
395-
__attribute__((aligned(16*1024)));
394+
static volatile rt_uint32_t _page_table[4 * 1024] \
395+
__attribute__((aligned(16 * 1024)));
396396
#endif
397397

398398
void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd,
@@ -401,11 +401,11 @@ void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd,
401401
volatile rt_uint32_t *pTT;
402402
volatile int nSec;
403403
int i = 0;
404-
pTT=(rt_uint32_t *)_page_table+(vaddrStart>>20);
405-
nSec=(vaddrEnd>>20)-(vaddrStart>>20);
406-
for(i=0; i<=nSec; i++)
404+
pTT = (rt_uint32_t *)_page_table + (vaddrStart >> 20);
405+
nSec = (vaddrEnd >> 20) - (vaddrStart >> 20);
406+
for (i = 0; i <= nSec; i++)
407407
{
408-
*pTT = attr |(((paddrStart>>20)+i)<<20);
408+
*pTT = attr | (((paddrStart >> 20) + i) << 20);
409409
pTT++;
410410
}
411411
}

‎libcpu/arm/arm926/mmu.h‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,7 @@
55
*
66
* Change Logs:
77
* Date Author Notes
8+
* 2018-02-08 RT-Thread the first version
89
*/
910

1011
#ifndef __MMU_H__
@@ -45,5 +46,7 @@ struct mem_desc
4546
};
4647

4748
void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size);
48-
49+
void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size);
50+
void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size);
51+
void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size);
4952
#endif

‎libcpu/arm/arm926/stack.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
3838

3939
stack_addr += sizeof(rt_uint32_t);
4040
stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
41-
stk = (rt_uint32_t *)stack_addr;
41+
stk = (rt_uint32_t *)stack_addr;
4242

4343
*(--stk) = (rt_uint32_t)tentry; /* entry point */
4444
*(--stk) = (rt_uint32_t)texit; /* lr */

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