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[DM/FEATURE] Support reset controller (#9630)
* [DM/FEATURE] Support reset controller Reset controllers are central units that control the reset signals to multiple peripherals. The reset controller API is split into two parts: 1. The consumer driver interface, which allows peripheral drivers to request control over their reset input signals 2. The reset controller driver interface which is used by drivers for reset controller devices to register their reset controls to provide them to the consumers. * [RESET/SIMPLE] Support simple reset Currently this driver supports: - Altera SoCFPGAs - ASPEED BMC SoCs - Bitmain BM1880 SoC - Realtek SoCs - RCC reset controller in STM32 MCUs - Allwinner SoCs - SiFive FU740 SoCs - Sophgo SoCs Signed-off-by: GuEe-GUI <[email protected]>
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‎components/drivers/Kconfig‎

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@@ -26,6 +26,7 @@ rsource "phye/Kconfig"
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rsource "block/Kconfig"
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rsource "nvme/Kconfig"
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rsource "scsi/Kconfig"
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rsource "reset/Kconfig"
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rsource "virtio/Kconfig"
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rsource "dma/Kconfig"
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rsource "mfd/Kconfig"

‎components/drivers/include/drivers/reset.h‎

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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-11-26 GuEe-GUI first version
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*/
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#ifndef __RESET_H__
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#define __RESET_H__
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#include <rthw.h>
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#include <rtthread.h>
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#include <drivers/ofw.h>
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#define RT_RESET_CONTROLLER_OBJ_NAME "RSTC"
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struct rt_reset_control_ops;
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struct rt_reset_controller
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{
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struct rt_object parent;
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rt_list_t rstc_nodes;
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const char *name;
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const struct rt_reset_control_ops *ops;
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struct rt_ofw_node *ofw_node;
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void *priv;
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struct rt_spinlock spinlock;
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};
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struct rt_reset_control
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{
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rt_list_t list;
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struct rt_reset_controller *rstcer;
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int id;
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const char *con_id;
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rt_bool_t is_array;
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void *priv;
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};
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struct rt_reset_control_ops
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{
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/*
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* rt_ofw_cell_args return:
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* args[0] = rstc.id
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*/
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rt_err_t (*ofw_parse)(struct rt_reset_control *rstc, struct rt_ofw_cell_args *args);
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/* API */
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rt_err_t (*reset)(struct rt_reset_control *rstc);
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rt_err_t (*assert)(struct rt_reset_control *rstc);
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rt_err_t (*deassert)(struct rt_reset_control *rstc);
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int (*status)(struct rt_reset_control *rstc);
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};
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rt_err_t rt_reset_controller_register(struct rt_reset_controller *rstcer);
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rt_err_t rt_reset_controller_unregister(struct rt_reset_controller *rstcer);
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rt_err_t rt_reset_control_reset(struct rt_reset_control *rstc);
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rt_err_t rt_reset_control_assert(struct rt_reset_control *rstc);
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rt_err_t rt_reset_control_deassert(struct rt_reset_control *rstc);
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int rt_reset_control_status(struct rt_reset_control *rstc);
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rt_ssize_t rt_reset_control_get_count(struct rt_device *dev);
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struct rt_reset_control *rt_reset_control_get_array(struct rt_device *dev);
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struct rt_reset_control *rt_reset_control_get_by_index(struct rt_device *dev, int index);
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struct rt_reset_control *rt_reset_control_get_by_name(struct rt_device *dev, const char *name);
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void rt_reset_control_put(struct rt_reset_control *rstc);
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struct rt_reset_control *rt_ofw_get_reset_control_array(struct rt_ofw_node *np);
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struct rt_reset_control *rt_ofw_get_reset_control_by_index(struct rt_ofw_node *np, int index);
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struct rt_reset_control *rt_ofw_get_reset_control_by_name(struct rt_ofw_node *np, const char *name);
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#endif /* __RESET_H__ */

‎components/drivers/include/rtdevice.h‎

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@@ -79,6 +79,10 @@ extern "C" {
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#include "drivers/pic.h"
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#endif /* RT_USING_PIC */
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#ifdef RT_USING_RESET
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#include "drivers/reset.h"
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#endif /* RT_USING_RESET */
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#ifdef RT_USING_SCSI
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#include "drivers/scsi.h"
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#endif /* RT_USING_SCSI */

‎components/drivers/ofw/ofw.c‎

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@@ -71,6 +71,9 @@ static const struct ofw_obj_cmp_list ofw_obj_cmp_list[] =
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{
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#ifdef RT_USING_CLK
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{ "#clock-cells", RT_CLK_NODE_OBJ_NAME, sizeof(struct rt_clk_node) },
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#endif
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#ifdef RT_USING_RESET
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{ "#reset-cells", RT_RESET_CONTROLLER_OBJ_NAME, sizeof(struct rt_reset_controller) },
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#endif
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{ "#power-domain-cells", RT_POWER_DOMAIN_PROXY_OBJ_NAME, sizeof(struct rt_dm_power_domain_proxy) },
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{ "#power-domain-cells", RT_POWER_DOMAIN_OBJ_NAME, sizeof(struct rt_dm_power_domain) },

‎components/drivers/reset/Kconfig‎

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menuconfig RT_USING_RESET
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bool "Using Reset Controller support"
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depends on RT_USING_DM
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depends on RT_USING_OFW
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default n
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config RT_RESET_SIMPLE
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bool "Simple Reset Controller Driver"
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depends on RT_USING_RESET
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default n
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if RT_USING_RESET
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osource "$(SOC_DM_RESET_DIR)/Kconfig"
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endif

‎components/drivers/reset/SConscript‎

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from building import *
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group = []
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if not GetDepend(['RT_USING_RESET']):
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Return('group')
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cwd = GetCurrentDir()
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CPPPATH = [cwd + '/../include']
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src = ['reset.c']
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if GetDepend(['RT_RESET_SIMPLE']):
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src += ['reset-simple.c']
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group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')

‎components/drivers/reset/reset-simple.c‎

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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-11-26 GuEe-GUI first version
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*/
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#include "reset-simple.h"
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struct reset_simple_data
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{
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rt_uint32_t reg_offset;
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rt_bool_t active_low;
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rt_bool_t status_active_low;
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};
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#define raw_to_reset_simple(raw) rt_container_of(raw, struct reset_simple, parent)
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static rt_err_t reset_simple_update(struct reset_simple *rsts, int id, rt_bool_t assert)
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{
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rt_uint32_t reg;
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rt_ubase_t level;
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int reg_width = sizeof(rt_uint32_t);
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int bank = id / (reg_width * 8);
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int offset = id % (reg_width * 8);
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level = rt_spin_lock_irqsave(&rsts->lock);
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reg = HWREG32(rsts->mmio_base + (bank * reg_width));
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if (assert ^ rsts->active_low)
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{
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reg |= RT_BIT(offset);
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}
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else
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{
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reg &= ~RT_BIT(offset);
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}
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HWREG32(rsts->mmio_base + (bank * reg_width)) = reg;
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rt_spin_unlock_irqrestore(&rsts->lock, level);
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return RT_EOK;
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}
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static rt_err_t reset_simple_assert(struct rt_reset_control *rstc)
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{
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struct reset_simple *rsts = raw_to_reset_simple(rstc);
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return reset_simple_update(rsts, rstc->id, RT_TRUE);
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}
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static rt_err_t reset_simple_deassert(struct rt_reset_control *rstc)
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{
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struct reset_simple *rsts = raw_to_reset_simple(rstc);
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return reset_simple_update(rsts, rstc->id, RT_FALSE);
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}
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static rt_err_t reset_simple_reset(struct rt_reset_control *rstc)
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{
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rt_err_t err;
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struct reset_simple *rsts = raw_to_reset_simple(rstc);
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if (!rsts->reset_us)
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{
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return -RT_ENOSYS;
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}
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if ((err = reset_simple_assert(rstc)))
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{
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return err;
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}
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rt_hw_us_delay(rsts->reset_us + (rsts->reset_us >> 1));
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return reset_simple_deassert(rstc);
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}
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static int reset_simple_status(struct rt_reset_control *rstc)
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{
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rt_uint32_t value;
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int reg_width = sizeof(rt_uint32_t);
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int bank = rstc->id / (reg_width * 8);
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int offset = rstc->id % (reg_width * 8);
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struct reset_simple *rsts = raw_to_reset_simple(rstc);
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value = HWREG32(rsts->mmio_base + (bank * reg_width));
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return !(value & RT_BIT(offset)) ^ !rsts->status_active_low;
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}
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const struct rt_reset_control_ops reset_simple_ops =
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{
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.reset = reset_simple_reset,
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.assert = reset_simple_assert,
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.deassert = reset_simple_deassert,
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.status = reset_simple_status,
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};
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static rt_err_t reset_simple_probe(struct rt_platform_device *pdev)
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{
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rt_err_t err;
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struct rt_reset_controller *rstcer;
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struct rt_device *dev = &pdev->parent;
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const struct reset_simple_data *rsts_data = pdev->id->data;
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struct reset_simple *rsts = rt_calloc(1, sizeof(*rsts));
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if (!rsts)
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{
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return -RT_ENOMEM;
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}
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rsts->mmio_base = rt_dm_dev_iomap(dev, 0);
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if (!rsts->mmio_base)
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{
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err = -RT_EIO;
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goto _fail;
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}
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rt_spin_lock_init(&rsts->lock);
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rstcer = &rsts->parent;
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rstcer->priv = rsts;
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rstcer->ofw_node = dev->ofw_node;
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rstcer->ops = &reset_simple_ops;
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if ((err = rt_reset_controller_register(rstcer)))
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{
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goto _fail;
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}
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if (rsts_data)
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{
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rsts->mmio_base += rsts_data->reg_offset;
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rsts->active_low = rsts_data->active_low;
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rsts->status_active_low = rsts_data->status_active_low;
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}
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return RT_EOK;
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_fail:
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if (rsts->mmio_base)
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{
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rt_iounmap(rsts->mmio_base);
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}
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rt_free(rsts);
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return err;
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}
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static const struct reset_simple_data reset_simple_socfpga =
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{
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.reg_offset = 0x20,
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.status_active_low = RT_TRUE,
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};
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static const struct reset_simple_data reset_simple_active_low =
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{
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.active_low = RT_TRUE,
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.status_active_low = RT_TRUE,
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};
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static const struct rt_ofw_node_id reset_simple_ofw_ids[] =
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{
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{ .compatible = "altr,stratix10-rst-mgr", .data = &reset_simple_socfpga },
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{ .compatible = "st,stm32-rcc", },
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{ .compatible = "allwinner,sun6i-a31-clock-reset", .data = &reset_simple_active_low },
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{ .compatible = "zte,zx296718-reset", .data = &reset_simple_active_low },
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{ .compatible = "aspeed,ast2400-lpc-reset" },
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{ .compatible = "aspeed,ast2500-lpc-reset" },
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{ .compatible = "aspeed,ast2600-lpc-reset" },
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{ .compatible = "bitmain,bm1880-reset", .data = &reset_simple_active_low },
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{ .compatible = "brcm,bcm4908-misc-pcie-reset", .data = &reset_simple_active_low },
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{ .compatible = "snps,dw-high-reset" },
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{ .compatible = "snps,dw-low-reset", .data = &reset_simple_active_low },
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{ .compatible = "sophgo,sg2042-reset", .data = &reset_simple_active_low },
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{ /* sentinel */ }
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};
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static struct rt_platform_driver reset_simple_driver =
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{
190+
.name = "reset-simple",
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.ids = reset_simple_ofw_ids,
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.probe = reset_simple_probe,
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};
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static int reset_simple_register(void)
197+
{
198+
rt_platform_driver_register(&reset_simple_driver);
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return 0;
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}
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INIT_SUBSYS_EXPORT(reset_simple_register);

‎components/drivers/reset/reset-simple.h‎

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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*
6+
* Change Logs:
7+
* Date Author Notes
8+
* 2022-11-26 GuEe-GUI first version
9+
*/
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#ifndef __RESET_SIMPLE_H__
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#define __RESET_SIMPLE_H__
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#include <rtthread.h>
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#include <rtdevice.h>
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struct reset_simple
18+
{
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struct rt_reset_controller parent;
20+
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void *mmio_base;
22+
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/*
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* If true, bits are cleared to assert the reset.
25+
* Otherwise, bits are set to assert the reset.
26+
*/
27+
rt_bool_t active_low;
28+
/*
29+
* If true, bits read back as cleared while the reset is asserted.
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* Otherwise, bits read back as set while the reset is asserted.
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*/
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rt_bool_t status_active_low;
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/*
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* Minimum delay in microseconds needed that needs to be
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* waited for between an assert and a deassert to reset the device.
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* If multiple consumers with different delay
38+
* requirements are connected to this controller, it must
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* be the largest minimum delay. 0 means that such a delay is
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* unknown and the reset operation is unsupported.
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*/
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rt_uint32_t reset_us;
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/* protect registers during read-modify-write cycles */
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struct rt_spinlock lock;
46+
};
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extern const struct rt_reset_control_ops reset_simple_ops;
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#endif /* __RESET_SIMPLE_H__ */

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