@@ -20,47 +20,47 @@ struct lpc_adc
2020*/
2121static rt_err_t lpc_adc_enabled (struct rt_adc_device * device , rt_uint32_t channel , rt_bool_t enabled )
2222{
23- struct lpc_adc * adc ;
23+ struct lpc_adc * adc ;
2424
2525 RT_ASSERT (device != RT_NULL );
2626 adc = (struct lpc_adc * )device -> parent .user_data ;
27-
28- //enabled ADC
29- if (enabled == RT_FALSE ) adc -> ADC -> CR &= ~(1 <<21 );
30- else adc -> ADC -> CR |= (1 <<21 );
31-
32- //Select the channel
33- adc -> ADC -> CR |= (1 <<channel );
27+
28+ //enabled ADC
29+ if (enabled == RT_FALSE ) adc -> ADC -> CR &= ~(1 <<21 );
30+ else adc -> ADC -> CR |= (1 <<21 );
31+
32+ //Select the channel
33+ adc -> ADC -> CR |= (1 <<channel );
3434
3535 return RT_EOK ;
3636}
3737
3838static rt_err_t lpc_adc_convert (struct rt_adc_device * device , rt_uint32_t channel , rt_uint32_t * value )
3939{
40- rt_uint32_t data ;
40+ rt_uint32_t data ;
4141
42- struct lpc_adc * adc ;
42+ struct lpc_adc * adc ;
4343
4444 RT_ASSERT (device != RT_NULL );
4545 adc = (struct lpc_adc * )device -> parent .user_data ;
46-
47- adc -> ADC -> CR = (LPC_ADC -> CR & 0x00FFFF00 ) | (1 <<channel ) | (1 << 24 );
48- while ((adc -> ADC -> GDR & 0x80000000 ) == 0 );
49- adc -> ADC -> CR = adc -> ADC -> CR | (1 << 24 );
50- while ((adc -> ADC -> GDR & 0x80000000 ) == 0 );
51-
52- data = adc -> ADC -> GDR ;
53- data = (data >> 4 ) & 0xFFF ;
54-
55- * value = data ;
56-
57- return RT_EOK ;
46+
47+ adc -> ADC -> CR = (LPC_ADC -> CR & 0x00FFFF00 ) | (1 <<channel ) | (1 << 24 );
48+ while ((adc -> ADC -> GDR & 0x80000000 ) == 0 );
49+ adc -> ADC -> CR = adc -> ADC -> CR | (1 << 24 );
50+ while ((adc -> ADC -> GDR & 0x80000000 ) == 0 );
51+
52+ data = adc -> ADC -> GDR ;
53+ data = (data >> 4 ) & 0xFFF ;
54+
55+ * value = data ;
56+
57+ return RT_EOK ;
5858}
5959
6060static const struct rt_adc_ops lpc_adc_ops =
6161{
62- lpc_adc_enabled ,
63- lpc_adc_convert ,
62+ lpc_adc_enabled ,
63+ lpc_adc_convert ,
6464};
6565
6666struct lpc_adc lpc_adc0 =
@@ -72,29 +72,29 @@ struct rt_adc_device adc0;
7272
7373int rt_hw_adc_init (void )
7474{
75- rt_err_t ret = RT_EOK ;
76- struct lpc_adc * adc ;
77-
78- adc = & lpc_adc0 ;
79-
80- adc0 .ops = & lpc_adc_ops ;
81- adc0 .parent .user_data = adc ;
82-
83- //ADC port
84- LPC_IOCON -> P0_23 = 0x01 ; //ADC0[0]
75+ rt_err_t ret = RT_EOK ;
76+ struct lpc_adc * adc ;
77+
78+ adc = & lpc_adc0 ;
79+
80+ adc0 .ops = & lpc_adc_ops ;
81+ adc0 .parent .user_data = adc ;
82+
83+ //ADC port
84+ LPC_IOCON -> P0_23 = 0x01 ; //ADC0[0]
8585 LPC_IOCON -> P0_24 = 0x01 ; //ADC0[1]
8686 LPC_IOCON -> P0_25 = 0x01 ; //ADC0[2]
8787 LPC_IOCON -> P0_26 = 0x01 ; //ADC0[3]
8888 LPC_IOCON -> P1_30 = 0x03 ; //ADC0[4]
8989 LPC_IOCON -> P1_31 = 0x03 ; //ADC0[5]
9090 LPC_IOCON -> P0_12 = 0x03 ; //ADC0[6]
9191 LPC_IOCON -> P0_13 = 0x03 ; //ADC0[7]
92-
93-
94- //clock
95- LPC_SC -> PCONP |= (1U << 12 );
96- //config
97- LPC_ADC -> CR = 0 ;
92+
93+
94+ //clock
95+ LPC_SC -> PCONP |= (1U << 12 );
96+ //config
97+ LPC_ADC -> CR = 0 ;
9898 LPC_ADC -> CR = (1 << 0 )| // SEL
9999 ((PeripheralClock / 1000000 - 1 ) << 8 ) | // CLKDIV = Fpclk / 1000000 - 1
100100 (0 << 16 )| // BURST
@@ -103,12 +103,12 @@ int rt_hw_adc_init(void)
103103 (0 << 22 )| // TEST1
104104 (1 << 24 )| // START
105105 (0 << 27 ); // EDGE
106- //waiting
106+ //waiting
107107 while ((LPC_ADC -> GDR & 0x80000000 ) == 0 );
108108
109- ret = rt_hw_adc_register (& adc0 ,"adc0" ,& lpc_adc_ops ,adc );
110-
111- return ret ;
109+ ret = rt_hw_adc_register (& adc0 ,"adc0" ,& lpc_adc_ops ,adc );
110+
111+ return ret ;
112112}
113113
114114INIT_BOARD_EXPORT (rt_hw_adc_init );
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