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CYFS3CYFS3
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[bsp][gd32]: can add support for GD32F5xx (#10737)
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4 files changed

+65
-12
lines changed

4 files changed

+65
-12
lines changed

‎bsp/gd32/arm/gd32527I-eval/board/Kconfig‎

Lines changed: 43 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -371,6 +371,49 @@ menu "On-chip Peripheral Drivers"
371371
bool "Enable SDRAM"
372372
select RT_USING_SDRAM
373373
default n
374+
375+
menuconfig BSP_USING_CAN
376+
bool "Enable CAN BUS"
377+
default n
378+
select RT_USING_CAN
379+
select RT_USING_DEVICE_IPC
380+
select BSP_USING_GD_DBG
381+
if BSP_USING_CAN
382+
config BSP_USING_CAN0
383+
bool "Enable CAN0"
384+
default n
385+
386+
if BSP_USING_CAN0
387+
choice
388+
prompt "Select CAN0 TX source"
389+
default BSP_CAN0_TX_PH13
390+
391+
config BSP_CAN0_TX_PA12
392+
bool "GPIOA pin 12"
393+
config BSP_CAN0_TX_PB9
394+
bool "GPIOB pin 9"
395+
config BSP_CAN0_TX_PD1
396+
bool "GPIOD pin 1"
397+
config BSP_CAN0_TX_PH13
398+
bool "GPIOH pin 13"
399+
endchoice
400+
401+
choice
402+
prompt "Select CAN0 RX source"
403+
default BSP_CAN0_RX_PI9
404+
405+
config BSP_CAN0_RX_PA11
406+
bool "GPIOA pin 11"
407+
config BSP_CAN0_RX_PB8
408+
bool "GPIOB pin 8"
409+
config BSP_CAN0_RX_PD0
410+
bool "GPIOD pin 0"
411+
config BSP_CAN0_RX_PI9
412+
bool "GPIOI pin 9"
413+
endchoice
414+
endif
415+
416+
endif
374417

375418
source "$(BSP_DIR)/../libraries/gd32_drivers/Kconfig"
376419

‎bsp/gd32/arm/libraries/gd32_drivers/Kconfig‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,3 +24,7 @@ if BSP_USING_USBD
2424
# "ULPI: UTMI+ Low Pin Interface"
2525
endif
2626

27+
config BSP_USING_GD_DBG
28+
bool
29+
default y
30+
# "Using GD32 debug module"

‎bsp/gd32/arm/libraries/gd32_drivers/drv_can.c‎

Lines changed: 16 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@
88
* Change Logs:
99
* Date Author Notes
1010
* 2025-18-03 Dmitriy Chernov first implementation for GD32F4xx
11+
* 2025-09-24 CYFS add support for GD32F5xx
1112
*/
1213

1314
#include "drv_can.h"
@@ -31,7 +32,7 @@ static const struct gd32_baudrate_tbl can_baudrate_tbl[] =
3132
{CAN20kBaud, CAN_BT_SJW_1TQ, CAN_BT_BS1_11TQ, CAN_BT_BS2_2TQ, 150},
3233
{CAN10kBaud, CAN_BT_SJW_1TQ, CAN_BT_BS1_11TQ, CAN_BT_BS2_2TQ, 300},
3334
};
34-
#elif defined(GD32F425) || defined(GD32F427) || defined(GD32F450) /* 50MHz(max) */
35+
#elif defined(GD32F425) || defined(GD32F427) || defined(GD32F450) || defined(GD32F527)/* 50MHz(max) */
3536
static const struct gd32_baudrate_tbl can_baudrate_tbl[] =
3637
{
3738
{CAN1MBaud, CAN_BT_SJW_1TQ, CAN_BT_BS1_8TQ, CAN_BT_BS2_1TQ, 5},
@@ -82,7 +83,9 @@ static const struct gd32_can gd32_can_gpio[] =
8283
#ifdef BSP_USING_CAN0
8384
{
8485
.can_clk = RCU_CAN0,
86+
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx
8587
.alt_func_num = GPIO_AF_9,
88+
#endif
8689
#if defined BSP_CAN0_TX_PA12
8790
.tx_clk = RCU_GPIOA,
8891
.tx_pin = GET_PIN(A, 12),
@@ -119,7 +122,10 @@ static const struct gd32_can gd32_can_gpio[] =
119122
#ifdef BSP_USING_CAN1
120123
{
121124
.can_clk = RCU_CAN1,
125+
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx
122126
.alt_func_num = GPIO_AF_9,
127+
#endif
128+
123129
#if defined BSP_CAN1_TX_PB6
124130
.tx_clk = RCU_GPIOB,
125131
.tx_pin = GET_PIN(B, 6),
@@ -150,7 +156,7 @@ static void gd32_can_gpio_init(void)
150156
rcu_periph_clock_enable(gd32_can_gpio[i].tx_clk);
151157
rcu_periph_clock_enable(gd32_can_gpio[i].rx_clk);
152158

153-
#if defined SOC_SERIES_GD32F4xx
159+
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx
154160
gpio_af_set(PIN_GDPORT(gd32_can_gpio[i].tx_pin), gd32_can_gpio[i].alt_func_num, PIN_GDPIN(gd32_can_gpio[i].tx_pin));
155161
gpio_af_set(PIN_GDPORT(gd32_can_gpio[i].rx_pin), gd32_can_gpio[i].alt_func_num, PIN_GDPIN(gd32_can_gpio[i].rx_pin));
156162

@@ -515,7 +521,7 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
515521
return RT_EOK;
516522
}
517523

518-
static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_num)
524+
static rt_ssize_t _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_num)
519525
{
520526
RT_ASSERT(can);
521527

@@ -605,7 +611,7 @@ static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t
605611
return RT_EOK;
606612
}
607613

608-
static int _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo)
614+
static rt_ssize_t _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo)
609615
{
610616
RT_ASSERT(can);
611617

@@ -656,7 +662,6 @@ static int _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo)
656662
return RT_EOK;
657663
}
658664

659-
660665
static const struct rt_can_ops _can_ops =
661666
{
662667
_can_config,
@@ -735,23 +740,23 @@ static void _can_ewmc_isr(struct rt_can_device *can)
735740
can->status.ackerrcnt++;
736741
if (can_interrupt_flag_get(can_x, CAN_INT_FLAG_MTF0))
737742
{
738-
if (!can_interrupt_flag_get(can_x, CAN_FLAG_MTFNERR0))
743+
if (!can_flag_get(can_x, CAN_FLAG_MTFNERR0))
739744
{
740745
rt_hw_can_isr(can, RT_CAN_EVENT_TX_FAIL | 0 << 8);
741746
}
742747
can_interrupt_flag_clear(can_x, CAN_INT_FLAG_MTF0);
743748
}
744749
else if (can_interrupt_flag_get(can_x, CAN_INT_FLAG_MTF1))
745750
{
746-
if (!can_interrupt_flag_get(can_x, CAN_FLAG_MTFNERR1))
751+
if (!can_flag_get(can_x, CAN_FLAG_MTFNERR1))
747752
{
748753
rt_hw_can_isr(can, RT_CAN_EVENT_TX_FAIL | 1 << 8);
749754
}
750755
can_interrupt_flag_clear(can_x, CAN_INT_FLAG_MTF1);
751756
}
752757
else if (can_interrupt_flag_get(can_x, CAN_INT_FLAG_MTF2))
753758
{
754-
if (!can_interrupt_flag_get(can_x, CAN_FLAG_MTFNERR2))
759+
if (!can_flag_get(can_x, CAN_FLAG_MTFNERR2))
755760
{
756761
rt_hw_can_isr(can, RT_CAN_EVENT_TX_FAIL | 2 << 8);
757762
}
@@ -796,7 +801,7 @@ static void _can_tx_isr(struct rt_can_device *can)
796801

797802
if (can_interrupt_flag_get(can_x, CAN_INT_FLAG_MTF0))
798803
{
799-
if (can_interrupt_flag_get(can_x, CAN_FLAG_MTFNERR0))
804+
if (can_flag_get(can_x, CAN_FLAG_MTFNERR0))
800805
{
801806
rt_hw_can_isr(can, RT_CAN_EVENT_TX_DONE | 0 << 8);
802807
}
@@ -809,7 +814,7 @@ static void _can_tx_isr(struct rt_can_device *can)
809814
}
810815
else if (can_interrupt_flag_get(can_x, CAN_INT_FLAG_MTF1))
811816
{
812-
if (can_interrupt_flag_get(can_x, CAN_FLAG_MTFNERR1))
817+
if (can_flag_get(can_x, CAN_FLAG_MTFNERR1))
813818
{
814819
rt_hw_can_isr(can, RT_CAN_EVENT_TX_DONE | 1 << 8);
815820
}
@@ -822,7 +827,7 @@ static void _can_tx_isr(struct rt_can_device *can)
822827
}
823828
else if (can_interrupt_flag_get(can_x, CAN_INT_FLAG_MTF2))
824829
{
825-
if (can_interrupt_flag_get(can_x, CAN_FLAG_MTFNERR2))
830+
if (can_flag_get(can_x, CAN_FLAG_MTFNERR2))
826831
{
827832
rt_hw_can_isr(can, RT_CAN_EVENT_TX_DONE | 2 << 8);
828833
}

‎bsp/gd32/arm/libraries/gd32_drivers/drv_can.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@
88
* Change Logs:
99
* Date Author Notes
1010
* 2025-18-03 Dmitriy Chernov first implementation
11+
* 2025-09-24 CYFS add support for GD32F5xx
1112
*/
1213

1314
#ifndef __DRV_CAN_H__
@@ -34,7 +35,7 @@ struct gd32_can
3435
rcu_periph_enum can_clk;
3536
rcu_periph_enum tx_clk;
3637
rcu_periph_enum rx_clk;
37-
#if defined SOC_SERIES_GD32F4xx
38+
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx
3839
uint32_t alt_func_num;
3940
#endif
4041
rt_base_t tx_pin;

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